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add imx61 cpufreq and bump to v3.8-rc5

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
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commit d88208009fb7296e2c4341f67e8b1fe6d394f0f2 1 parent 7287e89
Robert Nelson authored January 26, 2013
1  patch.sh
@@ -59,6 +59,7 @@ imx () {
59 59
 	${git} "${DIR}/patches/imx/0001-ARM-imx-Enable-UART1-for-Sabrelite.patch"
60 60
 	${git} "${DIR}/patches/imx/0002-Add-IMX6Q-AHCI-support.patch"
61 61
 	${git} "${DIR}/patches/imx/0003-imx-Add-IMX53-AHCI-support.patch"
  62
+	${git} "${DIR}/patches/imx/0004-cpufreq-add-imx6q-cpufreq-driver.patch"
62 63
 }
63 64
 
64 65
 arm
3  patches/defconfig
... ...
@@ -1,6 +1,6 @@
1 1
 #
2 2
 # Automatically generated file; DO NOT EDIT.
3  
-# Linux/arm 3.8.0-rc4 Kernel Configuration
  3
+# Linux/arm 3.8.0-rc5 Kernel Configuration
4 4
 #
5 5
 CONFIG_ARM=y
6 6
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -569,6 +569,7 @@ CONFIG_GENERIC_CPUFREQ_CPU0=y
569 569
 # CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
570 570
 # CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set
571 571
 # CONFIG_ARM_EXYNOS5250_CPUFREQ is not set
  572
+CONFIG_ARM_IMX6Q_CPUFREQ=y
572 573
 CONFIG_CPU_FREQ_IMX=y
573 574
 CONFIG_CPU_IDLE=y
574 575
 CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
371  patches/imx/0004-cpufreq-add-imx6q-cpufreq-driver.patch
... ...
@@ -0,0 +1,371 @@
  1
+From bd45b3b6ae9f1f780b9e78ce27cc97d8bbe406b7 Mon Sep 17 00:00:00 2001
  2
+From: Shawn Guo <shawn.guo@linaro.org>
  3
+Date: Sat, 26 Jan 2013 23:31:43 +0800
  4
+Subject: [PATCH 4/4] cpufreq: add imx6q-cpufreq driver
  5
+
  6
+Add an imx6q-cpufreq driver for Freescale i.MX6Q SoC to handle the
  7
+hardware specific frequency and voltage scaling requirements.
  8
+
  9
+The driver supports module build and is instantiated by the platform
  10
+device/driver mechanism, so that it will not be instantiated on other
  11
+platforms, as IMX is built with multiplatform support.
  12
+
  13
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
  14
+Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
  15
+Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
  16
+---
  17
+ drivers/cpufreq/Kconfig.arm     |    9 ++
  18
+ drivers/cpufreq/Makefile        |    1 +
  19
+ drivers/cpufreq/imx6q-cpufreq.c |  308 +++++++++++++++++++++++++++++++++++++++
  20
+ 3 files changed, 318 insertions(+)
  21
+ create mode 100644 drivers/cpufreq/imx6q-cpufreq.c
  22
+
  23
+diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
  24
+index a0b3661..9e628ba 100644
  25
+--- a/drivers/cpufreq/Kconfig.arm
  26
++++ b/drivers/cpufreq/Kconfig.arm
  27
+@@ -77,6 +77,15 @@ config ARM_EXYNOS5250_CPUFREQ
  28
+ 	  This adds the CPUFreq driver for Samsung EXYNOS5250
  29
+ 	  SoC.
  30
+ 
  31
++config ARM_IMX6Q_CPUFREQ
  32
++	tristate "Freescale i.MX6Q cpufreq support"
  33
++	depends on SOC_IMX6Q
  34
++	depends on REGULATOR_ANATOP
  35
++	help
  36
++	  This adds cpufreq driver support for Freescale i.MX6Q SOC.
  37
++
  38
++	  If in doubt, say N.
  39
++
  40
+ config ARM_SPEAR_CPUFREQ
  41
+ 	bool "SPEAr CPUFreq support"
  42
+ 	depends on PLAT_SPEAR
  43
+diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
  44
+index fadc4d4..b2bc9c7 100644
  45
+--- a/drivers/cpufreq/Makefile
  46
++++ b/drivers/cpufreq/Makefile
  47
+@@ -50,6 +50,7 @@ obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
  48
+ obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
  49
+ obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
  50
+ obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
  51
++obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o
  52
+ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)     += omap-cpufreq.o
  53
+ obj-$(CONFIG_ARM_SPEAR_CPUFREQ)		+= spear-cpufreq.o
  54
+ 
  55
+diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
  56
+new file mode 100644
  57
+index 0000000..368b6e7
  58
+--- /dev/null
  59
++++ b/drivers/cpufreq/imx6q-cpufreq.c
  60
+@@ -0,0 +1,308 @@
  61
++/*
  62
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
  63
++ *
  64
++ * This program is free software; you can redistribute it and/or modify
  65
++ * it under the terms of the GNU General Public License version 2 as
  66
++ * published by the Free Software Foundation.
  67
++ */
  68
++
  69
++#include <linux/clk.h>
  70
++#include <linux/cpufreq.h>
  71
++#include <linux/delay.h>
  72
++#include <linux/err.h>
  73
++#include <linux/module.h>
  74
++#include <linux/of.h>
  75
++#include <linux/opp.h>
  76
++#include <linux/platform_device.h>
  77
++#include <linux/regulator/consumer.h>
  78
++
  79
++#define PU_SOC_VOLTAGE_NORMAL	1250000
  80
++#define PU_SOC_VOLTAGE_HIGH	1275000
  81
++#define FREQ_1P2_GHZ		1200000000
  82
++
  83
++/*
  84
++ * 1275000 mV - 950000 mV = 325 mV, 325 mV / 25 mV = 13 steps
  85
++ * 512 clock cycles at 24 MHz for one step = 21.33 uS
  86
++ * 21.33 us * 13 = ~280 uS
  87
++ */
  88
++#define MAX_REG_LATENCY		280
  89
++
  90
++static struct regulator *arm_reg;
  91
++static struct regulator *pu_reg;
  92
++static struct regulator *soc_reg;
  93
++
  94
++static struct clk *arm_clk;
  95
++static struct clk *pll1_sys_clk;
  96
++static struct clk *pll1_sw_clk;
  97
++static struct clk *step_clk;
  98
++static struct clk *pll2_pfd2_396m_clk;
  99
++
  100
++static struct device *cpu_dev;
  101
++static struct cpufreq_frequency_table *freq_table;
  102
++static unsigned int transition_latency = MAX_REG_LATENCY;
  103
++
  104
++static int imx6q_verify_speed(struct cpufreq_policy *policy)
  105
++{
  106
++	return cpufreq_frequency_table_verify(policy, freq_table);
  107
++}
  108
++
  109
++static unsigned int imx6q_get_speed(unsigned int cpu)
  110
++{
  111
++	return clk_get_rate(arm_clk) / 1000;
  112
++}
  113
++
  114
++static int imx6q_set_target(struct cpufreq_policy *policy,
  115
++			    unsigned int target_freq, unsigned int relation)
  116
++{
  117
++	struct cpufreq_freqs freqs;
  118
++	struct opp *opp;
  119
++	unsigned long freq_hz, volt, volt_old;
  120
++	unsigned int index, cpu;
  121
++	int ret;
  122
++
  123
++	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  124
++					     relation, &index);
  125
++	if (ret) {
  126
++		dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
  127
++			target_freq, ret);
  128
++		return ret;
  129
++	}
  130
++
  131
++	freqs.new = freq_table[index].frequency;
  132
++	freq_hz = freqs.new * 1000;
  133
++	freqs.old = clk_get_rate(arm_clk) / 1000;
  134
++
  135
++	if (freqs.old == freqs.new)
  136
++		return 0;
  137
++
  138
++	for_each_online_cpu(cpu) {
  139
++		freqs.cpu = cpu;
  140
++		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  141
++	}
  142
++
  143
++	rcu_read_lock();
  144
++	opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
  145
++	if (IS_ERR(opp)) {
  146
++		rcu_read_unlock();
  147
++		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  148
++		return PTR_ERR(opp);
  149
++	}
  150
++
  151
++	volt = opp_get_voltage(opp);
  152
++	rcu_read_unlock();
  153
++	volt_old = regulator_get_voltage(arm_reg);
  154
++
  155
++	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  156
++		freqs.old / 1000, volt_old / 1000,
  157
++		freqs.new / 1000, volt / 1000);
  158
++
  159
++	/* scaling up?  scale voltage before frequency */
  160
++	if (freqs.new > freqs.old) {
  161
++		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  162
++		if (ret) {
  163
++			dev_err(cpu_dev, "failed to scale voltage up: %d\n", ret);
  164
++			return ret;
  165
++		}
  166
++
  167
++		/*
  168
++		 * Need to increase vddpu and vddsoc for safety
  169
++		 * if we are about to run at 1.2 GHz.
  170
++		 */
  171
++		if (freqs.new == FREQ_1P2_GHZ / 1000) {
  172
++			regulator_set_voltage_tol(pu_reg,
  173
++					PU_SOC_VOLTAGE_HIGH, 0);
  174
++			regulator_set_voltage_tol(soc_reg,
  175
++					PU_SOC_VOLTAGE_HIGH, 0);
  176
++		}
  177
++
  178
++		/* Wait for LDOs to ramp up */
  179
++		udelay(MAX_REG_LATENCY);
  180
++	}
  181
++
  182
++	/*
  183
++	 * The setpoints are selected per PLL/PDF frequencies, so we need to
  184
++	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
  185
++	 * PLL1 is as below.
  186
++	 *
  187
++	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
  188
++	 *  - Disable pll1_sys_clk and reprogram it
  189
++	 *  - Enable pll1_sys_clk and reparent pll1_sw_clk back to it
  190
++	 *  - Disable pll2_pfd2_396m_clk
  191
++	 */
  192
++	clk_prepare_enable(pll2_pfd2_396m_clk);
  193
++	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
  194
++	clk_set_parent(pll1_sw_clk, step_clk);
  195
++	clk_prepare_enable(pll1_sys_clk);
  196
++	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
  197
++		clk_disable_unprepare(pll1_sys_clk);
  198
++		clk_set_rate(pll1_sys_clk, freqs.new * 1000);
  199
++		clk_prepare_enable(pll1_sys_clk);
  200
++		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
  201
++		clk_disable_unprepare(pll2_pfd2_396m_clk);
  202
++	} else {
  203
++		/*
  204
++		 * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
  205
++		 * to provide the frequency.
  206
++		 */
  207
++		clk_disable_unprepare(pll1_sys_clk);
  208
++	}
  209
++
  210
++	/* Ensure the arm clock divider is what we expect */
  211
++	ret = clk_set_rate(arm_clk, freqs.new * 1000);
  212
++	if (ret) {
  213
++		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
  214
++		regulator_set_voltage_tol(arm_reg, volt_old, 0);
  215
++		return ret;
  216
++	}
  217
++
  218
++	/* scaling down?  scale voltage after frequency */
  219
++	if (freqs.new < freqs.old) {
  220
++		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  221
++		if (ret)
  222
++			dev_warn(cpu_dev, "failed to scale voltage down: %d\n", ret);
  223
++
  224
++		if (freqs.old == FREQ_1P2_GHZ / 1000) {
  225
++			regulator_set_voltage_tol(pu_reg,
  226
++					PU_SOC_VOLTAGE_NORMAL, 0);
  227
++			regulator_set_voltage_tol(soc_reg,
  228
++					PU_SOC_VOLTAGE_NORMAL, 0);
  229
++		}
  230
++	}
  231
++
  232
++	for_each_online_cpu(cpu) {
  233
++		freqs.cpu = cpu;
  234
++		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  235
++	}
  236
++
  237
++	return 0;
  238
++}
  239
++
  240
++static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
  241
++{
  242
++	int ret;
  243
++
  244
++	ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
  245
++	if (ret) {
  246
++		dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
  247
++		return ret;
  248
++	}
  249
++
  250
++	policy->cpuinfo.transition_latency = transition_latency;
  251
++	policy->cur = clk_get_rate(arm_clk) / 1000;
  252
++	policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
  253
++	cpumask_setall(policy->cpus);
  254
++	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
  255
++
  256
++	return 0;
  257
++}
  258
++
  259
++static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
  260
++{
  261
++	cpufreq_frequency_table_put_attr(policy->cpu);
  262
++	return 0;
  263
++}
  264
++
  265
++static struct freq_attr *imx6q_cpufreq_attr[] = {
  266
++	&cpufreq_freq_attr_scaling_available_freqs,
  267
++	NULL,
  268
++};
  269
++
  270
++static struct cpufreq_driver imx6q_cpufreq_driver = {
  271
++	.verify = imx6q_verify_speed,
  272
++	.target = imx6q_set_target,
  273
++	.get = imx6q_get_speed,
  274
++	.init = imx6q_cpufreq_init,
  275
++	.exit = imx6q_cpufreq_exit,
  276
++	.name = "imx6q-cpufreq",
  277
++	.attr = imx6q_cpufreq_attr,
  278
++};
  279
++
  280
++static int imx6q_cpufreq_probe(struct platform_device *pdev)
  281
++{
  282
++	struct device_node *np;
  283
++	int ret;
  284
++
  285
++	cpu_dev = &pdev->dev;
  286
++
  287
++	np = of_find_node_by_path("/cpus/cpu@0");
  288
++	if (!np) {
  289
++		dev_err(cpu_dev, "failed to find cpu0 node\n");
  290
++		return -ENOENT;
  291
++	}
  292
++
  293
++	cpu_dev->of_node = np;
  294
++
  295
++	arm_clk = devm_clk_get(cpu_dev, "arm");
  296
++	pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
  297
++	pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
  298
++	step_clk = devm_clk_get(cpu_dev, "step");
  299
++	pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
  300
++	if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
  301
++	    IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
  302
++		dev_err(cpu_dev, "failed to get clocks\n");
  303
++		ret = -ENOENT;
  304
++		goto put_node;
  305
++	}
  306
++
  307
++	arm_reg = devm_regulator_get(cpu_dev, "arm");
  308
++	pu_reg = devm_regulator_get(cpu_dev, "pu");
  309
++	soc_reg = devm_regulator_get(cpu_dev, "soc");
  310
++	if (!arm_reg || !pu_reg || !soc_reg) {
  311
++		dev_err(cpu_dev, "failed to get regulators\n");
  312
++		ret = -ENOENT;
  313
++		goto put_node;
  314
++	}
  315
++
  316
++	/* We expect an OPP table supplied by platform */
  317
++	ret = opp_get_opp_count(cpu_dev);
  318
++	if (ret < 0) {
  319
++		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
  320
++		goto put_node;
  321
++	}
  322
++
  323
++	ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
  324
++	if (ret) {
  325
++		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
  326
++		goto put_node;
  327
++	}
  328
++
  329
++	if (of_property_read_u32(np, "clock-latency", &transition_latency))
  330
++		transition_latency = CPUFREQ_ETERNAL;
  331
++
  332
++	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
  333
++	if (ret) {
  334
++		dev_err(cpu_dev, "failed register driver: %d\n", ret);
  335
++		goto free_freq_table;
  336
++	}
  337
++
  338
++	of_node_put(np);
  339
++	return 0;
  340
++
  341
++free_freq_table:
  342
++	opp_free_cpufreq_table(cpu_dev, &freq_table);
  343
++put_node:
  344
++	of_node_put(np);
  345
++	return ret;
  346
++}
  347
++
  348
++static int imx6q_cpufreq_remove(struct platform_device *pdev)
  349
++{
  350
++	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
  351
++	opp_free_cpufreq_table(cpu_dev, &freq_table);
  352
++
  353
++	return 0;
  354
++}
  355
++
  356
++static struct platform_driver imx6q_cpufreq_platdrv = {
  357
++	.driver = {
  358
++		.name	= "imx6q-cpufreq",
  359
++		.owner	= THIS_MODULE,
  360
++	},
  361
++	.probe		= imx6q_cpufreq_probe,
  362
++	.remove		= imx6q_cpufreq_remove,
  363
++};
  364
++module_platform_driver(imx6q_cpufreq_platdrv);
  365
++
  366
++MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  367
++MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
  368
++MODULE_LICENSE("GPL");
  369
+-- 
  370
+1.7.10.4
  371
+
2  patches/ref_imx_v6_v7_defconfig
... ...
@@ -1,6 +1,6 @@
1 1
 #
2 2
 # Automatically generated file; DO NOT EDIT.
3  
-# Linux/arm 3.8.0-rc4 Kernel Configuration
  3
+# Linux/arm 3.8.0-rc5 Kernel Configuration
4 4
 #
5 5
 CONFIG_ARM=y
6 6
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
4  version.sh
@@ -23,8 +23,8 @@ config="imx_v6_v7_defconfig"
23 23
 
24 24
 #Kernel/Build
25 25
 KERNEL_REL=3.8
26  
-KERNEL_TAG=${KERNEL_REL}-rc4
27  
-BUILD=imx0.2
  26
+KERNEL_TAG=${KERNEL_REL}-rc5
  27
+BUILD=imx0.3
28 28
 
29 29
 #v3.X-rcX + upto SHA
30 30
 #KERNEL_SHA=""

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