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# This is a sample PCRAM configuration with mats organized and routed in bus-manner
# instead of traditional H-tree. The sense amps are placed outside the mats.
# The structure is similar to the design in "A 0.1um 1.8V 256Mb phase-change random
# access memory with 66MHz synchronous burst read operation", JSSC 2007
-DesignTarget: RAM
-ProcessNode: 90
-Capacity (MB): 16
-WordWidth (bit): 64
-DeviceRoadmap: LOP
-LocalWireType: LocalConservative
-LocalWireRepeaterType: RepeatedNone
-LocalWireUseLowSwing: No
-GlobalWireType: LocalConservative
-GlobalWireRepeaterType: RepeatedNone
-GlobalWireUseLowSwing: No
-Routing: non-H-tree
-InternalSensing: false
-MemoryCellInputFile: sample_PCRAM.cell
-Temperature (K): 340
-Optimization: latency
-BufferDesignOptimization: latency
-ForceBank (Total AxB, Active CxD): 8x4, 1x1
-ForceMat (Total AxB, Active CxD): 1x4, 1x4
-ForceMuxSenseAmp: 8
-ForceMuxOutputLev1: 8
-ForceMuxOutputLev2: 1