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92ea4e7 Feb 11, 2013
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# This sample STTRAM configuration tries to explore a limited design space
# of a 22nm STT-RAM based L3 cache with a balanced design optimization.
-DesignTarget: cache
//-CacheAccessMode: Normal
//-CacheAccessMode: Fast
-CacheAccessMode: Sequential
//-OptimizationTarget: ReadLatency
//-OptimizationTarget: WriteLatency
//-OptimizationTarget: ReadDynamicEnergy
//-OptimizationTarget: WriteDynamicEnergy
-OptimizationTarget: ReadEDP
//-OptimizationTarget: WriteEDP
//-OptimizationTarget: LeakagePower
//-OptimizationTarget: Area
//-OptimizationTarget: Exploration
//-OutputFilePrefix: sttram_l3_cache
-EnablePruning: Yes
-ProcessNode: 22
//-Capacity (KB): 128
-Capacity (MB): 8
-WordWidth (bit): 512
-Associativity (for cache only): 16
-DeviceRoadmap: HP
//-DeviceRoadmap: LSTP
//-DeviceRoadmap: LOP
-LocalWireType: LocalAggressive
//-LocalWireType: LocalConservative
//-LocalWireType: SemiAggressive
//-LocalWireType: SemiConservative
//-LocalWireType: GlobalAggressive
//-LocalWireType: GlobalConservative
-LocalWireRepeaterType: RepeatedNone
//-LocalWireRepeaterType: RepeatedOpt
//-LocalWireRepeaterType: Repeated5%Penalty
//-LocalWireRepeaterType: Repeated10%Penalty
//-LocalWireRepeaterType: Repeated20%Penalty
//-LocalWireRepeaterType: Repeated30%Penalty
//-LocalWireRepeaterType: Repeated40%Penalty
//-LocalWireRepeaterType: Repeated50%Penalty
//-LocalWireUseLowSwing: Yes
-LocalWireUseLowSwing: No
//-GlobalWireType: LocalAggressive
//-GlobalWireType: LocalConservative
//-GlobalWireType: SemiAggressive
//-GlobalWireType: SemiConservative
-GlobalWireType: GlobalAggressive
//-GlobalWireType: GlobalConservative
-GlobalWireRepeaterType: RepeatedNone
//-GlobalWireRepeaterType: RepeatedOpt
//-GlobalWireRepeaterType: Repeated5%Penalty
//-GlobalWireRepeaterType: Repeated10%Penalty
//-GlobalWireRepeaterType: Repeated20%Penalty
//-GlobalWireRepeaterType: Repeated30%Penalty
//-GlobalWireRepeaterType: Repeated40%Penalty
//-GlobalWireRepeaterType: Repeated50%Penalty
//-GlobalWireUseLowSwing: Yes
-GlobalWireUseLowSwing: No
-Routing: H-tree
-InternalSensing: true
-MemoryCellInputFile: sample_STTRAM.cell
-Temperature (K): 350
-BufferDesignOptimization: latency
//-BufferDesignOptimization: area
//-BufferDesignOptimization: balance
//-ForceBank (Total AxB, Active CxD): 8x8, 1x8
//-ForceMat (Total AxB, Active CxD): 2x2, 1x2
//-ForceMuxSenseAmp: 16
//-ForceMuxOutputLev1: 1
//-ForceMuxOutputLev2: 1
-UseCactiAssumption: Yes
//-ApplyReadLatencyConstraint: 37.4
//-ApplyWriteLatencyConstraint: 0.5
//-ApplyReadDynamicEnergyConstraint: 0.5
//-ApplyWriteDynamicEnergyConstraint: 0.5
//-ApplyLeakageConstraint: 0.5
//-ApplyAreaConstraint: 1
//-ApplyReadEdpConstraint: 0.5
//-ApplyWriteEdpConstraint: 0.5