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fix the unix format error

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cxxz committed Feb 11, 2013
1 parent f26661f commit 92ea4e71963595ac40c970426bb29e5ca1492f7b
Showing with 6,593 additions and 6,593 deletions.
  1. +89 −89 Bank.cpp
  2. +84 −84 Bank.h
  3. +661 −661 BankWithHtree.cpp
  4. +76 −76 BankWithHtree.h
  5. +463 −463 BankWithoutHtree.cpp
  6. +69 −69 BankWithoutHtree.h
  7. +32 −32 BasicDecoder.cpp
  8. +32 −32 BasicDecoder.h
  9. +202 −202 Comparator.cpp
  10. +68 −68 Comparator.h
  11. +32 −32 FunctionUnit.cpp
  12. +32 −32 FunctionUnit.h
  13. +629 −629 InputParameter.cpp
  14. +130 −130 InputParameter.h
  15. +32 −32 Mat.cpp
  16. +32 −32 Mat.h
  17. +32 −32 MemCell.cpp
  18. +32 −32 MemCell.h
  19. +173 −173 Mux.cpp
  20. +70 −70 Mux.h
  21. +32 −32 OutputDriver.cpp
  22. +32 −32 OutputDriver.h
  23. +32 −32 Precharger.cpp
  24. +32 −32 Precharger.h
  25. +32 −32 PredecodeBlock.cpp
  26. +32 −32 PredecodeBlock.h
  27. +32 −32 Result.cpp
  28. +32 −32 Result.h
  29. +32 −32 RowDecoder.cpp
  30. +32 −32 RowDecoder.h
  31. +40 −40 SRAM.cell
  32. +228 −228 SenseAmp.cpp
  33. +63 −63 SenseAmp.h
  34. +941 −941 SubArray.cpp
  35. +109 −109 SubArray.h
  36. +32 −32 Technology.cpp
  37. +32 −32 Technology.h
  38. +817 −817 Wire.cpp
  39. +89 −89 Wire.h
  40. +32 −32 constant.h
  41. +32 −32 formula.cpp
  42. +32 −32 formula.h
  43. +32 −32 global.h
  44. +336 −336 macros.h
  45. +32 −32 main.cpp
  46. +111 −111 nvsim.cfg
  47. +28 −28 sample_PCRAM.cell
  48. +38 −38 sample_PCRAM.cfg
  49. +36 −36 sample_RRAM.cell
  50. +34 −34 sample_RRAM.cfg
  51. +15 −15 sample_SLCNAND.cell
  52. +26 −26 sample_SLCNAND.cfg
  53. +99 −99 sample_STTRAM_cache.cfg
  54. +37 −37 sample_STTRAM_macro.cfg
  55. +32 −32 typedef.h
View
178 Bank.cpp
@@ -1,93 +1,93 @@
/*******************************************************************************
* Copyright (c) 2012-2013, The Microsystems Design Labratory (MDL)
/*******************************************************************************
* Copyright (c) 2012-2013, The Microsystems Design Labratory (MDL)
* Department of Computer Science and Engineering, The Pennsylvania State University
* Exascale Computing Lab, Hewlett-Packard Company
* All rights reserved.
*
* Exascale Computing Lab, Hewlett-Packard Company
* All rights reserved.
*
* This source code is part of NVSim - An area, timing and power model for both
* volatile (e.g., SRAM, DRAM) and non-volatile memory (e.g., PCRAM, STT-RAM, ReRAM,
* SLC NAND Flash). The source code is free and you can redistribute and/or modify it
* by providing that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author list:
* Cong Xu ( Email: czx102 at psu dot edu
* Website: http://www.cse.psu.edu/~czx102/ )
* Xiangyu Dong ( Email: xydong at cse dot psu dot edu
* Website: http://www.cse.psu.edu/~xydong/ )
*******************************************************************************/
#include "Bank.h"
Bank::Bank() {
// TODO Auto-generated constructor stub
initialized = false;
invalid = false;
}
Bank::~Bank() {
// TODO Auto-generated destructor stub
}
void Bank::PrintProperty() {
cout << "Bank Properties:" << endl;
FunctionUnit::PrintProperty();
}
Bank & Bank::operator=(const Bank &rhs) {
height = rhs.height;
width = rhs.width;
area = rhs.area;
readLatency = rhs.readLatency;
writeLatency = rhs.writeLatency;
readDynamicEnergy = rhs.readDynamicEnergy;
writeDynamicEnergy = rhs.writeDynamicEnergy;
resetLatency = rhs.resetLatency;
setLatency = rhs.setLatency;
resetDynamicEnergy = rhs.resetDynamicEnergy;
setDynamicEnergy = rhs.setDynamicEnergy;
cellReadEnergy = rhs.cellReadEnergy;
cellSetEnergy = rhs.cellSetEnergy;
cellResetEnergy = rhs.cellResetEnergy;
leakage = rhs.leakage;
initialized = rhs.initialized;
invalid = rhs.invalid;
numRowMat = rhs.numRowMat;
numColumnMat = rhs.numColumnMat;
capacity = rhs.capacity;
blockSize = rhs.blockSize;
associativity = rhs.associativity;
numRowPerSet = rhs.numRowPerSet;
numActiveMatPerRow = rhs.numActiveMatPerRow;
numActiveMatPerColumn = rhs.numActiveMatPerColumn;
muxSenseAmp = rhs.muxSenseAmp;
internalSenseAmp = rhs.internalSenseAmp;
muxOutputLev1 = rhs.muxOutputLev1;
muxOutputLev2 = rhs.muxOutputLev2;
areaOptimizationLevel = rhs.areaOptimizationLevel;
memoryType = rhs.memoryType;
numRowSubarray = rhs.numRowSubarray;
numColumnSubarray = rhs.numColumnSubarray;
numActiveSubarrayPerRow = rhs.numActiveSubarrayPerRow;
numActiveSubarrayPerColumn = rhs.numActiveSubarrayPerColumn;
mat = rhs.mat;
return *this;
}
* by providing that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author list:
* Cong Xu ( Email: czx102 at psu dot edu
* Website: http://www.cse.psu.edu/~czx102/ )
* Xiangyu Dong ( Email: xydong at cse dot psu dot edu
* Website: http://www.cse.psu.edu/~xydong/ )
*******************************************************************************/
#include "Bank.h"
Bank::Bank() {
// TODO Auto-generated constructor stub
initialized = false;
invalid = false;
}
Bank::~Bank() {
// TODO Auto-generated destructor stub
}
void Bank::PrintProperty() {
cout << "Bank Properties:" << endl;
FunctionUnit::PrintProperty();
}
Bank & Bank::operator=(const Bank &rhs) {
height = rhs.height;
width = rhs.width;
area = rhs.area;
readLatency = rhs.readLatency;
writeLatency = rhs.writeLatency;
readDynamicEnergy = rhs.readDynamicEnergy;
writeDynamicEnergy = rhs.writeDynamicEnergy;
resetLatency = rhs.resetLatency;
setLatency = rhs.setLatency;
resetDynamicEnergy = rhs.resetDynamicEnergy;
setDynamicEnergy = rhs.setDynamicEnergy;
cellReadEnergy = rhs.cellReadEnergy;
cellSetEnergy = rhs.cellSetEnergy;
cellResetEnergy = rhs.cellResetEnergy;
leakage = rhs.leakage;
initialized = rhs.initialized;
invalid = rhs.invalid;
numRowMat = rhs.numRowMat;
numColumnMat = rhs.numColumnMat;
capacity = rhs.capacity;
blockSize = rhs.blockSize;
associativity = rhs.associativity;
numRowPerSet = rhs.numRowPerSet;
numActiveMatPerRow = rhs.numActiveMatPerRow;
numActiveMatPerColumn = rhs.numActiveMatPerColumn;
muxSenseAmp = rhs.muxSenseAmp;
internalSenseAmp = rhs.internalSenseAmp;
muxOutputLev1 = rhs.muxOutputLev1;
muxOutputLev2 = rhs.muxOutputLev2;
areaOptimizationLevel = rhs.areaOptimizationLevel;
memoryType = rhs.memoryType;
numRowSubarray = rhs.numRowSubarray;
numColumnSubarray = rhs.numColumnSubarray;
numActiveSubarrayPerRow = rhs.numActiveSubarrayPerRow;
numActiveSubarrayPerColumn = rhs.numActiveSubarrayPerColumn;
mat = rhs.mat;
return *this;
}
View
168 Bank.h
@@ -1,88 +1,88 @@
/*******************************************************************************
* Copyright (c) 2012-2013, The Microsystems Design Labratory (MDL)
/*******************************************************************************
* Copyright (c) 2012-2013, The Microsystems Design Labratory (MDL)
* Department of Computer Science and Engineering, The Pennsylvania State University
* Exascale Computing Lab, Hewlett-Packard Company
* All rights reserved.
*
* Exascale Computing Lab, Hewlett-Packard Company
* All rights reserved.
*
* This source code is part of NVSim - An area, timing and power model for both
* volatile (e.g., SRAM, DRAM) and non-volatile memory (e.g., PCRAM, STT-RAM, ReRAM,
* SLC NAND Flash). The source code is free and you can redistribute and/or modify it
* by providing that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author list:
* Cong Xu ( Email: czx102 at psu dot edu
* Website: http://www.cse.psu.edu/~czx102/ )
* Xiangyu Dong ( Email: xydong at cse dot psu dot edu
* Website: http://www.cse.psu.edu/~xydong/ )
*******************************************************************************/
#ifndef BANK_H_
#define BANK_H_
#include "FunctionUnit.h"
#include "Mat.h"
#include "typedef.h"
class Bank: public FunctionUnit {
public:
Bank();
virtual ~Bank();
/* Functions */
void PrintProperty();
virtual void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType) = 0;
virtual void CalculateArea() = 0;
virtual void CalculateRC() = 0;
virtual void CalculateLatencyAndPower() = 0;
virtual Bank & operator=(const Bank &);
/* Properties */
bool initialized; /* Initialization flag */
bool invalid; /* Indicate that the current configuration is not valid, pass down to all the sub-components */
bool internalSenseAmp;
int numRowMat; /* Number of mat rows in a bank */
int numColumnMat; /* Number of mat columns in a bank */
long long capacity; /* The capacity of this bank, Unit: bit */
long blockSize; /* The basic block size in this bank, Unit: bit */
int associativity; /* Associativity, for cache design only */
int numRowPerSet; /* For cache design, the number of wordlines which a set is partitioned into */
int numActiveMatPerRow; /* For different access types */
int numActiveMatPerColumn; /* For different access types */
int muxSenseAmp; /* How many bitlines connect to one sense amplifier */
int muxOutputLev1; /* How many sense amplifiers connect to one output bit, level-1 */
int muxOutputLev2; /* How many sense amplifiers connect to one output bit, level-2 */
int numRowSubarray; /* Number of subarray rows in a mat */
int numColumnSubarray; /* Number of subarray columns in a mat */
int numActiveSubarrayPerRow; /* For different access types */
int numActiveSubarrayPerColumn; /* For different access types */
BufferDesignTarget areaOptimizationLevel;
MemoryType memoryType;
Mat mat;
};
#endif /* BANK_H_ */
* by providing that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author list:
* Cong Xu ( Email: czx102 at psu dot edu
* Website: http://www.cse.psu.edu/~czx102/ )
* Xiangyu Dong ( Email: xydong at cse dot psu dot edu
* Website: http://www.cse.psu.edu/~xydong/ )
*******************************************************************************/
#ifndef BANK_H_
#define BANK_H_
#include "FunctionUnit.h"
#include "Mat.h"
#include "typedef.h"
class Bank: public FunctionUnit {
public:
Bank();
virtual ~Bank();
/* Functions */
void PrintProperty();
virtual void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType) = 0;
virtual void CalculateArea() = 0;
virtual void CalculateRC() = 0;
virtual void CalculateLatencyAndPower() = 0;
virtual Bank & operator=(const Bank &);
/* Properties */
bool initialized; /* Initialization flag */
bool invalid; /* Indicate that the current configuration is not valid, pass down to all the sub-components */
bool internalSenseAmp;
int numRowMat; /* Number of mat rows in a bank */
int numColumnMat; /* Number of mat columns in a bank */
long long capacity; /* The capacity of this bank, Unit: bit */
long blockSize; /* The basic block size in this bank, Unit: bit */
int associativity; /* Associativity, for cache design only */
int numRowPerSet; /* For cache design, the number of wordlines which a set is partitioned into */
int numActiveMatPerRow; /* For different access types */
int numActiveMatPerColumn; /* For different access types */
int muxSenseAmp; /* How many bitlines connect to one sense amplifier */
int muxOutputLev1; /* How many sense amplifiers connect to one output bit, level-1 */
int muxOutputLev2; /* How many sense amplifiers connect to one output bit, level-2 */
int numRowSubarray; /* Number of subarray rows in a mat */
int numColumnSubarray; /* Number of subarray columns in a mat */
int numActiveSubarrayPerRow; /* For different access types */
int numActiveSubarrayPerColumn; /* For different access types */
BufferDesignTarget areaOptimizationLevel;
MemoryType memoryType;
Mat mat;
};
#endif /* BANK_H_ */
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