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ASCII logging at 115200 baud drops packets about every 176144 bytes.

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0 parents commit 388e3835286c3f0fa9c735416281eaf713a5cef8 unknown committed Oct 18, 2010
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  1. BIN FW.SFE
  2. +85 −0 LPCUSB/armVIC.c
  3. +157 −0 LPCUSB/armVIC.h
  4. +10 −0 LPCUSB/blockdev.h
  5. +360 −0 LPCUSB/blockdev_sd.c
  6. +149 −0 LPCUSB/lpc2000_spi.c
  7. +205 −0 LPCUSB/main_msc.c
  8. +1 −0 LPCUSB/main_msc.h
  9. +467 −0 LPCUSB/main_serial.c
  10. +5 −0 LPCUSB/main_serial.h
  11. +418 −0 LPCUSB/msc_bot.c
  12. +9 −0 LPCUSB/msc_bot.h
  13. +333 −0 LPCUSB/msc_scsi.c
  14. +5 −0 LPCUSB/msc_scsi.h
  15. +85 −0 LPCUSB/serial_fifo.c
  16. +42 −0 LPCUSB/serial_fifo.h
  17. +44 −0 LPCUSB/spi.h
  18. +57 −0 LPCUSB/type.h
  19. +121 −0 LPCUSB/usbapi.h
  20. +232 −0 LPCUSB/usbcontrol.c
  21. +38 −0 LPCUSB/usbdebug.h
  22. +560 −0 LPCUSB/usbhw_lpc.c
  23. +182 −0 LPCUSB/usbhw_lpc.h
  24. +82 −0 LPCUSB/usbinit.c
  25. +433 −0 LPCUSB/usbstdreq.c
  26. +120 −0 LPCUSB/usbstruct.h
  27. +516 −0 Main/Makefile
  28. +581 −0 Main/Startup.S
  29. BIN Main/lpc21isp
  30. +1,323 −0 Main/main.c
  31. +158 −0 Main/main_memory_block.ld
  32. +399 −0 lib/LPC214x.h
  33. +383 −0 lib/LPC21xx.h
  34. +1,947 −0 lib/fat16.c
  35. +152 −0 lib/fat16.h
  36. +33 −0 lib/fat16_config.h
  37. +188 −0 lib/firmware.c
  38. +2 −0 lib/firmware.h
  39. +164 −0 lib/iap_flash.c
  40. +40 −0 lib/iap_flash.h
  41. +160 −0 lib/irq.c
  42. +127 −0 lib/irq.h
  43. +19 −0 lib/itoa.c
  44. +2 −0 lib/itoa.h
  45. +120 −0 lib/partition.c
  46. +161 −0 lib/partition.h
  47. +222 −0 lib/rootdir.c
  48. +21 −0 lib/rootdir.h
  49. +250 −0 lib/rprintf.c
  50. +7 −0 lib/rprintf.h
  51. +972 −0 lib/sd_raw.c
  52. +135 −0 lib/sd_raw.h
  53. +97 −0 lib/sd_raw_config.h
  54. +99 −0 lib/serial.c
  55. +13 −0 lib/serial.h
  56. +271 −0 lib/string_printf.c
  57. +4 −0 lib/string_printf.h
  58. +143 −0 lib/syscalls.c
  59. +44 −0 lib/target.h
  60. +32 −0 lib/type.h
  61. +162 −0 lib/uart.c
  62. +48 −0 lib/uart.h
BIN FW.SFE
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+/******************************************************************************
+ *
+ * $RCSfile$
+ * $Revision: 124 $
+ *
+ * This module provides the interface routines for setting up and
+ * controlling the various interrupt modes present on the ARM processor.
+ * Copyright 2004, R O SoftWare
+ * No guarantees, warrantees, or promises, implied or otherwise.
+ * May be used for hobby or commercial purposes provided copyright
+ * notice remains intact.
+ *
+ *****************************************************************************/
+#include "type.h"
+#include "armVIC.h"
+
+#define IRQ_MASK 0x00000080
+#define FIQ_MASK 0x00000040
+#define INT_MASK (IRQ_MASK | FIQ_MASK)
+
+static inline unsigned __get_cpsr(void)
+{
+ unsigned long retval;
+ asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
+ return retval;
+}
+
+static inline void __set_cpsr(unsigned val)
+{
+ asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
+}
+
+unsigned disableIRQ(void)
+{
+ unsigned _cpsr;
+
+ _cpsr = __get_cpsr();
+ __set_cpsr(_cpsr | IRQ_MASK);
+ return _cpsr;
+}
+
+unsigned restoreIRQ(unsigned oldCPSR)
+{
+ unsigned _cpsr;
+
+ _cpsr = __get_cpsr();
+ __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK));
+ return _cpsr;
+}
+
+unsigned enableIRQ(void)
+{
+ unsigned _cpsr;
+
+ _cpsr = __get_cpsr();
+ __set_cpsr(_cpsr & ~IRQ_MASK);
+ return _cpsr;
+}
+
+unsigned disableFIQ(void)
+{
+ unsigned _cpsr;
+
+ _cpsr = __get_cpsr();
+ __set_cpsr(_cpsr | FIQ_MASK);
+ return _cpsr;
+}
+
+unsigned restoreFIQ(unsigned oldCPSR)
+{
+ unsigned _cpsr;
+
+ _cpsr = __get_cpsr();
+ __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK));
+ return _cpsr;
+}
+
+unsigned enableFIQ(void)
+{
+ unsigned _cpsr;
+
+ _cpsr = __get_cpsr();
+ __set_cpsr(_cpsr & ~FIQ_MASK);
+ return _cpsr;
+}
@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * $RCSfile$
+ * $Revision: 124 $
+ *
+ * This module provides the interface definitions for setting up and
+ * controlling the various interrupt modes present on the ARM processor.
+ * Copyright 2004, R O SoftWare
+ * No guarantees, warrantees, or promises, implied or otherwise.
+ * May be used for hobby or commercial purposes provided copyright
+ * notice remains intact.
+ *
+ *****************************************************************************/
+#ifndef INC_ARM_VIC_H
+#define INC_ARM_VIC_H
+
+/******************************************************************************
+ *
+ * MACRO Name: ISR_ENTRY()
+ *
+ * Description:
+ * This MACRO is used upon entry to an ISR. The current version of
+ * the gcc compiler for ARM does not produce correct code for
+ * interrupt routines to operate properly with THUMB code. The MACRO
+ * performs the following steps:
+ *
+ * 1 - Adjust address at which execution should resume after servicing
+ * ISR to compensate for IRQ entry
+ * 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
+ * 3 - Get the status of the interrupted program is in SPSR.
+ * 4 - Push it onto the IRQ stack as well.
+ *
+ *****************************************************************************/
+#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \
+ " stmfd sp!,{r0-r12,lr}\n" \
+ " mrs r1, spsr\n" \
+ " stmfd sp!,{r1}")
+
+/******************************************************************************
+ *
+ * MACRO Name: ISR_EXIT()
+ *
+ * Description:
+ * This MACRO is used to exit an ISR. The current version of the gcc
+ * compiler for ARM does not produce correct code for interrupt
+ * routines to operate properly with THUMB code. The MACRO performs
+ * the following steps:
+ *
+ * 1 - Recover SPSR value from stack
+ * 2 - and restore its value
+ * 3 - Pop the return address & the saved general registers from
+ * the IRQ stack & return
+ *
+ *****************************************************************************/
+#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \
+ " msr spsr_c,r1\n" \
+ " ldmfd sp!,{r0-r12,pc}^")
+
+/******************************************************************************
+ *
+ * Function Name: disableIRQ()
+ *
+ * Description:
+ * This function sets the IRQ disable bit in the status register
+ *
+ * Calling Sequence:
+ * void
+ *
+ * Returns:
+ * previous value of CPSR
+ *
+ *****************************************************************************/
+unsigned disableIRQ(void);
+
+/******************************************************************************
+ *
+ * Function Name: enableIRQ()
+ *
+ * Description:
+ * This function clears the IRQ disable bit in the status register
+ *
+ * Calling Sequence:
+ * void
+ *
+ * Returns:
+ * previous value of CPSR
+ *
+ *****************************************************************************/
+unsigned enableIRQ(void);
+
+/******************************************************************************
+ *
+ * Function Name: restoreIRQ()
+ *
+ * Description:
+ * This function restores the IRQ disable bit in the status register
+ * to the value contained within passed oldCPSR
+ *
+ * Calling Sequence:
+ * void
+ *
+ * Returns:
+ * previous value of CPSR
+ *
+ *****************************************************************************/
+unsigned restoreIRQ(unsigned oldCPSR);
+
+/******************************************************************************
+ *
+ * Function Name: disableFIQ()
+ *
+ * Description:
+ * This function sets the FIQ disable bit in the status register
+ *
+ * Calling Sequence:
+ * void
+ *
+ * Returns:
+ * previous value of CPSR
+ *
+ *****************************************************************************/
+unsigned disableFIQ(void);
+
+/******************************************************************************
+ *
+ * Function Name: enableFIQ()
+ *
+ * Description:
+ * This function clears the FIQ disable bit in the status register
+ *
+ * Calling Sequence:
+ * void
+ *
+ * Returns:
+ * previous value of CPSR
+ *
+ *****************************************************************************/
+unsigned enableFIQ(void);
+
+/******************************************************************************
+ *
+ * Function Name: restoreIRQ()
+ *
+ * Description:
+ * This function restores the FIQ disable bit in the status register
+ * to the value contained within passed oldCPSR
+ *
+ * Calling Sequence:
+ * void
+ *
+ * Returns:
+ * previous value of CPSR
+ *
+ *****************************************************************************/
+unsigned restoreFIQ(unsigned oldCPSR);
+
+#endif
@@ -0,0 +1,10 @@
+#include "type.h"
+
+
+int BlockDevInit(void);
+
+int BlockDevWrite(U32 dwAddress, U8* pbBuf);
+int BlockDevRead(U32 dwAddress, U8* pbBuf);
+
+int BlockDevGetSize(U32 *pdwDriveSize);
+int BlockDevGetStatus(void);
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