{"payload":{"header_redesign_enabled":false,"results":[{"id":"414366201","archived":false,"color":"#b2b7f8","followers":1,"has_funding_file":false,"hl_name":"SM2A/Digital_Logic_Design_Lab_Course_Projects","hl_trunc_description":"🎓💻University of Tehran Digital Logic Design Lab Course Projects - Spring 2021","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":414366201,"name":"Digital_Logic_Design_Lab_Course_Projects","owner_id":35252268,"owner_login":"SM2A","updated_at":"2021-11-20T08:40:41.153Z","has_issues":true}},"sponsorable":false,"topics":["verilog","synthesis","dld","digital-logic-design"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":68,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ASM2A%252FDigital_Logic_Design_Lab_Course_Projects%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/SM2A/Digital_Logic_Design_Lab_Course_Projects/star":{"post":"ljQFFaxy0ChlnjgF3kcf_GOSwpyNbLcC0pQTx0NTJohkAbi6K6tmhjQijsaM8eBNWoQ_TxVedXT8suSbvHGA2w"},"/SM2A/Digital_Logic_Design_Lab_Course_Projects/unstar":{"post":"O33J9IfgGAiRDyoLrUdfqXvFxje7DhAVIG5Aqw16BzvNHBDI3iQut0ajNBobBYsFrlCxiG3keZ1xYBRPc6JEpw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"aQRqhP7PgqXvlDI5uE1iHeik6Q_Knalu0PaQxI6Gya7CryJs-RdsX1agzJNeiJrqHThKyEpPN8vlShcCxbXhEg"}}},"title":"Repository search results"}