From 52757b5e33259a088509a777a9e3a5b971194c7d Mon Sep 17 00:00:00 2001 From: Eya Date: Tue, 5 Jul 2022 11:07:36 +0100 Subject: [PATCH] Release v1.27.1 --- Drivers/CMSIS/Device/ST/STM32F4xx/README.md | 11 +- .../Inc/Legacy/stm32_hal_legacy.h | 76 +++-- .../Inc/stm32f4xx_hal_conf_template.h | 4 +- .../Inc/stm32f4xx_hal_eth.h | 283 +++++++++--------- Drivers/STM32F4xx_HAL_Driver/README.md | 16 +- .../STM32F4xx_HAL_Driver/Release_Notes.html | 86 ++++-- .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 4 +- .../Src/stm32f4xx_hal_eth.c | 198 +++++++++--- Release_Notes.html | 240 ++++++++------- _htmresc/ReleaseNotes.html | 5 +- _htmresc/ReleaseNotes_Patch.html | 34 +-- _htmresc/STM32Cube.bmp | Bin 2246766 -> 1802394 bytes package.xml | 4 +- 13 files changed, 553 insertions(+), 408 deletions(-) diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/README.md b/Drivers/CMSIS/Device/ST/STM32F4xx/README.md index 9270214c4..1c317afb3 100644 --- a/Drivers/CMSIS/Device/ST/STM32F4xx/README.md +++ b/Drivers/CMSIS/Device/ST/STM32F4xx/README.md @@ -27,16 +27,7 @@ Details about the content of this release are available in the release note [her ## Compatibility information -In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: - -CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package ---------------- | ---------- | ------------------------------------- -Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 -Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 -Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 -Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 -Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 -Tag v2.6.8 | Tag v5.4.0_cm4 | Tag v1.27.0 +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeF4/blob/master/Release_Notes.html) release note. The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 1cfd19b94..934f1f971 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,14 +37,16 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF #endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ /** * @} */ @@ -110,6 +112,7 @@ extern "C" { #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ + /** * @} */ @@ -231,8 +234,11 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ +#if defined(STM32C0) +#else #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif /** * @} */ @@ -499,7 +505,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -568,7 +574,6 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ - /** * @} */ @@ -668,6 +673,10 @@ extern "C" { #if defined(STM32U5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ #endif /* STM32U5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ /** * @} */ @@ -1080,8 +1089,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1092,15 +1101,22 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ /** * @} @@ -3407,7 +3423,7 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3520,8 +3536,8 @@ extern "C" { #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE @@ -3537,15 +3553,20 @@ extern "C" { #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE -#endif +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ /** * @} @@ -3563,7 +3584,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3616,7 +3639,6 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - /** * @} */ @@ -3628,7 +3650,7 @@ extern "C" { #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE @@ -3965,6 +3987,16 @@ extern "C" { * @} */ +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h index d32595ffd..c0c448417 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h @@ -209,8 +209,8 @@ #define MAC_ADDR5 0U /* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RX_BUF_SIZE 1528U /* ETH Max buffer size for receive */ +#define ETH_TX_BUF_SIZE 1528U /* ETH Max buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h index af84bcb42..ba5a09bbc 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h @@ -276,9 +276,6 @@ typedef struct PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). This parameter can be a value of @ref ETH_Preamble_Length */ - FunctionalState - UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */ - FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ @@ -404,7 +401,7 @@ typedef struct typedef enum { HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ - HAL_ETH_RMII_MODE = ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) /*!< Reduced Media Independent Interface */ + HAL_ETH_RMII_MODE = SYSCFG_PMC_MII_RMII_SEL /*!< Reduced Media Independent Interface */ } ETH_MediaInterfaceTypeDef; /** * @@ -694,51 +691,51 @@ typedef struct /** * @brief Bit definition of TDES0 register: DMA Tx descriptor status register */ -#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */ -#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */ -#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */ -#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */ -#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */ +#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ +#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ +#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ +#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ +#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ +#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ +#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ /** * @brief Bit definition of TDES1 register */ -#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */ +#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ /** * @brief Bit definition of TDES2 register */ -#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ +#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ /** * @brief Bit definition of TDES3 register */ -#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ +#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ /*--------------------------------------------------------------------------------------------- TDES6 | Transmit Time Stamp Low [31:0] | @@ -747,10 +744,10 @@ TDES7 | Transmit Time Stamp High [31:0] ----------------------------------------------------------------------------------------------*/ /* Bit definition of TDES6 register */ -#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ +#define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ /* Bit definition of TDES7 register */ -#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ +#define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ /** * @} @@ -777,44 +774,44 @@ TDES7 | Transmit Time Stamp High [31:0] /** * @brief Bit definition of RDES0 register: DMA Rx descriptor status register */ -#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ +#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ /** * @brief Bit definition of RDES1 register */ -#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */ +#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ /** * @brief Bit definition of RDES2 register */ -#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ +#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ /** * @brief Bit definition of RDES3 register */ -#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ +#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ /*--------------------------------------------------------------------------------------------------------------------- RDES4 | Reserved[31:15] | Extended Status [14:0] | @@ -827,47 +824,47 @@ TDES7 | Transmit Time Stamp High [31:0] --------------------------------------------------------------------------------------------------------------------*/ /* Bit definition of RDES4 register */ -#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ -#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ -#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ -#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message - (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message - (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message - (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message - (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message - (peer-to-peer transparent clock) - or Announce message (Ordinary - or Boundary clock) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message - (peer-to-peer transparent clock) - or Management message (Ordinary - or Boundary clock) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message - (peer-to-peer transparent clock) - or Signaling message (Ordinary - or Boundary clock) */ -#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ -#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ -#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ -#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ -#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ -#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ -#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in - the IP datagram */ -#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in - the IP datagram */ -#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in +#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ +#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message + (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message + (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message + (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message + (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message + (peer-to-peer transparent clock) + or Announce message (Ordinary + or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message + (peer-to-peer transparent clock) + or Management message (Ordinary + or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message + (peer-to-peer transparent clock) + or Signaling message (Ordinary + or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ +#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in + the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in + the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ /* Bit definition of RDES6 register */ -#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ +#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ /* Bit definition of RDES7 register */ -#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ +#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ /** * @} @@ -876,13 +873,13 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_Frame_settings ETH frame settings * @{ */ -#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ -#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ +#define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ /** * @} */ @@ -890,14 +887,14 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_Error_Code ETH Error Code * @{ */ -#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */ -#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */ -#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ -#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ -#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */ +#define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */ +#define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */ +#define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ +#define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */ +#define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ /** * @} @@ -906,12 +903,12 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes * @{ */ -#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U) -#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U) -#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U) -#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U) -#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U) -#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U) +#define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U +#define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U +#define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U +#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U +#define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U +#define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U /** * @} */ @@ -930,7 +927,7 @@ TDES7 | Transmit Time Stamp High [31:0] * @{ */ #define ETH_CRC_PAD_DISABLE (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC) -#define ETH_CRC_PAD_INSERT ((uint32_t)0x00000000U) +#define ETH_CRC_PAD_INSERT 0x00000000U #define ETH_CRC_INSERT ETH_DMATXDESC_DP /** * @} @@ -997,7 +994,7 @@ TDES7 | Transmit Time Stamp High [31:0] * @{ */ #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA -#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U) +#define ETH_DMAARBITRATION_RX1_TX1 0x00000000U #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 @@ -1006,7 +1003,7 @@ TDES7 | Transmit Time Stamp High [31:0] #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) -#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U) +#define ETH_DMAARBITRATION_TX1_RX1 0x00000000U #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) @@ -1023,7 +1020,7 @@ TDES7 | Transmit Time Stamp High [31:0] */ #define ETH_BURSTLENGTH_FIXED ETH_DMABMR_FB #define ETH_BURSTLENGTH_MIXED ETH_DMABMR_MB -#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U) +#define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U /** * @} */ @@ -1089,12 +1086,12 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags * @{ */ -#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U) +#define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0) #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1) #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0) #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 -#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U) +#define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0) #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1) #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0) @@ -1191,7 +1188,7 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_Speed ETH Speed * @{ */ -#define ETH_SPEED_10M ((uint32_t)0x00000000U) +#define ETH_SPEED_10M 0x00000000U #define ETH_SPEED_100M 0x00004000U /** * @} @@ -1201,7 +1198,7 @@ TDES7 | Transmit Time Stamp High [31:0] * @{ */ #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM -#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U) +#define ETH_HALFDUPLEX_MODE 0x00000000U /** * @} */ @@ -1230,7 +1227,7 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control * @{ */ -#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U) +#define ETH_SOURCEADDRESS_DISABLE 0x00000000U #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 @@ -1262,10 +1259,10 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_MAC_addresses ETH MAC addresses * @{ */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) +#define ETH_MAC_ADDRESS0 0x00000000U +#define ETH_MAC_ADDRESS1 0x00000008U +#define ETH_MAC_ADDRESS2 0x00000010U +#define ETH_MAC_ADDRESS3 0x00000018U /** * @} */ @@ -1304,11 +1301,11 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup HAL_ETH_StateTypeDef ETH States * @{ */ -#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */ -#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */ -#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */ -#define HAL_ETH_STATE_STARTED ((uint32_t)0x00000023U) /*!< an internal process is started */ -#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */ +#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ +#define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */ +#define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */ +#define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */ +#define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */ /** * @} */ @@ -1344,7 +1341,7 @@ TDES7 | Transmit Time Stamp High [31:0] * @{ */ #define ETH_MEDIA_INTERFACE_MII 0x00000000U -#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) +#define ETH_MEDIA_INTERFACE_RMII (SYSCFG_PMC_MII_RMII_SEL) /** * @} */ @@ -1805,8 +1802,8 @@ TDES7 | Transmit Time Stamp High [31:0] /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status * @{ */ -#define HAL_ETH_PTP_NOT_CONFIGURATED ((uint32_t)0x00000000U) /*!< ETH PTP Configuration not done */ -#define HAL_ETH_PTP_CONFIGURATED ((uint32_t)0x00000001U) /*!< ETH PTP Configuration done */ +#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */ +#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */ /** * @} */ @@ -1928,7 +1925,7 @@ TDES7 | Transmit Time Stamp High [31:0] ( __INTERRUPT__)) == ( __INTERRUPT__)) /*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ -#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00080000U) +#define ETH_WAKEUP_EXTI_LINE 0x00080000U /** * @brief Enable the ETH WAKEUP Exti Line. diff --git a/Drivers/STM32F4xx_HAL_Driver/README.md b/Drivers/STM32F4xx_HAL_Driver/README.md index c345d9be8..5900a11b7 100644 --- a/Drivers/STM32F4xx_HAL_Driver/README.md +++ b/Drivers/STM32F4xx_HAL_Driver/README.md @@ -27,21 +27,7 @@ Details about the content of this release are available in the release note [her ## Compatibility information -In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package: - -It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table. - -HAL Driver F4 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package -------------- | --------------- | ---------- | ------------------------------------- -Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till HAL tag) -Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till HAL tag) -Tag v1.7.8 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 (and following, if any, till HAL tag) -Tag v1.7.9 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 (and following, if any, till HAL tag) -Tag v1.7.10| Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 (and following, if any, till HAL tag) -Tag v1.7.11| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 (and following, if any, till HAL tag) -Tag v1.7.12| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.1 (and following, if any, till HAL tag) -Tag v1.7.13| Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 (and following, if any, till HAL tag) -Tag v1.8.0 | Tag v2.6.8 | Tag v5.4.0_cm4 | Tag v1.27.0 (and following, if any, till HAL tag) +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeF4/blob/master/Release_Notes.html) release note. The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). diff --git a/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 08f03c75c..215114fdb 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -6,7 +6,8 @@ Release Notes for STM32F4xx HAL Drivers + charset=windows-1252">Release Notes for STM32F4xx HAL Drivers +

 

@@ -46,11 +47,30 @@

-

Update +

Update - History

V1.8.0 + History

V1.8.1 + / 24-June-2022

+
+

Main + + + + + Changes
+

+
+
  • General updates to fix HAL ETH defects and implementation enhancements.

  • HAL + updates

    + + +
      +
    • HAL ETH update
      • Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().
      • Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.
      • Correct +bit positions when getting MAC and DMA configurations and replace +‘UnicastSlowProtocolPacketDetect’ by ‘UnicastPausePacketDetect’ in the +MAC default configuration structure.
      • Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.
      • Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.

V1.8.0 / 11-February-2022

Main @@ -260,7 +280,7 @@

V1.7.13 +

V1.7.13 / 16-July-2021

Main @@ -467,7 +487,7 @@

-

V1.7.12 +

V1.7.12 / 26-March-2021

Main @@ -491,7 +511,7 @@

V1.7.11 +

V1.7.11 / 12-February-2021

Main @@ -1016,7 +1036,7 @@

V1.7.10 +

V1.7.10 @@ -1050,7 +1070,7 @@

V1.7.9 +

V1.7.9 @@ -1172,7 +1192,7 @@

V1.7.8 +

V1.7.8 @@ -1280,7 +1300,7 @@

V1.7.7 +

V1.7.7 @@ -2435,7 +2455,7 @@

-

V1.7.6 +

V1.7.6 @@ -2563,7 +2583,7 @@

V1.7.5 +

V1.7.5 @@ -3277,7 +3297,7 @@

device -

V1.7.4 +

V1.7.4 @@ -3339,7 +3359,7 @@

-

V1.7.3 +

V1.7.3 @@ -3610,7 +3630,7 @@

FSMC_PCCARD_Init() -

V1.7.2 +

V1.7.2 @@ -3995,7 +4015,7 @@

used -

V1.7.1 +

V1.7.1 @@ -4079,7 +4099,7 @@

V1.7.0 +

V1.7.0 @@ -4578,7 +4598,7 @@

-

V1.6.0 +

V1.6.0 @@ -4814,7 +4834,7 @@

callbacks -

V1.5.2 +

V1.5.2 @@ -4913,7 +4933,7 @@

V1.5.1 +

V1.5.1 @@ -5005,7 +5025,7 @@

way -

V1.5.0 +

V1.5.0 @@ -6211,7 +6231,7 @@

WWDG_Example -

V1.4.4 +

V1.4.4 @@ -6957,7 +6977,7 @@



-

V1.4.4 +

V1.4.4 / 11-December-2015

Main Changes

    @@ -6995,7 +7015,7 @@

-

V1.4.2 +

V1.4.2 @@ -7227,7 +7247,7 @@

-

V1.4.1 +

V1.4.1 @@ -7317,7 +7337,7 @@

correctly” -

V1.4.0 +

V1.4.0 @@ -7547,7 +7567,7 @@

-

V1.3.2 +

V1.3.2 @@ -7875,7 +7895,7 @@

activation -

V1.3.1 +

V1.3.1 @@ -7945,7 +7965,7 @@

configuration -

V1.3.0 +

V1.3.0 @@ -8846,7 +8866,7 @@

-

V1.2.0 +

V1.2.0 @@ -10476,7 +10496,7 @@

V1.1.0 +

V1.1.0 @@ -11393,7 +11413,7 @@

-

V1.0.0 +

V1.0.0 @@ -11418,7 +11438,7 @@

-

 

+

 

diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index cb652b8e2..9ba2ba7d8 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.8.0 + * @brief STM32F4xx HAL Driver version number V1.8.1 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c index 9cf3e6c2f..50d95b882 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c @@ -194,44 +194,44 @@ /** @addtogroup ETH_Private_Constants ETH Private Constants * @{ */ -#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU) -#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU) -#define ETH_MACFFR_MASK ((uint32_t)0x800007FFU) -#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU) -#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U) -#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U) -#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U) -#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU) - -#define ETH_DMAMR_MASK ((uint32_t)0x00007802U) -#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U) -#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU) -#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U) -#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U) -#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \ - ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU) +#define ETH_MACCR_MASK 0xFFFB7F7CU +#define ETH_MACECR_MASK 0x3F077FFFU +#define ETH_MACFFR_MASK 0x800007FFU +#define ETH_MACWTR_MASK 0x0000010FU +#define ETH_MACTFCR_MASK 0xFFFF00F2U +#define ETH_MACRFCR_MASK 0x00000003U +#define ETH_MTLTQOMR_MASK 0x00000072U +#define ETH_MTLRQOMR_MASK 0x0000007BU + +#define ETH_DMAMR_MASK 0x00007802U +#define ETH_DMASBMR_MASK 0x0000D001U +#define ETH_DMACCR_MASK 0x00013FFFU +#define ETH_DMACTCR_MASK 0x003F1010U +#define ETH_DMACRCR_MASK 0x803F0000U +#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \ + ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU) /* Timeout values */ -#define ETH_SWRESET_TIMEOUT ((uint32_t)500U) -#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U) +#define ETH_SWRESET_TIMEOUT 500U +#define ETH_MDIO_BUS_TIMEOUT 1000U #define ETH_DMARXDESC_ERRORS_MASK ((uint32_t)(ETH_DMARXDESC_DBE | ETH_DMARXDESC_RE | \ ETH_DMARXDESC_OE | ETH_DMARXDESC_RWT |\ ETH_DMARXDESC_LC | ETH_DMARXDESC_CE |\ ETH_DMARXDESC_DE | ETH_DMARXDESC_IPV4HCE)) -#define ETH_MAC_US_TICK ((uint32_t)1000000U) +#define ETH_MAC_US_TICK 1000000U -#define ETH_MACTSCR_MASK ((uint32_t)0x0087FF2FU) +#define ETH_MACTSCR_MASK 0x0087FF2FU -#define ETH_PTPTSHR_VALUE ((uint32_t)0xFFFFFFFFU) -#define ETH_PTPTSLR_VALUE ((uint32_t)0xBB9ACA00U) +#define ETH_PTPTSHR_VALUE 0xFFFFFFFFU +#define ETH_PTPTSLR_VALUE 0xBB9ACA00U /* Ethernet MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U /* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) +#define ETH_REG_WRITE_DELAY 0x00000001U /* ETHERNET MACCR register Mask */ #define ETH_MACCR_CLEAR_MASK 0xFF20810FU @@ -243,8 +243,8 @@ #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U /* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ /* ETHERNET DMA Rx descriptors Frame length Shift */ #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U @@ -696,6 +696,8 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca */ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { + uint32_t tmpreg1; + if (heth->gState == HAL_ETH_STATE_READY) { heth->gState = HAL_ETH_STATE_BUSY; @@ -709,9 +711,21 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) /* Enable the MAC transmission */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Enable the MAC reception */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); @@ -739,6 +753,8 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) { + uint32_t tmpreg1; + if (heth->gState == HAL_ETH_STATE_READY) { heth->gState = HAL_ETH_STATE_BUSY; @@ -765,9 +781,21 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) /* Enable the MAC transmission */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Enable the MAC reception */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); @@ -802,12 +830,14 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) { + uint32_t tmpreg1; + if (heth->gState == HAL_ETH_STATE_STARTED) { /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; /* Disable the DMA transmission */ - CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); /* Disable the DMA reception */ CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); @@ -815,12 +845,24 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) /* Disable the MAC reception */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); /* Disable the MAC transmission */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + heth->gState = HAL_ETH_STATE_READY; /* Return function status */ @@ -842,6 +884,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) { ETH_DMADescTypeDef *dmarxdesc; uint32_t descindex; + uint32_t tmpreg1; if (heth->gState == HAL_ETH_STATE_STARTED) { @@ -852,19 +895,32 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); /* Disable the DMA transmission */ - CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); /* Disable the DMA reception */ CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); /* Disable the MAC reception */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); /* Disable the MAC transmission */ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + /* Clear IOC bit to all Rx descriptors */ for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) { @@ -1173,20 +1229,23 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (allocStatus != 0U) { - /* Ensure rest of descriptor is written to RAM before the OWN bit */ - __DMB(); - - WRITE_REG(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); - if (heth->RxDescList.ItMode == 0U) { - WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | 1000U | ETH_DMARXDESC_RCH); + WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); } else { - WRITE_REG(dmarxdesc->DESC1, 1000U | ETH_DMARXDESC_RCH); + WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); } + /* Before transferring the ownership to DMA, make sure that the RX descriptors bits writing + is fully performed. + The __DMB() instruction is added to avoid any potential compiler optimization that + may lead to abnormal behavior. */ + __DMB(); + + SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); + /* Increment current rx descriptor index */ INCR_RX_DESC_INDEX(descidx, 1U); /* Get current descriptor address */ @@ -2146,15 +2205,15 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 23) == 0U) ? ENABLE : DISABLE; macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE; macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG); - macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 27) > 0U) ? ENABLE : DISABLE; + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 10U) > 0U) ? ENABLE : DISABLE; macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE; macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE; macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PLT); macconf->PauseTime = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PT) >> 16); - macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) > 0U) ? ENABLE : DISABLE; - macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 1) > 0U) + macconf->ReceiveFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) >> 2U) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 3U) > 0U) ? ENABLE : DISABLE; return HAL_OK; @@ -2175,8 +2234,9 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp return HAL_ERROR; } - dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_DSL) >> 2; - dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR, + (ETH_DMAARBITRATION_RXPRIORTX | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1)); + dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 25U) > 0U) ? ENABLE : DISABLE; dmaconf->BurstMode = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_FB | ETH_DMABMR_MB); dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_RDP); dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_PBL); @@ -2312,6 +2372,7 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) { uint32_t filterconfig; + uint32_t tmpreg1; if (pFilterConfig == NULL) { @@ -2332,6 +2393,12 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil MODIFY_REG(heth->Instance->MACFFR, ETH_MACFFR_MASK, filterconfig); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFFR = tmpreg1; + return HAL_OK; } @@ -2417,14 +2484,28 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_ */ HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) { + uint32_t tmpreg1; if (pHashTable == NULL) { return HAL_ERROR; } heth->Instance->MACHTHR = pHashTable[0]; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACHTHR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACHTHR = tmpreg1; + heth->Instance->MACHTLR = pHashTable[1]; + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACHTLR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACHTLR = tmpreg1; + return HAL_OK; } @@ -2439,6 +2520,7 @@ HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashT */ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) { + uint32_t tmpreg1; MODIFY_REG(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTI, VLANIdentifier); if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) { @@ -2448,6 +2530,12 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit { SET_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); } + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACVLANTR = tmpreg1; } /** @@ -2478,13 +2566,27 @@ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigType */ void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) { + uint32_t tmpreg1; + /* clear wake up sources */ CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFE | ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU); + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACPMTCSR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACPMTCSR = tmpreg1; + if (READ_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD) != 0U) { /* Exit power down mode */ CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACPMTCSR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACPMTCSR = tmpreg1; } /* Disable PMT interrupt */ @@ -2670,11 +2772,11 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac tmpreg1 &= ETH_MACFCR_CLEAR_MASK; tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | - (uint32_t)macconf->ZeroQuantaPause | + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | macconf->PauseLowThreshold | - (uint32_t)macconf->UnicastSlowProtocolPacketDetect | - (uint32_t)macconf->ReceiveFlowControl | - (uint32_t)macconf->TransmitFlowControl); + ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | + ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) | + ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U)); /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; @@ -2764,7 +2866,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) macDefaultConf.TransmitFlowControl = DISABLE; macDefaultConf.Speed = ETH_SPEED_100M; macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; - macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; + macDefaultConf.UnicastPausePacketDetect = DISABLE; /* MAC default configuration */ ETH_SetMACConfig(heth, &macDefaultConf); @@ -3091,6 +3193,12 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */ +#ifdef HAL_ETH_USE_PTP + heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */ +#endif /* HAL_ETH_USE_PTP */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */ } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ diff --git a/Release_Notes.html b/Release_Notes.html index 73c479bad..b11e845b5 100644 --- a/Release_Notes.html +++ b/Release_Notes.html @@ -11,7 +11,7 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} - + @@ -60,11 +60,49 @@

Purpose

Update History

- +

Maintenance release

Main Changes

    +

  • Patch release of STM32CubeF4 Firmware Package.

    • +
  • HAL +
      +
    • ETH_HAL +
        +
      • Remove useless assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)) from static function ETH_MACAddressConfig().
        • +
      • Replace hard coded Rx buffer size (1000U) by macro ETH_RX_BUF_SIZE.
        • +
      • Correct bit positions when getting MAC and DMA configurations and replace ‘UnicastSlowProtocolPacketDetect’ by ‘UnicastPausePacketDetect’ in the MAC default configuration structure.
        • +
      • Ensure a delay of 4 TX_CLK/RX_CLK cycles between two successive write operations to the same register.
        • +
      • Disable DMA transmission in both HAL_ETH_Stop_IT() and HAL_ETH_Stop() APIs.
        • +
      • +
    • +
+

Contents

+ + + + + + + + + + + + + + + +
NameVersionRelease note
STM32F4xx HALV1.8.1release notes
+
+
+
+ +
+

Maintenance release

+

Main Changes

+
  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
  • The following changes done on the HAL drivers require an update of the application code based on older HAL versions @@ -267,7 +305,7 @@

    Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    @@ -677,8 +715,8 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • General updates to fix known defects and enhancements implementation.

    • CMSIS updates @@ -787,7 +825,7 @@

      Main Changes

    -

    Contents

    +

    Contents

    Drivers
    @@ -814,8 +852,8 @@

    Contents

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • Patch release to mainly fix a wrong system clock configuration in some STM32F411/412/413 projects.

    • HAL @@ -834,7 +872,7 @@

      Main Changes

    -

    Contents

    +

    Contents

    @@ -856,8 +894,8 @@

    Contents

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • Add new HAL FMPSMBUS extended driver to support FMPSMBUS fast Mode Plus.
      • @@ -1145,7 +1183,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component
    • -

    Contents

    +

    Contents

    @@ -1540,8 +1578,8 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • Patch release of STM32CubeF4 Firmware Package.

    • HAL

      @@ -1555,7 +1593,7 @@

      Main Changes

    -

    Contents

    +

    Contents

    Drivers
    @@ -1577,8 +1615,8 @@

    Contents

    -

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    -

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    +

    Maintenance release

    +

    Main Changes

    • Patch release to fix known defects and enhancements implementation.

    • HAL

      @@ -1609,7 +1647,7 @@

      Main Changes

    -

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    +

    Contents

    @@ -1631,8 +1669,8 @@

    Contents

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Add new HAL FMPSMBUS and LL FMPI2C drivers
    • General updates to fix known defects and enhancements implementation
      • @@ -1733,7 +1771,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    @@ -2112,8 +2150,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Patch release to fix known defects and enhancements implementation

    • HAL @@ -2134,7 +2172,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    Drivers
    @@ -2162,8 +2200,8 @@

    Contents

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Patch release to fix mainly the I2C send break issue with IT processes API’s
    • HAL I2C update @@ -2195,7 +2233,7 @@

      Main Changes

    • Software Quality improvement with a fix ofCodeSonar warning on PCD_Port_IRQHandler() and HCD_Port_IRQHandler()interrupt handlers
    -

    Contents

    +

    Contents

    Drivers
    @@ -2218,8 +2256,8 @@

    Contents

    -

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    -

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    +

    Maintenance release

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    Main Changes

    • HAL
        @@ -2302,7 +2340,7 @@

        Main Changes

    • For the complete list of changes, please refer to the release notes of each firmware component
    -

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    +

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    Drivers
    @@ -2676,8 +2714,8 @@

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    -

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    -

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    +

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    • Maintenance release:
        @@ -2689,8 +2727,8 @@

        Main Changes

        -

        Maintenance release

        -

        Main Changes

        +

        Maintenance release

        +

        Main Changes

        • Thanks to the acquisition of Draupner Graphics A/S, ST is extending the STM32 ecosystem with advanced and easy to use graphic software solution enabling stunning GUI additions to embedded devices. TouchGFX solution is now fully part of STM32CubeF4.

        • TouchGFX examples and demonstrations can be accessed directly through the TouchGFX Designer tool. Here you simply create a new project, select the appropriate ST board in the Application Template section and select whatever demonstration or example you want in the UI Template selector. After this you will have a TouchGFX application ready to compile and flash to the selected ST board. More information are available here

          • @@ -2717,7 +2755,7 @@

          Main Changes

      • For the complete list of changes, please refer to the release notes of each firmware component

      -

      Contents

      +

      Contents

    Drivers
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    -

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    -

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    +

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    +

    Main Changes

    • General updates to fix known defects and enhancements implementation

    • HAL @@ -3126,7 +3164,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    Drivers
    @@ -3496,12 +3534,12 @@

    Dependencies

    -

    Maintenance release

    -

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    Main Changes

    • Package Clean-up: remove unwanted project folders
    -

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    Drivers
    @@ -3871,8 +3909,8 @@

    Dependencies

    -

    Maintenance release

    -

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    Maintenance release

    +

    Main Changes

    • General updates to be compliant with Linux platforms
    • General update to fix known defects and several implementations enhancement
      • @@ -3931,7 +3969,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component
    • -

    Contents

    +

    Contents

    Drivers
    @@ -4301,8 +4339,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • General update to fix known defects and several implementations enhancement

    • HAL @@ -4335,7 +4373,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    Drivers
    @@ -4696,8 +4734,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Add the support of the STM32F413H-Discovery board
        @@ -4772,7 +4810,7 @@

        Main Changes

    • For the complete list of changes, please refer to the release notes of each firmware component

    -

    Contents

    +

    Contents

    Drivers
    @@ -5133,8 +5171,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Official release to add the support of STM32F413xx and STM32F423xx devices

    • Fix known defects and several implementation enhancement

      • @@ -5184,7 +5222,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    Drivers
    @@ -5545,12 +5583,12 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Patch release to fix issues in I2C/FMPI2C HAL drivers
    -

    Contents

    +

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    Drivers
    @@ -5572,8 +5610,8 @@

    Contents

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Fix known defects and enhancements implementation
    • HAL @@ -5620,7 +5658,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component
    • -

    Contents

    +

    Contents

    @@ -5979,8 +6017,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Official release to add the support of STM32F412cx, STM32F412rx, STM32F412vx and STM32F412zx devices

    • Fix known defects and several implementation enhancement

      • @@ -6021,7 +6059,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    Drivers
    @@ -6379,8 +6417,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Fix known defects and enhancements implementation
    • HAL @@ -6417,7 +6455,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component
    • -

    Contents

    +

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    Drivers
    @@ -6774,12 +6812,12 @@

    Dependencies

    -

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    -

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    • For the complete list of changes, please refer to the release notes of each firmware component
    -

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    +

    Contents

    Drivers
    @@ -6801,8 +6839,8 @@

    Contents

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Support new boards: STM32F411E-Discovery, STM32F446ZE NUCLEO144 and STM32F429ZI NUCLEO144

    • Fix known defects and enhancements implementation

      • @@ -6838,7 +6876,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component

    • -

    Contents

    +

    Contents

    @@ -7185,8 +7223,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Maintenance release to fix known defects and enhancements implementation
    • HAL @@ -7228,7 +7266,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware component
    • -

    Contents

    +

    Contents

    Drivers
    @@ -7567,8 +7605,8 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • Official release to support STM32F469xx, STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx devices

    • Fix known defects and several enhancements implementation

      • @@ -7607,7 +7645,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware components

    • -

    Contents

    +

    Contents

    Drivers
    @@ -7949,8 +7987,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Official release to support STM32446E-Nucleo board

    • Maintenance release to fix known defects

      • @@ -7987,7 +8025,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware components

    • -

    Contents

    +

    Contents

    Drivers
    @@ -8351,8 +8389,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Add support of System Workbench for STM32 (SW4STM32) toolchain

    • Maintenance release to fix known defects

      • @@ -8392,7 +8430,7 @@

      Main Changes

  • Fix compile issue in some projects (9 in total), mainly due to bad project settings

    • -

    Contents

    +

    Contents

    Drivers
    @@ -8749,8 +8787,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Official release to support STM32F446xx devices

    • Fix known defects and several enhancements implementation

      • @@ -8788,7 +8826,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware components

    • -

    Contents

    +

    Contents

    Drivers
    @@ -9144,8 +9182,8 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • Maintenance release to fix known defects and several enhancements implementation
    • HAL @@ -9194,7 +9232,7 @@

      Main Changes

  • For the complete list of changes, please refer to the release notes of each firmware components

    • -

    Contents

    +

    Contents

    Drivers
    @@ -9541,8 +9579,8 @@

    Dependencies

    -

    Maintenance release

    -

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    +

    Maintenance release

    +

    Main Changes

    • Full features release, containing all projects sources for the supported boards

    • Projects @@ -9562,7 +9600,7 @@

      Main Changes

  • Use STM32CubeUpdater.exe utility V4.2.0

    • -

    Contents

    +

    Contents

    Drivers
    @@ -9898,8 +9936,8 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • Patch release for STM32CubeF4, adding support of STM32F411xE devices with several enhancements and bugs fix
        @@ -9921,7 +9959,7 @@

        Main Changes

    • Note: for the complete list of changes, please refer to the release notes of each Firmware component
    -

    Contents

    +

    Contents

    Drivers
    @@ -10236,8 +10274,8 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • Add sources of STM324x9I-EVAL (both references MB1046 and MB1063), STM324xG-EVAL and STM32F429I-Discovery Demonstration (only for EWARM and MDK-ARM)
        @@ -10247,7 +10285,7 @@

        Main Changes

      • Miscellaneous update on Examples, Applications, Demonstrations and Templates projects for some boards; for more details refer to the associated release notes
      • Minor update in STM324x9I-EVAL, STM324xG-EVAL and STM32F429I-Discovery uSD and EEPROM BSP drivers
      -

      Contents

      +

      Contents

    Drivers
    @@ -10549,12 +10587,12 @@

    Dependencies

    -

    Maintenance release

    -

    Main Changes

    +

    Maintenance release

    +

    Main Changes

    • First official release of STM32CubeF4 (STM32Cube for STM32F4 Series)
    -

    Contents

    +

    Contents

    Drivers
    diff --git a/_htmresc/ReleaseNotes.html b/_htmresc/ReleaseNotes.html index 3bbbcc98b..0abd0eaa2 100644 --- a/_htmresc/ReleaseNotes.html +++ b/_htmresc/ReleaseNotes.html @@ -1,4 +1,3 @@ - -STM32CubeF4 Firmware Package V1.26.0 / 12-February-2021
    +STM32CubeF4 Firmware Package V1.27.0 / 11-February-2022

    -Main Changes

    • General updates to fix known defects and enhancements implementation
    • Added new HAL FMPSMBUS extended driver to support FMPSMBUS fast Mode Plus.
    • Upgraded FreeRTOS to use V10.3.1 ST modified 20200831.
    • Upgraded USB Device Lib to use V2.7.1.
    • Upgraded MbedTLS to use V2.16.2
    • Upgraded PDM Lib to use V3.3.0
    • Removed register keyword to be compliant with new C++ rules:
      • The register storage class specifier was deprecated in C++11 and removed in C++17.
    • Support onew component LSM303AGR accelerometer.
    • Support new component I34250D gyroscope.
    • Support new LCD controller component NT35510.
    \ No newline at end of file +Main Changes

    • Maintenance release
    • General updates to fix known defects and enhancements implementation
    • Rework Ethernet driver to resolve problems and improve performance.
    • Upgraded USB Device Lib to use V2.10.0.
    • Upgraded USB Host Lib to use V3.4.0.
    \ No newline at end of file diff --git a/_htmresc/ReleaseNotes_Patch.html b/_htmresc/ReleaseNotes_Patch.html index 72cdf5d96..e3e366ed3 100644 --- a/_htmresc/ReleaseNotes_Patch.html +++ b/_htmresc/ReleaseNotes_Patch.html @@ -1,30 +1,4 @@ - - - - - - - - STM32CubeF4 Firmware Package V1.26.2 / - 16-July-2021
    -
    - Main Changes
    -
      -
    • -

      Patch release to fix - known defects and enhancements implementation.

      -
      • -
    - - +STM32CubeF4 Firmware Package V1.27.1 /22-June-2022
    +
    +Main Changes
    • Patch release of STM32CubeF4 Firmware package.
    • Update HAL ETH driver.
      +
    \ No newline at end of file diff --git a/_htmresc/STM32Cube.bmp b/_htmresc/STM32Cube.bmp index 3f4eb3d9beab87c0f85fa2841c325de07f98898c..44657b635421249532114efc6bdf1a2d3f8734f8 100644 GIT binary patch literal 1802394 zcmeFa*>fC8mhP95{)U;krm@k3%w#qXx_Tk0kyVd$%|RaX^30tENHxL_j)fLKWo#7clW0VFc9Z~+$}7XVza5F|1|7HjS9>JEL82XHzg z5+D*8k(tQ&(!5v^9`46Iety#Za}UqJKmCW&g1_~dpZ^j6{XPEs<-hXz{=9~XsQm7*AS@4*__tBB0X;h?MsH!9~e)Q21DOW#65whZ~=aN#)%Al?veI{7!k$M(; zRfWt)0GL=#2VGS|T*3q@al1=J969ot1@%g->;o%2MvPbHb(XXnz!@VH8+_lIsp{HlWG3EtFx-gM>H@!+~P3{6|Ek^8# zKX|jE)*w=0a~0s&>ZNL>*V$g8epQZ@2G;HC$M)t+idtZm^%qiniqW=Ju1W14cNPq;gNC3mSeY?Is)=S+WTE$uubu|S_7!_o#0O=tvaH)gF45RYBa>!PCE@_02n+aKpM4~ye|F@E z$ZS}{GQKX|l|n`?y)4}tj#Y^&UQdi;A@ISQRViUdCAOQ=XCkU-J(;S8x~eLv-;qkD z8dqX;Q%O;)j32D9N@=f&IZa)DKBY=g>2aXfO0SYC)NWI)^Q%kh00z~uZcQ&y3KeHi z@$eR<(v=0ds!l(GHyt^G@1TlN+2uePL4s9ef1)UJ#-~1#F=>VMvea?Xl*$?obgFth zk4b<8NPq-LfCREgAn5?D#&=b*bTq$gR>3MOK57$!vMdrszXVZX&tj>PeyX&q9;xiB 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    Drivers