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Repository for my FPGA Stuff
VHDL Tcl Other
branch: master

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Binary7SegCounter
Memory added not working fifo and more ...
RamTest01 added not working fifo and more ...
TestFileIO started my File I/O Test Project
VGABufferRAM added not working fifo and more ...
VGATest fixed trhe RAM Project
led_sw_test added the README and played a bit around
Nexys3_Master.ucf
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