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_ngo
_xmsgs
iseconfig
planAhead_run_1
xlnx_auto_0_xdb
xst/work
Nexys3_Master 2.ucf
README
TEST04.gise
TEST04.xise
clockDivider.vhd
clockDivider2.vhd
main.bgn
main.bit
main.bld
main.cmd_log
main.drc
main.lso
main.ncd
main.ngc
main.ngd
main.ngr
main.pad
main.par
main.pcf
main.prj
main.ptwx
main.stx
main.syr
main.twr
main.twx
main.ucf
main.unroutes
main.ut
main.vhd
main.xpi
main.xst
main_bitgen.xwbt
main_envsettings.html
main_guide.ncd
main_map.map
main_map.mrp
main_map.ncd
main_map.ngm
main_map.xrpt
main_ngdbuild.xrpt
main_pad.csv
main_pad.txt
main_par.xrpt
main_summary.html
main_summary.xml
main_usage.xml
main_xst.xrpt
pa.fromNetlist.tcl
par_usage_statistics.html
planAhead.ngc2edif.log
sevenSegment.v
sevenSegment.vhd
usage_statistics_webtalk.html
webtalk.log
webtalk_pn.xml

README

This is my first VHDL Test Project for my NEXYS3 Board from digilent with an Spartan-6
What it does:
    You can set a binary number with the switches on the board.
    The 7-Segment Display, with the 4 digits, will display this number, after counting to it.
    It can count reverse or forward, depending on the current and new number.
What I have learned:
    FPGA 100mhz clock is too fast for the signals for the 7-Segment Display. It was not possible to multiplex it.
    When I reduced the clock speed, everything worked.
    Having multiple VHDL modules and used them in a main module.

This folder includes the full 13.2 ISE Project. You can clone this and open the project.
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