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  1. BaseJump STL: A Standard Template Library for SystemVerilog

    Verilog 57 9

  2. Tile based architecture designed for computing efficiency, scalability and generality

    Verilog 13 1

  3. This repository contains the complete toolchain used for the first MaPU chip

    C++ 1

281 contributions in the last year

Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Mon Wed Fri

Contribution activity

May - June 2019

ShawnLess has no activity yet for this period.

April 2019

Created a pull request in bespoke-silicon-group/bsg_manycore that received 4 comments

Pipeline Control Review and Bug Fix

When the pipeline stalled by MUL instruction and a remote load returns, the returned result is a load buffer. The forwarding logic in this case sho…

+159 −170 4 comments

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