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return OCCP to instance all 15 WCI masters and test on ml605

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1 parent 4433315 commit 19f64f6629a7863e8cc2409bfaf44704315b1e7d @ShepardSiegel committed Jul 5, 2012
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4 bsv/inf/OCCP.bsv
@@ -119,9 +119,9 @@ module mkOCCP#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (OCCPIfc#(Nwcit)
//return (i<6||i>9) ? mkWciMaster : mkWciMasterNull; // only instance the 11 (0:5,10:14) we need
//FIXME: Specalized for n210 platform development!
- return (i<7||i>11) ? mkWciMasterNull : mkWciMaster;
+ //return (i<7||i>11) ? mkWciMasterNull : mkWciMaster;
- //return mkWciMaster; // all get WCI masters
+ return mkWciMaster; // all get WCI masters
endfunction
Vector#(Nwcit,WciMasterIfc#(20,32)) wci <- genWithM(makeWciMaster);
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13,685 logs/ml605-20120705_1309/fpgaTop-ml605.srp
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5,852 logs/ml605-20120705_1309/fpgaTop.bld
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1,203 logs/ml605-20120705_1309/fpgaTop.par
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10,451 logs/ml605-20120705_1309/fpgaTop.twr
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8,272 logs/ml605-20120705_1309/fpgaTop_map.mrp
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22 rtl/mkCTop16B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
-// On Thu Jul 5 11:10:39 EDT 2012
+// On Thu Jul 5 12:35:43 EDT 2012
//
//
// Ports:
@@ -37,12 +37,12 @@
// wci_m_3_MAddr O 32
// wci_m_3_MData O 32 reg
// wci_m_3_MFlag O 2 reg
-// wci_m_4_MCmd O 3 const
-// wci_m_4_MAddrSpace O 1 const
-// wci_m_4_MByteEn O 4 const
-// wci_m_4_MAddr O 32 const
-// wci_m_4_MData O 32 const
-// wci_m_4_MFlag O 2 const
+// wci_m_4_MCmd O 3
+// wci_m_4_MAddrSpace O 1
+// wci_m_4_MByteEn O 4
+// wci_m_4_MAddr O 32
+// wci_m_4_MData O 32 reg
+// wci_m_4_MFlag O 2 reg
// cpNow O 64 reg
// RDY_cpNow O 1 const
// wsi_s_adc_SThreadBusy O 1 const
@@ -90,9 +90,9 @@
// wci_m_3_SResp I 2
// wci_m_3_SData I 32
// wci_m_3_SFlag I 2 reg
-// wci_m_4_SResp I 2 unused
-// wci_m_4_SData I 32 unused
-// wci_m_4_SFlag I 2 unused
+// wci_m_4_SResp I 2
+// wci_m_4_SData I 32
+// wci_m_4_SFlag I 2 reg
// wsi_s_adc_MCmd I 3 unused
// wsi_s_adc_MBurstLength I 12 unused
// wsi_s_adc_MData I 128 unused
@@ -107,7 +107,7 @@
// wci_m_1_SThreadBusy I 1 reg
// wci_m_2_SThreadBusy I 1 reg
// wci_m_3_SThreadBusy I 1 reg
-// wci_m_4_SThreadBusy I 1 unused
+// wci_m_4_SThreadBusy I 1 reg
// wsi_s_adc_MReqLast I 1 unused
// wsi_s_adc_MBurstPrecise I 1 unused
// wsi_s_adc_MReset_n I 1 unused
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14 rtl/mkFTop_ml605.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
-// On Thu Jul 5 11:10:45 EDT 2012
+// On Thu Jul 5 12:35:49 EDT 2012
//
//
// Ports:
@@ -2101,10 +2101,10 @@ module mkFTop_ml605(sys0_clkp,
!pciw_i2pAF_sInReset_isInReset &&
ctop$RDY_server_response_get ;
assign ctop$EN_cpServer_request_put =
- gbe0$RDY_cpClient_request_get && ctop$RDY_cpServer_request_put ;
+ ctop$RDY_cpServer_request_put && gbe0$RDY_cpClient_request_get ;
assign ctop$EN_cpServer_response_get =
- gbe0$RDY_cpClient_response_put &&
- ctop$RDY_cpServer_response_get ;
+ ctop$RDY_cpServer_response_get &&
+ gbe0$RDY_cpClient_response_put ;
assign ctop$wci_m_0_SThreadBusy = fmc150$wciS0_SThreadBusy ;
assign ctop$wci_m_1_SThreadBusy = flash0$wciS0_SThreadBusy ;
assign ctop$wci_m_2_SThreadBusy = gbe0$wciS0_SThreadBusy ;
@@ -2184,10 +2184,10 @@ module mkFTop_ml605(sys0_clkp,
assign gbe0$wsiS0_MBurstPrecise = 1'b0 ;
assign gbe0$wsiS0_MReset_n = 1'b0 ;
assign gbe0$EN_cpClient_request_get =
- gbe0$RDY_cpClient_request_get && ctop$RDY_cpServer_request_put ;
+ ctop$RDY_cpServer_request_put && gbe0$RDY_cpClient_request_get ;
assign gbe0$EN_cpClient_response_put =
- gbe0$RDY_cpClient_response_put &&
- ctop$RDY_cpServer_response_get ;
+ ctop$RDY_cpServer_response_get &&
+ gbe0$RDY_cpClient_response_put ;
// submodule lcd_ctrl
assign lcd_ctrl$setLine1_text = 128'h202073656C75522063696D6F74412020 ;
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21,221 rtl/mkOCCP.v
17,779 additions, 3,442 deletions not shown because the diff is too large. Please use a local Git client to view these changes.
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202 rtl/mkOCInf16B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
-// On Thu Jul 5 11:10:32 EDT 2012
+// On Thu Jul 5 12:35:36 EDT 2012
//
//
// Ports:
@@ -13,48 +13,48 @@
// cpServer_response_get O 40 reg
// RDY_cpServer_response_get O 1 reg
// led O 2 reg
-// wci_m_0_MCmd O 3 const
-// wci_m_0_MAddrSpace O 1 const
-// wci_m_0_MByteEn O 4 const
-// wci_m_0_MAddr O 32 const
-// wci_m_0_MData O 32 const
-// wci_m_0_MFlag O 2 const
-// wci_m_1_MCmd O 3 const
-// wci_m_1_MAddrSpace O 1 const
-// wci_m_1_MByteEn O 4 const
-// wci_m_1_MAddr O 32 const
-// wci_m_1_MData O 32 const
-// wci_m_1_MFlag O 2 const
-// wci_m_2_MCmd O 3 const
-// wci_m_2_MAddrSpace O 1 const
-// wci_m_2_MByteEn O 4 const
-// wci_m_2_MAddr O 32 const
-// wci_m_2_MData O 32 const
-// wci_m_2_MFlag O 2 const
-// wci_m_3_MCmd O 3 const
-// wci_m_3_MAddrSpace O 1 const
-// wci_m_3_MByteEn O 4 const
-// wci_m_3_MAddr O 32 const
-// wci_m_3_MData O 32 const
-// wci_m_3_MFlag O 2 const
-// wci_m_4_MCmd O 3 const
-// wci_m_4_MAddrSpace O 1 const
-// wci_m_4_MByteEn O 4 const
-// wci_m_4_MAddr O 32 const
-// wci_m_4_MData O 32 const
-// wci_m_4_MFlag O 2 const
-// wci_m_5_MCmd O 3 const
-// wci_m_5_MAddrSpace O 1 const
-// wci_m_5_MByteEn O 4 const
-// wci_m_5_MAddr O 32 const
-// wci_m_5_MData O 32 const
-// wci_m_5_MFlag O 2 const
-// wci_m_6_MCmd O 3 const
-// wci_m_6_MAddrSpace O 1 const
-// wci_m_6_MByteEn O 4 const
-// wci_m_6_MAddr O 32 const
-// wci_m_6_MData O 32 const
-// wci_m_6_MFlag O 2 const
+// wci_m_0_MCmd O 3
+// wci_m_0_MAddrSpace O 1
+// wci_m_0_MByteEn O 4
+// wci_m_0_MAddr O 32
+// wci_m_0_MData O 32 reg
+// wci_m_0_MFlag O 2 reg
+// wci_m_1_MCmd O 3
+// wci_m_1_MAddrSpace O 1
+// wci_m_1_MByteEn O 4
+// wci_m_1_MAddr O 32
+// wci_m_1_MData O 32 reg
+// wci_m_1_MFlag O 2 reg
+// wci_m_2_MCmd O 3
+// wci_m_2_MAddrSpace O 1
+// wci_m_2_MByteEn O 4
+// wci_m_2_MAddr O 32
+// wci_m_2_MData O 32 reg
+// wci_m_2_MFlag O 2 reg
+// wci_m_3_MCmd O 3
+// wci_m_3_MAddrSpace O 1
+// wci_m_3_MByteEn O 4
+// wci_m_3_MAddr O 32
+// wci_m_3_MData O 32 reg
+// wci_m_3_MFlag O 2 reg
+// wci_m_4_MCmd O 3
+// wci_m_4_MAddrSpace O 1
+// wci_m_4_MByteEn O 4
+// wci_m_4_MAddr O 32
+// wci_m_4_MData O 32 reg
+// wci_m_4_MFlag O 2 reg
+// wci_m_5_MCmd O 3
+// wci_m_5_MAddrSpace O 1
+// wci_m_5_MByteEn O 4
+// wci_m_5_MAddr O 32
+// wci_m_5_MData O 32 reg
+// wci_m_5_MFlag O 2 reg
+// wci_m_6_MCmd O 3
+// wci_m_6_MAddrSpace O 1
+// wci_m_6_MByteEn O 4
+// wci_m_6_MAddr O 32
+// wci_m_6_MData O 32 reg
+// wci_m_6_MFlag O 2 reg
// wci_m_7_MCmd O 3
// wci_m_7_MAddrSpace O 1
// wci_m_7_MByteEn O 4
@@ -85,12 +85,12 @@
// wci_m_11_MAddr O 32
// wci_m_11_MData O 32 reg
// wci_m_11_MFlag O 2 reg
-// wci_m_12_MCmd O 3 const
-// wci_m_12_MAddrSpace O 1 const
-// wci_m_12_MByteEn O 4 const
-// wci_m_12_MAddr O 32 const
-// wci_m_12_MData O 32 const
-// wci_m_12_MFlag O 2 const
+// wci_m_12_MCmd O 3
+// wci_m_12_MAddrSpace O 1
+// wci_m_12_MByteEn O 4
+// wci_m_12_MAddr O 32
+// wci_m_12_MData O 32 reg
+// wci_m_12_MFlag O 2 reg
// wmiDP0_SResp O 2 reg
// wmiDP0_SData O 128 reg
// wmiDP0_SThreadBusy O 1
@@ -130,27 +130,27 @@
// server_request_put I 153
// cpServer_request_put I 59 reg
// switch_x I 3 reg
-// wci_m_0_SResp I 2 unused
-// wci_m_0_SData I 32 unused
-// wci_m_0_SFlag I 2 unused
-// wci_m_1_SResp I 2 unused
-// wci_m_1_SData I 32 unused
-// wci_m_1_SFlag I 2 unused
-// wci_m_2_SResp I 2 unused
-// wci_m_2_SData I 32 unused
-// wci_m_2_SFlag I 2 unused
-// wci_m_3_SResp I 2 unused
-// wci_m_3_SData I 32 unused
-// wci_m_3_SFlag I 2 unused
-// wci_m_4_SResp I 2 unused
-// wci_m_4_SData I 32 unused
-// wci_m_4_SFlag I 2 unused
-// wci_m_5_SResp I 2 unused
-// wci_m_5_SData I 32 unused
-// wci_m_5_SFlag I 2 unused
-// wci_m_6_SResp I 2 unused
-// wci_m_6_SData I 32 unused
-// wci_m_6_SFlag I 2 unused
+// wci_m_0_SResp I 2
+// wci_m_0_SData I 32
+// wci_m_0_SFlag I 2 reg
+// wci_m_1_SResp I 2
+// wci_m_1_SData I 32
+// wci_m_1_SFlag I 2 reg
+// wci_m_2_SResp I 2
+// wci_m_2_SData I 32
+// wci_m_2_SFlag I 2 reg
+// wci_m_3_SResp I 2
+// wci_m_3_SData I 32
+// wci_m_3_SFlag I 2 reg
+// wci_m_4_SResp I 2
+// wci_m_4_SData I 32
+// wci_m_4_SFlag I 2 reg
+// wci_m_5_SResp I 2
+// wci_m_5_SData I 32
+// wci_m_5_SFlag I 2 reg
+// wci_m_6_SResp I 2
+// wci_m_6_SData I 32
+// wci_m_6_SFlag I 2 reg
// wci_m_7_SResp I 2
// wci_m_7_SData I 32
// wci_m_7_SFlag I 2 reg
@@ -166,9 +166,9 @@
// wci_m_11_SResp I 2
// wci_m_11_SData I 32
// wci_m_11_SFlag I 2 reg
-// wci_m_12_SResp I 2 unused
-// wci_m_12_SData I 32 unused
-// wci_m_12_SFlag I 2 unused
+// wci_m_12_SResp I 2
+// wci_m_12_SData I 32
+// wci_m_12_SFlag I 2 reg
// wmiDP0_MCmd I 3
// wmiDP0_MReqInfo I 1
// wmiDP0_MAddrSpace I 1
@@ -189,19 +189,19 @@
// uuid_arg I 512
// EN_server_request_put I 1
// EN_cpServer_request_put I 1
-// wci_m_0_SThreadBusy I 1 unused
-// wci_m_1_SThreadBusy I 1 unused
-// wci_m_2_SThreadBusy I 1 unused
-// wci_m_3_SThreadBusy I 1 unused
-// wci_m_4_SThreadBusy I 1 unused
-// wci_m_5_SThreadBusy I 1 unused
-// wci_m_6_SThreadBusy I 1 unused
+// wci_m_0_SThreadBusy I 1 reg
+// wci_m_1_SThreadBusy I 1 reg
+// wci_m_2_SThreadBusy I 1 reg
+// wci_m_3_SThreadBusy I 1 reg
+// wci_m_4_SThreadBusy I 1 reg
+// wci_m_5_SThreadBusy I 1 reg
+// wci_m_6_SThreadBusy I 1 reg
// wci_m_7_SThreadBusy I 1 reg
// wci_m_8_SThreadBusy I 1 reg
// wci_m_9_SThreadBusy I 1 reg
// wci_m_10_SThreadBusy I 1 reg
// wci_m_11_SThreadBusy I 1 reg
-// wci_m_12_SThreadBusy I 1 unused
+// wci_m_12_SThreadBusy I 1 reg
// wmiDP0_MReqLast I 1
// wmiDP0_MDataValid I 1
// wmiDP0_MDataLast I 1
@@ -1841,10 +1841,10 @@ module mkOCInf16B(pciDevice,
reg CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1;
wire [127 : 0] pkt__h7324, pw_data__h10312;
wire [57 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147;
- wire [31 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d364,
+ wire [31 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d353,
wreq_data__h6162;
- wire [15 : 0] pciDevice_BITS_15_TO_3_43_CONCAT_0___d372,
- pciDevice_BITS_15_TO_3_43_CONCAT_1___d356,
+ wire [15 : 0] pciDevice_BITS_15_TO_3_43_CONCAT_0___d361,
+ pciDevice_BITS_15_TO_3_43_CONCAT_1___d362,
pw_be__h10311;
wire [11 : 0] byteCount__h5138, x__h5357, x__h5359, y__h5358, y__h5360;
wire [6 : 0] lowAddr__h5137;
@@ -2491,7 +2491,7 @@ module mkOCInf16B(pciDevice,
// submodule dp0
mkOCDP16B #(.hasPush(1'd0),
.hasPull(1'd1),
- .hasDebugLogic(1'd1)) dp0(.pciDevice(pciDevice_BITS_15_TO_3_43_CONCAT_0___d372),
+ .hasDebugLogic(1'd1)) dp0(.pciDevice(pciDevice_BITS_15_TO_3_43_CONCAT_0___d361),
.CLK(CLK),
.RST_N(cp$RST_N_wci_Vm_13),
.server_request_put(dp0$server_request_put),
@@ -2536,7 +2536,7 @@ module mkOCInf16B(pciDevice,
// submodule dp1
mkOCDP16B #(.hasPush(1'd1),
.hasPull(1'd0),
- .hasDebugLogic(1'd1)) dp1(.pciDevice(pciDevice_BITS_15_TO_3_43_CONCAT_1___d356),
+ .hasDebugLogic(1'd1)) dp1(.pciDevice(pciDevice_BITS_15_TO_3_43_CONCAT_1___d362),
.CLK(CLK),
.RST_N(cp$RST_N_wci_Vm_14),
.server_request_put(dp1$server_request_put),
@@ -3154,35 +3154,35 @@ module mkOCInf16B(pciDevice,
assign noc_sm0$EN_c0_response_put =
noc_sm0$RDY_c0_response_put && cpTlp_outF$EMPTY_N ;
assign noc_sm0$EN_c1_request_get =
- noc_sm0$RDY_c1_request_get && noc_sm1$RDY_s_request_put ;
+ noc_sm1$RDY_s_request_put && noc_sm0$RDY_c1_request_get ;
assign noc_sm0$EN_c1_response_put =
- noc_sm0$RDY_c1_response_put && noc_sm1$RDY_s_response_get ;
+ noc_sm1$RDY_s_response_get && noc_sm0$RDY_c1_response_put ;
// submodule noc_sm1
assign noc_sm1$c0_response_put = dp0$server_response_get ;
assign noc_sm1$c1_response_put = noc_sm2$s_response_get ;
assign noc_sm1$s_request_put = noc_sm0$c1_request_get ;
assign noc_sm1$EN_s_request_put =
- noc_sm0$RDY_c1_request_get && noc_sm1$RDY_s_request_put ;
+ noc_sm1$RDY_s_request_put && noc_sm0$RDY_c1_request_get ;
assign noc_sm1$EN_s_response_get =
- noc_sm0$RDY_c1_response_put && noc_sm1$RDY_s_response_get ;
+ noc_sm1$RDY_s_response_get && noc_sm0$RDY_c1_response_put ;
assign noc_sm1$EN_c0_request_get =
noc_sm1$RDY_c0_request_get && dp0$RDY_server_request_put ;
assign noc_sm1$EN_c0_response_put =
noc_sm1$RDY_c0_response_put && dp0$RDY_server_response_get ;
assign noc_sm1$EN_c1_request_get =
- noc_sm1$RDY_c1_request_get && noc_sm2$RDY_s_request_put ;
+ noc_sm2$RDY_s_request_put && noc_sm1$RDY_c1_request_get ;
assign noc_sm1$EN_c1_response_put =
- noc_sm1$RDY_c1_response_put && noc_sm2$RDY_s_response_get ;
+ noc_sm2$RDY_s_response_get && noc_sm1$RDY_c1_response_put ;
// submodule noc_sm2
assign noc_sm2$c0_response_put = dp1$server_response_get ;
assign noc_sm2$c1_response_put = 153'h0 ;
assign noc_sm2$s_request_put = noc_sm1$c1_request_get ;
assign noc_sm2$EN_s_request_put =
- noc_sm1$RDY_c1_request_get && noc_sm2$RDY_s_request_put ;
+ noc_sm2$RDY_s_request_put && noc_sm1$RDY_c1_request_get ;
assign noc_sm2$EN_s_response_get =
- noc_sm1$RDY_c1_response_put && noc_sm2$RDY_s_response_get ;
+ noc_sm2$RDY_s_response_get && noc_sm1$RDY_c1_response_put ;
assign noc_sm2$EN_c0_request_get =
noc_sm2$RDY_c0_request_get && dp1$RDY_server_request_put ;
assign noc_sm2$EN_c0_response_put =
@@ -3191,7 +3191,7 @@ module mkOCInf16B(pciDevice,
assign noc_sm2$EN_c1_response_put = 1'b0 ;
// remaining internal signals
- assign IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d364 =
+ assign IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d353 =
(cpTlp_tlpReq[62] && !cpTlp_tlpFirst) ? v__h5606 : cpTlp_tlpDW ;
assign IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147 =
cpTlp_tlpReq[62] ?
@@ -3214,9 +3214,9 @@ module mkOCInf16B(pciDevice,
cpTlp_tlpFirst ||
CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1 ;
assign lowAddr__h5137 = { cpTlp_inF$D_OUT[38:34], lowAddr10__h5136 } ;
- assign pciDevice_BITS_15_TO_3_43_CONCAT_0___d372 =
+ assign pciDevice_BITS_15_TO_3_43_CONCAT_0___d361 =
{ pciDevice[15:3], 3'd0 } ;
- assign pciDevice_BITS_15_TO_3_43_CONCAT_1___d356 =
+ assign pciDevice_BITS_15_TO_3_43_CONCAT_1___d362 =
{ pciDevice[15:3], 3'd1 } ;
assign pkt__h7324 =
{ 9'd148,
@@ -3244,10 +3244,10 @@ module mkOCInf16B(pciDevice,
{ cpTlp_rdv[95:0], cpTlp_rdv[127:96] } :
cpTlp_rdv) ;
assign wreq_data__h6162 =
- { IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d364[7:0],
- IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d364[15:8],
- IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d364[23:16],
- IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d364[31:24] } ;
+ { IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d353[7:0],
+ IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d353[15:8],
+ IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d353[23:16],
+ IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d353[31:24] } ;
assign x__h10731 = 3'h4 - { 1'd0, cpTlp_rdp } ;
assign x__h5357 = x__h5359 - y__h5360 ;
assign x__h5359 = { cpTlp_inF$D_OUT[105:96], 2'b0 } ;

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