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removed altera/tom directory

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1 parent bbb9d16 commit 45d3d192ca8e937421a01b63cb35fb1a32af7847 @ShepardSiegel committed Oct 4, 2012
Showing with 19 additions and 21,551 deletions.
  1. +1 −1 rtl/mkBiasWorker16B.v
  2. +1 −1 rtl/mkBiasWorker32B.v
  3. +1 −1 rtl/mkBiasWorker4B.v
  4. +1 −1 rtl/mkBiasWorker8B.v
  5. +1 −1 rtl/mkOCCP.v
  6. +1 −1 rtl/mkPktFork.v
  7. +1 −1 rtl/mkPktMerge.v
  8. +1 −1 rtl/mkSimDCP.v
  9. +1 −1 rtl/mkSimIO.v
  10. +1 −1 rtl/mkTB18.v
  11. +1 −1 rtl/mkTLPCM.v
  12. +1 −1 rtl/mkTLPClientNode.v
  13. +1 −1 rtl/mkTLPSM.v
  14. +1 −1 rtl/mkTLPServerNode.v
  15. +1 −1 rtl/mkTimeClient.v
  16. +1 −1 rtl/mkWSICaptureWorker4B.v
  17. +1 −1 rtl/mkWSIPatternWorker4B.v
  18. +1 −1 rtl/mkWciInitiator.v
  19. +1 −1 rtl/mkWciTarget.v
  20. +0 −353 scripts/altera/tom20110927/ddr3_x16.v
  21. BIN scripts/altera/tom20110927/ddr3_x16_example.qar
  22. +0 −6 scripts/altera/tom20110927/ddr3_x16_example.qarlog
  23. +0 −41 ...3_test/ddr_core_example_design/example_project/ddr_core_example/submodules/alt_mem_ddrx_define.iv
  24. +0 −102 ...20110927/ddr3_x16_example_restored/4401/s5_11_1/ddr_core_example_design/example_project/debug.stp
  25. +0 −293 ...27/ddr3_x16_example_restored/4401/s5_11_1/ddr_core_example_design/example_project/generate_ed.tcl
  26. +0 −5 scripts/altera/tom20110927/ddr3_x16_example_restored/PLLJ_PLLSPE_INFO.txt
  27. +0 −711 scripts/altera/tom20110927/ddr3_x16_example_restored/assignment_defaults.qdf
  28. +0 −132 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.jdi
  29. +0 −172 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.qip
  30. +0 −30 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.qpf
  31. +0 −387 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.qsf
  32. +0 −315 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/ddr3_x16_example.v
  33. +0 −226 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/addr_gen.sv
  34. +0 −563 .../altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_addr_cmd.v
  35. +0 −746 ...ra/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_addr_cmd_wrap.v
  36. +0 −1,165 ...s/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_arbiter.v
  37. +0 −150 ...ts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_buffer.v
  38. +0 −260 ...a/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_buffer_manager.v
  39. +0 −1,447 ...altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_burst_gen.v
  40. +0 −138 ...a/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_burst_tracking.v
  41. +0 −2,417 ...s/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_cmd_gen.v
  42. +0 −2,400 ...ltera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_controller.v
  43. +0 −1,106 ...om20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_controller_st_top.v
  44. +0 −1,412 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_csr.v
  45. +0 −861 ...a/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_dataid_manager.v
  46. +0 −458 ...era/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ddr2_odt_gen.v
  47. +0 −362 ...era/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ddr3_odt_gen.v
  48. +0 −41 ...s/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_define.iv
  49. +0 −363 ...tera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_decoder.v
  50. +0 −439 ...m20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v
  51. +0 −666 ...m20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v
  52. +0 −287 ...tera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder.v
  53. +0 −288 ...m20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v
  54. +0 −394 ...m20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v
  55. +0 −1,136 .../ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
  56. +0 −236 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_fifo.v
  57. +0 −308 .../altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_input_if.v
  58. +0 −248 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_list.v
  59. +0 −371 .../tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v
  60. +0 −206 .../tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_mm_st_converter.v
  61. +0 −291 ...s/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example/submodules/alt_mem_ddrx_odt_gen.v
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2 rtl/mkBiasWorker16B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:33 EDT 2012
+// On Wed Oct 3 15:52:39 EDT 2012
//
//
// Ports:
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2 rtl/mkBiasWorker32B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:34 EDT 2012
+// On Wed Oct 3 15:52:40 EDT 2012
//
//
// Ports:
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2 rtl/mkBiasWorker4B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:31 EDT 2012
+// On Wed Oct 3 15:52:37 EDT 2012
//
//
// Ports:
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2 rtl/mkBiasWorker8B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:32 EDT 2012
+// On Wed Oct 3 15:52:38 EDT 2012
//
//
// Ports:
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2 rtl/mkOCCP.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:15:38 EDT 2012
+// On Wed Oct 3 15:53:44 EDT 2012
//
//
// Ports:
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2 rtl/mkPktFork.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:15:00 EDT 2012
+// On Wed Oct 3 15:53:06 EDT 2012
//
//
// Ports:
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2 rtl/mkPktMerge.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:59 EDT 2012
+// On Wed Oct 3 15:53:05 EDT 2012
//
//
// Ports:
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2 rtl/mkSimDCP.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:17 EDT 2012
+// On Wed Oct 3 15:52:23 EDT 2012
//
//
// Ports:
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2 rtl/mkSimIO.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:19 EDT 2012
+// On Wed Oct 3 15:52:25 EDT 2012
//
//
// Ports:
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2 rtl/mkTB18.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:16:00 EDT 2012
+// On Wed Oct 3 15:54:06 EDT 2012
//
//
// Ports:
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2 rtl/mkTLPCM.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:15:00 EDT 2012
+// On Wed Oct 3 15:53:06 EDT 2012
//
//
// Ports:
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2 rtl/mkTLPClientNode.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:15:00 EDT 2012
+// On Wed Oct 3 15:53:06 EDT 2012
//
//
// Ports:
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2 rtl/mkTLPSM.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:15:00 EDT 2012
+// On Wed Oct 3 15:53:06 EDT 2012
//
//
// Ports:
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2 rtl/mkTLPServerNode.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:15:00 EDT 2012
+// On Wed Oct 3 15:53:06 EDT 2012
//
//
// Ports:
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2 rtl/mkTimeClient.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:41 EDT 2012
+// On Wed Oct 3 15:52:47 EDT 2012
//
//
// Ports:
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2 rtl/mkWSICaptureWorker4B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:44 EDT 2012
+// On Wed Oct 3 15:52:50 EDT 2012
//
//
// Ports:
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2 rtl/mkWSIPatternWorker4B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:38 EDT 2012
+// On Wed Oct 3 15:52:44 EDT 2012
//
//
// Ports:
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2 rtl/mkWciInitiator.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:24 EDT 2012
+// On Wed Oct 3 15:52:30 EDT 2012
//
//
// Ports:
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2 rtl/mkWciTarget.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Wed Oct 3 11:14:25 EDT 2012
+// On Wed Oct 3 15:52:31 EDT 2012
//
//
// Ports:
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353 scripts/altera/tom20110927/ddr3_x16.v
@@ -1,353 +0,0 @@
-// megafunction wizard: %DDR3 SDRAM Controller with UniPHY v11.0%
-// GENERATION: XML
-// ddr3_x16.v
-
-//
-
-`timescale 1 ps / 1 ps
-module ddr3_x16 (
- input wire pll_ref_clk, // pll_ref_clk.clk
- input wire global_reset_n, // global_reset.reset_n
- input wire soft_reset_n, // soft_reset.reset_n
- output wire afi_clk, // afi_clk.clk
- output wire afi_half_clk, // afi_half_clk.clk
- output wire afi_reset_n, // afi_reset.reset_n
- output wire [12:0] mem_a, // memory.mem_a
- output wire [2:0] mem_ba, // .mem_ba
- output wire mem_ck, // .mem_ck
- output wire mem_ck_n, // .mem_ck_n
- output wire mem_cke, // .mem_cke
- output wire mem_cs_n, // .mem_cs_n
- output wire [1:0] mem_dm, // .mem_dm
- output wire mem_ras_n, // .mem_ras_n
- output wire mem_cas_n, // .mem_cas_n
- output wire mem_we_n, // .mem_we_n
- output wire mem_reset_n, // .mem_reset_n
- inout wire [15:0] mem_dq, // .mem_dq
- inout wire [1:0] mem_dqs, // .mem_dqs
- inout wire [1:0] mem_dqs_n, // .mem_dqs_n
- output wire mem_odt, // .mem_odt
- output wire avl_ready, // avl.waitrequest_n
- input wire avl_burstbegin, // .beginbursttransfer
- input wire [23:0] avl_addr, // .address
- output wire avl_rdata_valid, // .readdatavalid
- output wire [63:0] avl_rdata, // .readdata
- input wire [63:0] avl_wdata, // .writedata
- input wire [7:0] avl_be, // .byteenable
- input wire avl_read_req, // .read
- input wire avl_write_req, // .write
- input wire [2:0] avl_size, // .burstcount
- output wire local_init_done, // status.local_init_done
- output wire local_cal_success, // .local_cal_success
- output wire local_cal_fail, // .local_cal_fail
- input wire oct_rdn, // oct.rdn
- input wire oct_rup, // .rup
- output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
- input wire local_powerdn_req // .local_powerdn_req
- );
-
- ddr3_x16_0002 ddr3_x16_inst (
- .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
- .global_reset_n (global_reset_n), // global_reset.reset_n
- .soft_reset_n (soft_reset_n), // soft_reset.reset_n
- .afi_clk (afi_clk), // afi_clk.clk
- .afi_half_clk (afi_half_clk), // afi_half_clk.clk
- .afi_reset_n (afi_reset_n), // afi_reset.reset_n
- .mem_a (mem_a), // memory.mem_a
- .mem_ba (mem_ba), // .mem_ba
- .mem_ck (mem_ck), // .mem_ck
- .mem_ck_n (mem_ck_n), // .mem_ck_n
- .mem_cke (mem_cke), // .mem_cke
- .mem_cs_n (mem_cs_n), // .mem_cs_n
- .mem_dm (mem_dm), // .mem_dm
- .mem_ras_n (mem_ras_n), // .mem_ras_n
- .mem_cas_n (mem_cas_n), // .mem_cas_n
- .mem_we_n (mem_we_n), // .mem_we_n
- .mem_reset_n (mem_reset_n), // .mem_reset_n
- .mem_dq (mem_dq), // .mem_dq
- .mem_dqs (mem_dqs), // .mem_dqs
- .mem_dqs_n (mem_dqs_n), // .mem_dqs_n
- .mem_odt (mem_odt), // .mem_odt
- .avl_ready (avl_ready), // avl.waitrequest_n
- .avl_burstbegin (avl_burstbegin), // .beginbursttransfer
- .avl_addr (avl_addr), // .address
- .avl_rdata_valid (avl_rdata_valid), // .readdatavalid
- .avl_rdata (avl_rdata), // .readdata
- .avl_wdata (avl_wdata), // .writedata
- .avl_be (avl_be), // .byteenable
- .avl_read_req (avl_read_req), // .read
- .avl_write_req (avl_write_req), // .write
- .avl_size (avl_size), // .burstcount
- .local_init_done (local_init_done), // status.local_init_done
- .local_cal_success (local_cal_success), // .local_cal_success
- .local_cal_fail (local_cal_fail), // .local_cal_fail
- .oct_rdn (oct_rdn), // oct.rdn
- .oct_rup (oct_rup), // .rup
- .local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
- .local_powerdn_req (local_powerdn_req) // .local_powerdn_req
- );
-
-endmodule
-// Retrieval info: <?xml version="1.0"?>
-//<!--
-// Generated by Altera MegaWizard Launcher Utility version 1.0
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-// Copyright (C) 1991-2011 Altera Corporation
-// Any megafunction design, and related net list (encrypted or decrypted),
-// support information, device programming or simulation file, and any other
-// associated documentation or information provided by Altera or a partner
-// under Altera's Megafunction Partnership Program may be used only to
-// program PLD devices (but not masked PLD devices) from Altera. Any other
-// use of such megafunction design, net list, support information, device
-// programming or simulation file, or any other related documentation or
-// information is prohibited for any other purpose, including, but not
-// limited to modification, reverse engineering, de-compiling, or use with
-// any other silicon devices, unless such use is explicitly licensed under
-// a separate agreement with Altera or a megafunction partner. Title to
-// the intellectual property, including patents, copyrights, trademarks,
-// trade secrets, or maskworks, embodied in any such megafunction design,
-// net list, support information, device programming or simulation file, or
-// any other related documentation or information provided by Altera or a
-// megafunction partner, remains with Altera, the megafunction partner, or
-// their respective licensors. No other licenses, including any licenses
-// needed under any third party's intellectual property, are provided herein.
-//-->
-// Retrieval info: <instance entity-name="altera_mem_if_ddr3_emif" version="11.0" >
-// Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-// Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" />
-// Retrieval info: <generic name="AC_PARITY" value="false" />
-// Retrieval info: <generic name="RDIMM_CONFIG" value="0" />
-// Retrieval info: <generic name="DISCRETE_FLY_BY" value="false" />
-// Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-// Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-// Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="666.667" />
-// Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="13" />
-// Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-// Retrieval info: <generic name="MEM_DQ_WIDTH" value="16" />
-// Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-// Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-// Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-// Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-// Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-// Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-// Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-// Retrieval info: <generic name="MEM_CK_WIDTH" value="1" />
-// Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-// Retrieval info: <generic name="NEXTGEN" value="true" />
-// Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-// Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-// Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-// Retrieval info: <generic name="MEM_BL" value="OTF" />
-// Retrieval info: <generic name="MEM_BT" value="Sequential" />
-// Retrieval info: <generic name="MEM_ASR" value="Manual" />
-// Retrieval info: <generic name="MEM_SRT" value="Normal" />
-// Retrieval info: <generic name="MEM_PD" value="DLL on" />
-// Retrieval info: <generic name="MEM_DRV_STR" value="RZQ/7" />
-// Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-// Retrieval info: <generic name="MEM_RTT_NOM" value="ODT Disabled" />
-// Retrieval info: <generic name="MEM_RTT_WR" value="RZQ/4" />
-// Retrieval info: <generic name="MEM_WTCL" value="6" />
-// Retrieval info: <generic name="MEM_ATCL" value="Disabled" />
-// Retrieval info: <generic name="MEM_TCL" value="7" />
-// Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-// Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-// Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-// Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-// Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-// Retrieval info: <generic name="TIMING_TIS" value="190" />
-// Retrieval info: <generic name="TIMING_TIH" value="140" />
-// Retrieval info: <generic name="TIMING_TDS" value="30" />
-// Retrieval info: <generic name="TIMING_TDH" value="65" />
-// Retrieval info: <generic name="TIMING_TDQSQ" value="125" />
-// Retrieval info: <generic name="TIMING_TQH" value="0.38" />
-// Retrieval info: <generic name="TIMING_TDQSCK" value="255" />
-// Retrieval info: <generic name="TIMING_TDQSS" value="0.25" />
-// Retrieval info: <generic name="TIMING_TQSH" value="0.4" />
-// Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-// Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-// Retrieval info: <generic name="MEM_TINIT_US" value="500" />
-// Retrieval info: <generic name="MEM_TMRD_CK" value="4" />
-// Retrieval info: <generic name="MEM_TRAS_NS" value="36.0" />
-// Retrieval info: <generic name="MEM_TRCD_NS" value="13.5" />
-// Retrieval info: <generic name="MEM_TRP_NS" value="13.5" />
-// Retrieval info: <generic name="MEM_TREFI_US" value="7.8" />
-// Retrieval info: <generic name="MEM_TRFC_NS" value="110.0" />
-// Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-// Retrieval info: <generic name="MEM_TWTR" value="4" />
-// Retrieval info: <generic name="MEM_TFAW_NS" value="30.0" />
-// Retrieval info: <generic name="MEM_TRRD_NS" value="6.0" />
-// Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-// Retrieval info: <generic name="CSR_ADDR_WIDTH" value="8" />
-// Retrieval info: <generic name="CSR_DATA_WIDTH" value="32" />
-// Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-// Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-// Retrieval info: <generic name="AVL_MAX_SIZE" value="4" />
-// Retrieval info: <generic name="BYTE_ENABLE" value="false" />
-// Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-// Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-// Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-// Retrieval info: <generic name="MEM_AUTO_PD_CYCLES" value="0" />
-// Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-// Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-// Retrieval info: <generic name="ADDR_ORDER" value="0" />
-// Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-// Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-// Retrieval info: <generic name="CFG_REORDER_DATA" value="true" />
-// Retrieval info: <generic name="CFG_STARVE_LIMIT" value="10" />
-// Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-// Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-// Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-// Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-// Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-// Retrieval info: <generic name="MULTICAST_EN" value="false" />
-// Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-// Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-// Retrieval info: <generic name="DEBUG_MODE" value="false" />
-// Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-// Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-// Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-// Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-// Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-// Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-// Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-// Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-// Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-// Retrieval info: <generic name="REF_CLK_FREQ" value="100.0" />
-// Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-// Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-// Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-// Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-// Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-// Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-// Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-// Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-// Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-// Retrieval info: <generic name="READ_VALID_FIFO_SIZE" value="16" />
-// Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-// Retrieval info: <generic name="MAX_LATENCY_COUNT_WIDTH" value="5" />
-// Retrieval info: <generic name="DLL_DELAY_CHAIN_LENGTH" value="10" />
-// Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-// Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
-// Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-// Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-// Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-// Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-// Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-// Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-// Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-// Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-// Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-// Retrieval info: <generic name="QSYS_SEQUENCER_DEBUG" value="true" />
-// Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-// Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-// Retrieval info: <generic name="SEQ_MODE" value="0" />
-// Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-// Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-// Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-// Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-// Retrieval info: <generic name="MEM_VOLTAGE" value="1.5V DDR3" />
-// Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-// Retrieval info: <generic name="SKIP_MEM_INIT" value="true" />
-// Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-// Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-// Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-// Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-// Retrieval info: <generic name="CALIBRATION_MODE" value="Skip" />
-// Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-// Retrieval info: <generic name="NIOS_ROM_ADDRESS_WIDTH" value="12" />
-// Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-// Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-// Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-// Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-// Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-// Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-// Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-// Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-// Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-// Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-// Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-// Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-// Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-// Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-// Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-// Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-// Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-// Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-// Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-// Retrieval info: <generic name="RATE" value="Half" />
-// Retrieval info: <generic name="MEM_CLK_FREQ" value="533.0" />
-// Retrieval info: <generic name="DQS_TRK_ENABLED" value="false" />
-// Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
-// Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-// Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-// Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-// Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-// Retrieval info: <generic name="SPEED_GRADE" value="2" />
-// Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-// Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-// Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-// Retrieval info: </instance>
-// IPFS_FILES : NONE
View
BIN scripts/altera/tom20110927/ddr3_x16_example.qar
Binary file not shown.
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6 scripts/altera/tom20110927/ddr3_x16_example.qarlog
@@ -1,6 +0,0 @@
-
-
-******* Archived project restoration attempt on Tue Sep 27 13:05:07 2011
-Source archive file: /home/shep/projects/ocpi/scripts/altera/tom20110927/ddr3_x16_example.qar
-Archive was extracted into /home/shep/projects/ocpi/scripts/altera/tom20110927/ddr3_x16_example_restored/
- - successfully.
View
41 ...dr_core_example_design/example_project/ddr_core_example/submodules/alt_mem_ddrx_define.iv
@@ -1,41 +0,0 @@
-// (C) 2001-2011 Altera Corporation. All rights reserved.
-// Your use of Altera Corporation's design tools, logic functions and other
-// software and tools, and its AMPP partner logic functions, and any output
-// files any of the foregoing (including device programming or simulation
-// files), and any associated documentation or information are expressly subject
-// to the terms and conditions of the Altera Program License Subscription
-// Agreement, Altera MegaCore Function License Agreement, or other applicable
-// license agreement, including, without limitation, that your use is for the
-// sole purpose of programming logic devices manufactured by Altera and sold by
-// Altera or its authorized distributors. Please refer to the applicable
-// agreement for further details.
-
-
-//--------------------------------------------------------------------------------------------------------
-//
-// [START] MMR - Memory Mapped Register Definition
-//
-//--------------------------------------------------------------------------------------------------------
- //----------------------------------------------------------------------------------------------------
- // Generic Signals
- //----------------------------------------------------------------------------------------------------
- // cfg_type
- `define MMR_TYPE_DDR1 3'b000
- `define MMR_TYPE_DDR2 3'b001
- `define MMR_TYPE_DDR3 3'b010
- `define MMR_TYPE_LPDDR1 3'b011
- `define MMR_TYPE_LPDDR2 3'b100
-
- //----------------------------------------------------------------------------------------------------
- // Address Mapping Signals
- //----------------------------------------------------------------------------------------------------
- // cfg_addr_order
- `define MMR_ADDR_ORDER_CS_ROW_BA_COL 2'b00
- `define MMR_ADDR_ORDER_CS_BA_ROW_COL 2'b01
- `define MMR_ADDR_ORDER_ROW_CS_BA_COL 2'b10
-
-//--------------------------------------------------------------------------------------------------------
-//
-// [END] MMR - Memory Mapped Register Definition
-//
-//--------------------------------------------------------------------------------------------------------
View
102 .../ddr3_x16_example_restored/4401/s5_11_1/ddr_core_example_design/example_project/debug.stp
@@ -1,102 +0,0 @@
-<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP4SGX230(.|ES) (0x024090DD)" sof_file="">
- <display_tree gui_logging_enabled="0">
- <display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
- </display_tree>
- <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
- <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
- <position_info>
- <single attribute="active tab" value="1"/>
- </position_info>
- <signal_set global_temp="1" name="signal_set: 2011/09/27 11:39:24 #0">
- <clock name="ddr3_x16_example_d0:d0|clk" polarity="posedge" tap_mode="classic"/>
- <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="512" trigger_in_enable="no" trigger_out_enable="no"/>
- <top_entity/>
- <signal_vec>
- <trigger_input_vec>
- <wire name="ddr3_x16_example_d0:d0|fail" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_d0:d0|pass" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_d0:d0|test_complete" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_cal_fail" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_cal_success" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_init_done" tap_mode="classic" type="combinatorial"/>
- </trigger_input_vec>
- <data_input_vec>
- <wire name="ddr3_x16_example_d0:d0|fail" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_d0:d0|pass" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_d0:d0|test_complete" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_cal_fail" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_cal_success" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_init_done" tap_mode="classic" type="combinatorial"/>
- </data_input_vec>
- <storage_qualifier_input_vec>
- <wire name="ddr3_x16_example_d0:d0|fail" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_d0:d0|pass" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_d0:d0|test_complete" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_cal_fail" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_cal_success" tap_mode="classic" type="combinatorial"/>
- <wire name="ddr3_x16_example_if0:if0|local_init_done" tap_mode="classic" type="combinatorial"/>
- </storage_qualifier_input_vec>
- </signal_vec>
- <presentation>
- <data_view>
- <net is_signal_inverted="no" name="ddr3_x16_example_if0:if0|local_cal_fail"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_if0:if0|local_cal_success"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_if0:if0|local_init_done"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_d0:d0|pass"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_d0:d0|fail"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_d0:d0|test_complete"/>
- </data_view>
- <setup_view>
- <net is_signal_inverted="no" name="ddr3_x16_example_if0:if0|local_cal_fail"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_if0:if0|local_cal_success"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_if0:if0|local_init_done"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_d0:d0|pass"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_d0:d0|fail"/>
- <net is_signal_inverted="no" name="ddr3_x16_example_d0:d0|test_complete"/>
- </setup_view>
- </presentation>
- <trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2011/09/27 11:39:24 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="64" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
- <power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
- <events use_custom_flow_control="no">
- <level enabled="yes" name="condition1" type="basic">
- <power_up enabled="yes">
- </power_up>
- <op_node/>
- </level>
- </events>
- <storage_qualifier_events>
- <transitional>000000
- <pwr_up_transitional>000000</pwr_up_transitional>
- </transitional>
- <storage_qualifier_level type="basic">
- <power_up>
- </power_up>
- <op_node/>
- </storage_qualifier_level>
- <storage_qualifier_level type="basic">
- <power_up>
- </power_up>
- <op_node/>
- </storage_qualifier_level>
- <storage_qualifier_level type="basic">
- <power_up>
- </power_up>
- <op_node/>
- </storage_qualifier_level>
- </storage_qualifier_events>
- </trigger>
- </signal_set>
- </instance>
- <mnemonics/>
- <global_info>
- <single attribute="active instance" value="0"/>
- <single attribute="config widget visible" value="1"/>
- <single attribute="data log widget visible" value="1"/>
- <single attribute="hierarchy widget visible" value="1"/>
- <single attribute="instance widget visible" value="1"/>
- <single attribute="jtag widget visible" value="1"/>
- <multi attribute="frame size" size="2" value="1501,1028"/>
- <multi attribute="jtag widget size" size="2" value="334,120"/>
- </global_info>
- <static_plugin_mnemonics/>
-</session>
View
293 ...x16_example_restored/4401/s5_11_1/ddr_core_example_design/example_project/generate_ed.tcl
@@ -1,293 +0,0 @@
-set arg_list [list]
-lappend arg_list "--system-info=DEVICE_FAMILY=STRATIXV"
-lappend arg_list "--file-set=QUARTUS_SYNTH"
-lappend arg_list "--report-file=csv:ddr_core_example.csv"
-lappend arg_list "--report-file=qip:ddr_core_example.qip"
-lappend arg_list "--output-name=ddr_core_example"
-lappend arg_list "--component-param=TG_NUM_DRIVER_LOOP=1"
-lappend arg_list "--component-param=ABSTRACT_REAL_COMPARE_TEST=false"
-lappend arg_list "--component-param=ABS_RAM_MEM_INIT_FILENAME=meminit"
-lappend arg_list "--component-param=AC_PARITY=false"
-lappend arg_list "--component-param=ADDR_ORDER=0"
-lappend arg_list "--component-param=ADD_EFFICIENCY_MONITOR=false"
-lappend arg_list "--component-param=ADVANCED_CK_PHASES=true"
-lappend arg_list "--component-param=ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false"
-lappend arg_list "--component-param=AFI_DEBUG_INFO_WIDTH=32"
-lappend arg_list "--component-param=ALLOW_BIDIR_MEM_CK=false"
-lappend arg_list "--component-param=AUTO_POWERDN_EN=false"
-lappend arg_list "--component-param=AVL_DATA_WIDTH_PORT_0=0"
-lappend arg_list "--component-param=AVL_DATA_WIDTH_PORT_1=0"
-lappend arg_list "--component-param=AVL_DATA_WIDTH_PORT_2=0"
-lappend arg_list "--component-param=AVL_DATA_WIDTH_PORT_3=0"
-lappend arg_list "--component-param=AVL_DATA_WIDTH_PORT_4=0"
-lappend arg_list "--component-param=AVL_DATA_WIDTH_PORT_5=0"
-lappend arg_list "--component-param=AVL_MAX_SIZE=4"
-lappend arg_list "--component-param=BYTE_ENABLE=false"
-lappend arg_list "--component-param=C2P_WRITE_CLOCK_ADD_PHASE=67.5"
-lappend arg_list "--component-param=CALIBRATION_MODE=Skip"
-lappend arg_list "--component-param=CALIB_REG_WIDTH=8"
-lappend arg_list "--component-param=CFG_DATA_REORDERING_TYPE=INTER_BANK"
-lappend arg_list "--component-param=CFG_REORDER_DATA=true"
-lappend arg_list "--component-param=CFG_STARVE_LIMIT=10"
-lappend arg_list "--component-param=CFG_TCCD_NS=2.5"
-lappend arg_list "--component-param=COMMAND_PHASE=90.0"
-lappend arg_list "--component-param=CONTROLLER_LATENCY=5"
-lappend arg_list "--component-param=CPORT_TYPE_PORT_0=0"
-lappend arg_list "--component-param=CPORT_TYPE_PORT_1=0"
-lappend arg_list "--component-param=CPORT_TYPE_PORT_2=0"
-lappend arg_list "--component-param=CPORT_TYPE_PORT_3=0"
-lappend arg_list "--component-param=CPORT_TYPE_PORT_4=0"
-lappend arg_list "--component-param=CPORT_TYPE_PORT_5=0"
-lappend arg_list "--component-param=CTL_AUTOPCH_EN=false"
-lappend arg_list "--component-param=CTL_CMD_QUEUE_DEPTH=8"
-lappend arg_list "--component-param=CTL_CSR_CONNECTION=INTERNAL_JTAG"
-lappend arg_list "--component-param=CTL_CSR_ENABLED=false"
-lappend arg_list "--component-param=CTL_CSR_READ_ONLY=1"
-lappend arg_list "--component-param=CTL_DEEP_POWERDN_EN=false"
-lappend arg_list "--component-param=CTL_DYNAMIC_BANK_ALLOCATION=false"
-lappend arg_list "--component-param=CTL_DYNAMIC_BANK_NUM=4"
-lappend arg_list "--component-param=CTL_ECC_AUTO_CORRECTION_ENABLED=false"
-lappend arg_list "--component-param=CTL_ECC_ENABLED=false"
-lappend arg_list "--component-param=CTL_ENABLE_BURST_INTERRUPT=false"
-lappend arg_list "--component-param=CTL_ENABLE_BURST_TERMINATE=false"
-lappend arg_list "--component-param=CTL_HRB_ENABLED=false"
-lappend arg_list "--component-param=CTL_LOOK_AHEAD_DEPTH=4"
-lappend arg_list "--component-param=CTL_SELF_REFRESH_EN=false"
-lappend arg_list "--component-param=CTL_USR_REFRESH_EN=false"
-lappend arg_list "--component-param=DAT_DATA_WIDTH=32"
-lappend arg_list "--component-param=DEBUG_MODE=false"
-lappend arg_list "--component-param=DEFAULT_FAST_SIM_MODEL=true"
-lappend arg_list "--component-param=DEVICE_DEPTH=1"
-lappend arg_list "--component-param=DEVICE_FAMILY_PARAM="
-lappend arg_list "--component-param=DISABLE_CHILD_MESSAGING=false"
-lappend arg_list "--component-param=DISCRETE_FLY_BY=true"
-lappend arg_list "--component-param=DLL_SHARING_MODE=None"
-lappend arg_list "--component-param=DQS_DQSN_MODE=DIFFERENTIAL"
-lappend arg_list "--component-param=DQS_TRK_ENABLED=false"
-lappend arg_list "--component-param=DQ_INPUT_REG_USE_CLKN=false"
-lappend arg_list "--component-param=ENABLE_ABS_RAM_MEM_INIT=false"
-lappend arg_list "--component-param=ENABLE_BONDING=false"
-lappend arg_list "--component-param=ENABLE_BURST_MERGE=false"
-lappend arg_list "--component-param=ENABLE_CTRL_AVALON_INTERFACE=true"
-lappend arg_list "--component-param=ENABLE_EMIT_BFM_MASTER=false"
-lappend arg_list "--component-param=ENABLE_EXTRA_REPORTING=false"
-lappend arg_list "--component-param=ENABLE_ISS_PROBES=false"
-lappend arg_list "--component-param=EXTRA_SETTINGS="
-lappend arg_list "--component-param=FORCE_SYNTHESIS_LANGUAGE="
-lappend arg_list "--component-param=HARD_PHY=false"
-lappend arg_list "--component-param=HCX_COMPAT_MODE=false"
-lappend arg_list "--component-param=HCX_COMPAT_MODE=false"
-lappend arg_list "--component-param=HHP_HPS=false"
-lappend arg_list "--component-param=HHP_REMAP_ADDR=true"
-lappend arg_list "--component-param=INCLUDE_BOARD_DELAY_MODEL=false"
-lappend arg_list "--component-param=IP_TYPE=0"
-lappend arg_list "--component-param=LOCAL_ID_WIDTH=8"
-lappend arg_list "--component-param=MAX_LATENCY_COUNT_WIDTH=5"
-lappend arg_list "--component-param=MEM_ASR=Manual"
-lappend arg_list "--component-param=MEM_ATCL=Disabled"
-lappend arg_list "--component-param=MEM_AUTO_LEVELING_MODE=true"
-lappend arg_list "--component-param=MEM_AUTO_PD_CYCLES=0"
-lappend arg_list "--component-param=MEM_BANKADDR_WIDTH=3"
-lappend arg_list "--component-param=MEM_BL=OTF"
-lappend arg_list "--component-param=MEM_BT=Sequential"
-lappend arg_list "--component-param=MEM_CK_PHASE=0.0"
-lappend arg_list "--component-param=MEM_CK_WIDTH=1"
-lappend arg_list "--component-param=MEM_CLK_FREQ=800.0"
-lappend arg_list "--component-param=MEM_CLK_FREQ_MAX=800.0"
-lappend arg_list "--component-param=MEM_COL_ADDR_WIDTH=10"
-lappend arg_list "--component-param=MEM_DEVICE=MISSING_MODEL"
-lappend arg_list "--component-param=MEM_DLL_EN=true"
-lappend arg_list "--component-param=MEM_DQ_PER_DQS=8"
-lappend arg_list "--component-param=MEM_DQ_WIDTH=72"
-lappend arg_list "--component-param=MEM_DRV_STR=RZQ/6"
-lappend arg_list "--component-param=MEM_FORMAT=UNBUFFERED"
-lappend arg_list "--component-param=MEM_GUARANTEED_WRITE_INIT=false"
-lappend arg_list "--component-param=MEM_IF_BOARD_BASE_DELAY=10"
-lappend arg_list "--component-param=MEM_IF_DM_PINS_EN=true"
-lappend arg_list "--component-param=MEM_IF_DQSN_EN=true"
-lappend arg_list "--component-param=MEM_IF_SIM_VALID_WINDOW=0"
-lappend arg_list "--component-param=MEM_INIT_EN=false"
-lappend arg_list "--component-param=MEM_INIT_FILE="
-lappend arg_list "--component-param=MEM_MIRROR_ADDRESSING=0"
-lappend arg_list "--component-param=MEM_NUMBER_OF_DIMMS=1"
-lappend arg_list "--component-param=MEM_NUMBER_OF_RANKS_PER_DEVICE=1"
-lappend arg_list "--component-param=MEM_NUMBER_OF_RANKS_PER_DIMM=1"
-lappend arg_list "--component-param=MEM_PD=DLL off"
-lappend arg_list "--component-param=MEM_ROW_ADDR_WIDTH=15"
-lappend arg_list "--component-param=MEM_RTT_NOM=RZQ/2"
-lappend arg_list "--component-param=MEM_RTT_WR=Dynamic ODT off"
-lappend arg_list "--component-param=MEM_SRT=Normal"
-lappend arg_list "--component-param=MEM_TCL=7"
-lappend arg_list "--component-param=MEM_TFAW_NS=37.5"
-lappend arg_list "--component-param=MEM_TINIT_US=500"
-lappend arg_list "--component-param=MEM_TMRD_CK=4"
-lappend arg_list "--component-param=MEM_TRAS_NS=37.5"
-lappend arg_list "--component-param=MEM_TRCD_NS=13.125"
-lappend arg_list "--component-param=MEM_TREFI_US=7.8"
-lappend arg_list "--component-param=MEM_TRFC_NS=160.0"
-lappend arg_list "--component-param=MEM_TRP_NS=13.125"
-lappend arg_list "--component-param=MEM_TRRD_NS=7.5"
-lappend arg_list "--component-param=MEM_TRTP_NS=7.5"
-lappend arg_list "--component-param=MEM_TWR_NS=15.0"
-lappend arg_list "--component-param=MEM_TWTR=4"
-lappend arg_list "--component-param=MEM_USER_LEVELING_MODE=Leveling"
-lappend arg_list "--component-param=MEM_VENDOR=Micron"
-lappend arg_list "--component-param=MEM_VERBOSE=true"
-lappend arg_list "--component-param=MEM_VOLTAGE=1.5V DDR3"
-lappend arg_list "--component-param=MEM_WTCL=6"
-lappend arg_list "--component-param=MPFE_ENABLED=false"
-lappend arg_list "--component-param=MULTICAST_EN=false"
-lappend arg_list "--component-param=NEXTGEN=true"
-lappend arg_list "--component-param=NEXTGEN=true"
-lappend arg_list "--component-param=NIOS_ROM_DATA_WIDTH=32"
-lappend arg_list "--component-param=NUM_EXTRA_REPORT_PATH=10"
-lappend arg_list "--component-param=NUM_OF_PORTS=1"
-lappend arg_list "--component-param=OCT_SHARING_MODE=None"
-lappend arg_list "--component-param=PACKAGE_DESKEW=false"
-lappend arg_list "--component-param=PARSE_FRIENDLY_DEVICE_FAMILY_PARAM="
-lappend arg_list "--component-param=PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false"
-lappend arg_list "--component-param=PHY_CSR_CONNECTION=INTERNAL_JTAG"
-lappend arg_list "--component-param=PHY_CSR_ENABLED=false"
-lappend arg_list "--component-param=PHY_ONLY=false"
-lappend arg_list "--component-param=PLL_ADDR_CMD_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_ADDR_CMD_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_AFI_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_AFI_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_AFI_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_AFI_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_AFI_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_AFI_HALF_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_AFI_HALF_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_AFI_HALF_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_C2P_WRITE_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_C2P_WRITE_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_CLK_PARAM_VALID=false"
-lappend arg_list "--component-param=PLL_CONFIG_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_CONFIG_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_CONFIG_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_CONFIG_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_DR_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_DR_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_DR_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_DR_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_DR_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_HR_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_HR_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_HR_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_HR_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_HR_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_LOCATION=Top_Bottom"
-lappend arg_list "--component-param=PLL_MEM_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_MEM_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_MEM_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_MEM_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_MEM_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_NIOS_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_NIOS_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_NIOS_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_NIOS_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_NIOS_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_P2C_READ_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_P2C_READ_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_P2C_READ_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_P2C_READ_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_SHARING_MODE=None"
-lappend arg_list "--component-param=PLL_WRITE_CLK_DIV_PARAM=0"
-lappend arg_list "--component-param=PLL_WRITE_CLK_FREQ_PARAM=0.0"
-lappend arg_list "--component-param=PLL_WRITE_CLK_FREQ_SIM_STR_PARAM="
-lappend arg_list "--component-param=PLL_WRITE_CLK_MULT_PARAM=0"
-lappend arg_list "--component-param=PLL_WRITE_CLK_PHASE_PS_PARAM=0"
-lappend arg_list "--component-param=PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM="
-lappend arg_list "--component-param=POWER_OF_TWO_BUS=false"
-lappend arg_list "--component-param=PRIORITY_PORT_0=0"
-lappend arg_list "--component-param=PRIORITY_PORT_1=0"
-lappend arg_list "--component-param=PRIORITY_PORT_2=0"
-lappend arg_list "--component-param=PRIORITY_PORT_3=0"
-lappend arg_list "--component-param=PRIORITY_PORT_4=0"
-lappend arg_list "--component-param=PRIORITY_PORT_5=0"
-lappend arg_list "--component-param=RATE=Quarter"
-lappend arg_list "--component-param=RDIMM_CONFIG=0"
-lappend arg_list "--component-param=READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS"
-lappend arg_list "--component-param=READ_FIFO_SIZE=8"
-lappend arg_list "--component-param=READ_VALID_FIFO_SIZE=16"
-lappend arg_list "--component-param=REF_CLK_FREQ=125.0"
-lappend arg_list "--component-param=REF_CLK_FREQ_MAX_PARAM=0.0"
-lappend arg_list "--component-param=REF_CLK_FREQ_MIN_PARAM=0.0"
-lappend arg_list "--component-param=REF_CLK_FREQ_PARAM_VALID=false"
-lappend arg_list "--component-param=SEQUENCER_TYPE=NIOS"
-lappend arg_list "--component-param=SEQ_MODE=0"
-lappend arg_list "--component-param=SKIP_MEM_INIT=true"
-lappend arg_list "--component-param=SKIP_RBC_VALIDATION=true"
-lappend arg_list "--component-param=SOPC_COMPAT_RESET=false"
-lappend arg_list "--component-param=SPEED_GRADE=2"
-lappend arg_list "--component-param=SYS_INFO_DEVICE_FAMILY=Stratix V"
-lappend arg_list "--component-param=TIMING_BOARD_AC_EYE_REDUCTION_H=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_AC_SKEW=0.02"
-lappend arg_list "--component-param=TIMING_BOARD_AC_SLEW_RATE=1.0"
-lappend arg_list "--component-param=TIMING_BOARD_AC_TO_CK_SKEW=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_CK_CKN_SLEW_RATE=2.0"
-lappend arg_list "--component-param=TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_DERATE_METHOD=AUTO"
-lappend arg_list "--component-param=TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0"
-lappend arg_list "--component-param=TIMING_BOARD_DQ_EYE_REDUCTION=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_DQ_SLEW_RATE=1.0"
-lappend arg_list "--component-param=TIMING_BOARD_DQ_TO_DQS_SKEW=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_ISI_METHOD=AUTO"
-lappend arg_list "--component-param=TIMING_BOARD_MAX_CK_DELAY=0.6"
-lappend arg_list "--component-param=TIMING_BOARD_MAX_DQS_DELAY=0.6"
-lappend arg_list "--component-param=TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05"
-lappend arg_list "--component-param=TIMING_BOARD_SKEW_BETWEEN_DQS=0.02"
-lappend arg_list "--component-param=TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.01"
-lappend arg_list "--component-param=TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=-0.01"
-lappend arg_list "--component-param=TIMING_BOARD_SKEW_WITHIN_DQS=0.02"
-lappend arg_list "--component-param=TIMING_BOARD_TDH=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_TDS=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_TIH=0.0"
-lappend arg_list "--component-param=TIMING_BOARD_TIS=0.0"
-lappend arg_list "--component-param=TIMING_TDH=100"
-lappend arg_list "--component-param=TIMING_TDQSCK=300"
-lappend arg_list "--component-param=TIMING_TDQSQ=150"
-lappend arg_list "--component-param=TIMING_TDQSS=0.25"
-lappend arg_list "--component-param=TIMING_TDS=25"
-lappend arg_list "--component-param=TIMING_TDSH=0.2"
-lappend arg_list "--component-param=TIMING_TDSS=0.2"
-lappend arg_list "--component-param=TIMING_TIH=200"
-lappend arg_list "--component-param=TIMING_TIS=125"
-lappend arg_list "--component-param=TIMING_TQH=0.38"
-lappend arg_list "--component-param=TIMING_TQSH=0.38"
-lappend arg_list "--component-param=USER_DEBUG_LEVEL=1"
-lappend arg_list "--component-param=USE_AXI_ADAPTOR=false"
-lappend arg_list "--component-param=USE_FAKE_PHY=false"
-lappend arg_list "--component-param=USE_MM_ADAPTOR=true"
-lappend arg_list "--component-param=USE_SEQUENCER_APB_BRIDGE=false"
-lappend arg_list "--component-param=USE_SEQUENCER_BFM=false"
-lappend arg_list "--component-param=WEIGHT_PORT_0=0"
-lappend arg_list "--component-param=WEIGHT_PORT_1=0"
-lappend arg_list "--component-param=WEIGHT_PORT_2=0"
-lappend arg_list "--component-param=WEIGHT_PORT_3=0"
-lappend arg_list "--component-param=WEIGHT_PORT_4=0"
-lappend arg_list "--component-param=WEIGHT_PORT_5=0"
-lappend arg_list "--component-param=WRBUFFER_ADDR_WIDTH=6"
-catch { eval [concat [list exec "C:/altera/11.1fb/quartus//sopc_builder/bin/ip-generate" --component-name=alt_mem_if_ddr3_tg_ed] $arg_list] } temp
-puts $temp
View
5 scripts/altera/tom20110927/ddr3_x16_example_restored/PLLJ_PLLSPE_INFO.txt
@@ -1,5 +0,0 @@
-PLL_Name ddr3_x16_example_if0:if0|ddr3_x16_example_if0_p0:p0|ddr3_x16_example_if0_p0_controller_phy:controller_phy_inst|ddr3_x16_example_if0_p0_memphy_top:memphy_top_inst|ddr3_x16_example_if0_p0_pll_memphy:upll_memphy|altpll:altpll_component|ddr3_x16_example_if0_p0_pll_memphy_altpll:auto_generated|pll1
-PLLJITTER NA
-PLLSPEmax 40
-PLLSPEmin -40
-
View
711 scripts/altera/tom20110927/ddr3_x16_example_restored/assignment_defaults.qdf
@@ -1,711 +0,0 @@
-# Default value changes
-#
-# In 10.1, the default value of assignment FAMILY has changed to "Cyclone IV GX"
-# In 10.0, the default value of assignment OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING has changed to "Normal"
-# In 9.1, the default value of assignment PARALLEL_SYNTHESIS has changed to "On"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GZ"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "HardCopy III"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV GX"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix IV"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV E"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "HardCopy IV"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone III"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone III LS"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix III"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GX"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GZ"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "HardCopy III"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV GX"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix IV"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV E"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "HardCopy IV"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone III"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone III LS"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix III"
-# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GX"
-# In 9.0, the default value of assignment ENABLE_BENEFICIAL_SKEW_OPTIMIZATION has changed to "On"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria II GZ"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "HardCopy III"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone IV GX"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Stratix IV"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone IV E"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "HardCopy IV"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone III LS"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone III"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Stratix III"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria GX"
-# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria II GX"
-# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone IV E"
-# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone III"
-# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone IV GX"
-# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone III LS"
-# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Stratix III"
-# In 7.2, the default value of assignment POWER_REPORT_SIGNAL_ACTIVITY has changed to "Off"
-# In 7.2, the default value of assignment POWER_REPORT_POWER_DISSIPATION has changed to "Off"
-# In 5.1, the default value of assignment ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS has changed to "On"
-# In 5.1, the default value of assignment STRATIXII_MRAM_COMPATIBILITY has changed to "Off"
-# In 5.0, the default value of assignment SMART_RECOMPILE has changed to "Off"
-# In 5.0, the default value of assignment SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF has changed to "On"
-# In 4.1, the default value of assignment FITTER_EFFORT has changed to "Auto Fit"
-
-
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name SMART_RECOMPILE Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
-set_global_assignment -name REVISION_TYPE Base
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
-set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
-set_global_assignment -name MUX_RESTRUCTURE Auto
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name DISABLE_OCP_HW_EVAL Off
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name FAMILY "Cyclone IV GX"
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name SAFE_STATE_MACHINE Off
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
-set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
-set_global_assignment -name PARALLEL_SYNTHESIS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
-set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
-set_global_assignment -name AUTO_CASCADE_CHAINS On
-set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name AUTO_ROM_RECOGNITION On
-set_global_assignment -name AUTO_RAM_RECOGNITION On
-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
-set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name STRICT_RAM_RECOGNITION Off
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
-set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
-set_global_assignment -name REPORT_PARAMETER_SETTINGS On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
-set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
-set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
-set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
-set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
-set_global_assignment -name SYNTHESIS_EFFORT Auto
-set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
-set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
-set_global_assignment -name MAX_LABS "-1 (Unlimited)"
-set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
-set_global_assignment -name SYNTHESIS_SEED 1
-set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name AUTO_MERGE_PLLS On
-set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
-set_global_assignment -name TXPMA_SLEW_RATE Low
-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name ARRIAV_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS Off
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
-set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
-set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
-set_global_assignment -name AUTO_RESTART_CONFIGURATION On
-set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
-set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
-set_global_assignment -name ENABLE_OCT_DONE Off
-set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
-set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
-set_global_assignment -name START_TIME 0ns
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
-set_global_assignment -name SETUP_HOLD_DETECTION Off
-set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
-set_global_assignment -name CHECK_OUTPUTS Off
-set_global_assignment -name SIMULATION_COVERAGE On
-set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name GLITCH_DETECTION Off
-set_global_assignment -name GLITCH_INTERVAL 1ns
-set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
-set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
-set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
-set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
-set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
-set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
-set_global_assignment -name DRC_TOP_FANOUT 50
-set_global_assignment -name DRC_FANOUT_EXCEEDING 30
-set_global_assignment -name DRC_GATED_CLOCK_FEED 30
-set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
-set_global_assignment -name ENABLE_DRC_SETTINGS Off
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
-set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
-set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
-set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
-set_global_assignment -name MERGE_HEX_FILE Off
-set_global_assignment -name GENERATE_SVF_FILE Off
-set_global_assignment -name GENERATE_ISC_FILE Off
-set_global_assignment -name GENERATE_JAM_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
-set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
-set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
-set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
-set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_USE_PVA On
-set_global_assignment -name POWER_USE_INPUT_FILE "No File"
-set_global_assignment -name POWER_USE_INPUT_FILES Off
-set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
-set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
-set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
-set_global_assignment -name POWER_TJ_VALUE 25
-set_global_assignment -name POWER_USE_TA_VALUE 25
-set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
-set_global_assignment -name POWER_BOARD_TEMPERATURE 25
-set_global_assignment -name IGNORE_PARTITIONS Off
-set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
-set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
-set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
-set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
-set_global_assignment -name RTLV_GROUP_RELATED_NODES On
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
-set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
-set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
-set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
-set_global_assignment -name EQC_BBOX_MERGE On
-set_global_assignment -name EQC_LVDS_MERGE On
-set_global_assignment -name EQC_RAM_UNMERGING On
-set_global_assignment -name EQC_DFF_SS_EMULATION On
-set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
-set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
-set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
-set_global_assignment -name EQC_STRUCTURE_MATCHING On
-set_global_assignment -name EQC_AUTO_BREAK_CONE On
-set_global_assignment -name EQC_POWER_UP_COMPARE Off
-set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
-set_global_assignment -name EQC_AUTO_INVERSION On
-set_global_assignment -name EQC_AUTO_TERMINATE On
-set_global_assignment -name EQC_SUB_CONE_REPORT Off
-set_global_assignment -name EQC_RENAMING_RULES On
-set_global_assignment -name EQC_PARAMETER_CHECK On
-set_global_assignment -name EQC_AUTO_PORTSWAP On
-set_global_assignment -name EQC_DETECT_DONT_CARES On
-set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
-set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
-set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
-set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
-set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
-set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
-set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
-set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
-set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
-set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
-set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
-set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
-set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
-set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
-set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
-set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
-set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
-set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
-set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
-set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
-set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
-set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
-set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
-set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
-set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
-set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
-set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
-set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
-set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
View
132 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.jdi
@@ -1,132 +0,0 @@
-<sld_project_info>
- <hub_info ir_width="8" node_count="2"/>
- <node_info>
- <node hpath="ddr3_x16_example_if0:if0|ddr3_x16_example_if0_p0:p0|ddr3_x16_example_if0_p0_controller_phy:controller_phy_inst|ddr3_x16_example_if0_p0_memphy_top:memphy_top_inst|ddr3_x16_example_if0_p0_memphy:umemphy|ddr3_x16_example_if0_p0_nios_sequencer:usequencer|ddr3_x16_example_if0_p0_qsys_sequencer:sequencer_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst:cpu_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|sld_virtual_jtag_basic:ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" instance_id="0" mfg_id="110" node_id="135" sld_node_info="0x1C386E00" version="3">
- <parameters>
- <parameter name="sld_mfg_id" type="dec" value="110"/>
- <parameter name="sld_type_id" type="dec" value="135"/>
- <parameter name="sld_version" type="dec" value="3"/>
- <parameter name="sld_instance_index" type="dec" value="0"/>
- <parameter name="sld_auto_instance_index" type="string" value="YES"/>
- <parameter name="sld_ir_width" type="dec" value="2"/>
- <parameter name="SLD_NODE_INFO" type="dec" value="473460224"/>
- </parameters>
- <inputs>
- <port name="usr_tdo" source="ddr3_x16_example_if0:if0|ddr3_x16_example_if0_p0:p0|ddr3_x16_example_if0_p0_controller_phy:controller_phy_inst|ddr3_x16_example_if0_p0_memphy_top:memphy_top_inst|ddr3_x16_example_if0_p0_memphy:umemphy|ddr3_x16_example_if0_p0_nios_sequencer:usequencer|ddr3_x16_example_if0_p0_qsys_sequencer:sequencer_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst:cpu_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|sld_virtual_jtag_basic:ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy|tdo"/>
- <port name="usr_ir_out[0]" source="ddr3_x16_example_if0:if0|ddr3_x16_example_if0_p0:p0|ddr3_x16_example_if0_p0_controller_phy:controller_phy_inst|ddr3_x16_example_if0_p0_memphy_top:memphy_top_inst|ddr3_x16_example_if0_p0_memphy:umemphy|ddr3_x16_example_if0_p0_nios_sequencer:usequencer|ddr3_x16_example_if0_p0_qsys_sequencer:sequencer_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst:cpu_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|sld_virtual_jtag_basic:ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy|ir_out[0]"/>
- <port name="usr_ir_out[1]" source="ddr3_x16_example_if0:if0|ddr3_x16_example_if0_p0:p0|ddr3_x16_example_if0_p0_controller_phy:controller_phy_inst|ddr3_x16_example_if0_p0_memphy_top:memphy_top_inst|ddr3_x16_example_if0_p0_memphy:umemphy|ddr3_x16_example_if0_p0_nios_sequencer:usequencer|ddr3_x16_example_if0_p0_qsys_sequencer:sequencer_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst:cpu_inst|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci|ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|sld_virtual_jtag_basic:ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy|ir_out[1]"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_raw_tck" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_raw_tck"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_raw_tms" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_raw_tms"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_tdi" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_tdi"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_tlr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_tlr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_rti" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_rti"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sdrs" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sdrs"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_cdr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_cdr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sdr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sdr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e1dr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e1dr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_pdr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_pdr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e2dr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e2dr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_udr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_udr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sirs" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sirs"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_cir" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_cir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sir" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_sir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e1ir" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e1ir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_pir" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_pir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e2ir" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_e2ir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_uir" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_jtag_state_uir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_usr1" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_usr1"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_clr" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_clr"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ena" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ena"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_in_0_" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_in_0_"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_in_1_" source="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_in_1_"/>
- </inputs>
- <outputs>
- <port name="usr_tck"/>
- <port name="usr_tdi"/>
- <port name="usr_ir_in[0]"/>
- <port name="usr_ir_in[1]"/>
- <port name="usr_virtual_state_cdr"/>
- <port name="usr_virtual_state_sdr"/>
- <port name="usr_virtual_state_e1dr"/>
- <port name="usr_virtual_state_pdr"/>
- <port name="usr_virtual_state_e2dr"/>
- <port name="usr_virtual_state_udr"/>
- <port name="usr_virtual_state_cir"/>
- <port name="usr_virtual_state_uir"/>
- <port name="usr_tms"/>
- <port name="usr_jtag_state_tlr"/>
- <port name="usr_jtag_state_rti"/>
- <port name="usr_jtag_state_sdrs"/>
- <port name="usr_jtag_state_cdr"/>
- <port name="usr_jtag_state_sdr"/>
- <port name="usr_jtag_state_e1dr"/>
- <port name="usr_jtag_state_pdr"/>
- <port name="usr_jtag_state_e2dr"/>
- <port name="usr_jtag_state_udr"/>
- <port name="usr_jtag_state_sirs"/>
- <port name="usr_jtag_state_cir"/>
- <port name="usr_jtag_state_sir"/>
- <port name="usr_jtag_state_e1ir"/>
- <port name="usr_jtag_state_pir"/>
- <port name="usr_jtag_state_e2ir"/>
- <port name="usr_jtag_state_uir"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_tdo"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_out_0_"/>
- <port name="jtag.bp.if0_p0_controller_phy_inst_memphy_top_inst_umemphy_usequencer_sequencer_inst_cpu_inst_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_the_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper_ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy_sld_virtual_jtag_impl_inst_ir_out_1_"/>
- </outputs>
- </node>
- <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
- <parameters>
- <parameter name="lpm_type" type="string" value="sld_signaltap"/>
- <parameter name="sld_node_info" type="unknown" value="805334528"/>
- <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
- <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
- <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
- <parameter name="sld_data_bits" type="unknown" value="6"/>
- <parameter name="sld_trigger_bits" type="unknown" value="6"/>
- <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
- <parameter name="sld_node_crc_hiword" type="unknown" value="60158"/>
- <parameter name="sld_node_crc_loword" type="unknown" value="41962"/>
- <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
- <parameter name="sld_sample_depth" type="unknown" value="512"/>
- <parameter name="sld_segment_size" type="unknown" value="512"/>
- <parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
- <parameter name="sld_state_bits" type="unknown" value="11"/>
- <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
- <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
- <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
- <parameter name="sld_trigger_level" type="unknown" value="1"/>
- <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
- <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
- <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
- <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
- <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
- <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
- <parameter name="sld_inversion_mask_length" type="unknown" value="41"/>
- <parameter name="sld_inversion_mask" type="unknown" value="00000000000000000000000000000000000000000"/>
- <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
- <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
- <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
- <parameter name="sld_current_resource_width" type="unknown" value="1"/>
- <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
- <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
- <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
- <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
- <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
- <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
- <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
- <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
- </parameters>
- <inputs/>
- <outputs/>
- </node>
- </node_info>
-</sld_project_info>
View
172 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.qip
@@ -1,172 +0,0 @@
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/ddr3_x16_example.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_c0.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_addr_cmd.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_addr_cmd_wrap.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ddr2_odt_gen.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ddr3_odt_gen.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_odt_gen.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_rdwr_data_tmg.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_arbiter.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_burst_gen.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_cmd_gen.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_csr.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_buffer.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_buffer_manager.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_burst_tracking.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_dataid_manager.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_fifo.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_list.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_rdata_path.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_wdata_path.v] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_define.iv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_decoder.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_input_if.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_rank_timer.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_sideband.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_tbp.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_timing_param.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_controller.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_controller_st_top.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/alt_mem_ddrx_mm_st_converter.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_clock_pair_generator.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_pll_memphy.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_dll_memphy.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_oct_control.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_controller_phy.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_memphy_top.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_read_valid_selector.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_addr_cmd_datapath.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_reset.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_addr_cmd_pads.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_memphy.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_reset_sync.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_afi_mux.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_new_io_pads.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_fr_cycle_shifter.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_read_datapath.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_write_datapath.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_hr_to_fr.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_sequencer_mux_bridge.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_phy_csr.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_iss_probe.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_flop_mem.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_nios_sequencer.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_altdqdqs.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altdq_dqs2_ddio_3reg_stratixiv.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/software/sequencer.c] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/software/sequencer.h] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_avalon_sc_fifo.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_avalon_st_pipeline_base.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_arbitrator.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_burst_uncompressor.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_master_agent.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_master_translator.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_slave_agent.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_slave_translator.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_merlin_traffic_limiter.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_reset_controller.sdc] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_reset_controller.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/altera_reset_synchronizer.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_addr_router.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_addr_router_001.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cmd_xbar_demux.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cmd_xbar_demux_001.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cmd_xbar_mux.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst.sdc] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper.v] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench.v] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_rf_ram_a.mif] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_rf_ram_b.mif] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_cpu_inst_test_bench.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_id_router.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_id_router_002.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_irq_mapper.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_rsp_xbar_demux.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_rsp_xbar_demux_002.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_rsp_xbar_mux.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_rsp_xbar_mux_001.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_sequencer_ram.v] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_sequencer_rom.hex] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_qsys_sequencer_sequencer_rom.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_ac_ROM_no_ifdef_params.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_ac_ROM_reg.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_bitcheck.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_core.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_datamux.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_data_broadcast.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_data_decoder.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_ddr3.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_di_buffer.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_di_buffer_wrap.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_dm_decoder.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_generic.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_inst_ROM_no_ifdef_params.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_inst_ROM_reg.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_jumplogic.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_lfsr12.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_lfsr36.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_lfsr72.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_pattern_fifo.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_ram.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_ram_csr.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_read_datapath.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rw_manager_write_decoder.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_data_mgr.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_phy_mgr.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_ptr_mgr.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_scc_mgr.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_scc_reg_file.v] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_scc_siii_phase_decode.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_scc_siii_wrapper.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_scc_sv_phase_decode.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/sequencer_scc_sv_wrapper.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_sequencer_rom.hex] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_AC_ROM.hex] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_inst_ROM.hex] -library lib_ddr3_x16_example
-set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0.ppf] -library lib_ddr3_x16_example
-set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0.sdc] -library lib_ddr3_x16_example
-set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_timing.tcl] -library lib_ddr3_x16_example
-set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_report_timing.tcl] -library lib_ddr3_x16_example
-set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_report_timing_core.tcl] -library lib_ddr3_x16_example
-set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_pin_map.tcl] -library lib_ddr3_x16_example
-set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_pin_assignments.tcl] -library lib_ddr3_x16_example
-set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_parameters.tcl] -library lib_ddr3_x16_example
-set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_if0_p0_sequencer_cpu.sdc] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/ddr3_x16_example_d0.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/driver_definitions.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/addr_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/burst_boundary_addr_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/lfsr.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/lfsr_wrapper.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rand_addr_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rand_burstcount_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rand_num_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/rand_seq_addr_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/reset_sync.v] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/scfifo_wrapper.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/seq_addr_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/template_addr_gen.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/template_stage.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/avalon_traffic_gen_avl_use_be_avl_use_burstbegin.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/block_rw_stage_avl_use_be_avl_use_burstbegin.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/driver_avl_use_be_avl_use_burstbegin.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/driver_fsm_avl_use_be_avl_use_burstbegin.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/read_compare_avl_use_be_avl_use_burstbegin.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr3_x16_example/submodules/single_rw_stage_avl_use_be_avl_use_burstbegin.sv] -library lib_ddr3_x16_example
-set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID ipds
-
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30 scripts/altera/tom20110927/ddr3_x16_example_restored/ddr3_x16_example.qpf
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2011 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
-# Date created = 09:41:43 September 27, 2011
-#
-# -------------------------------------------------------------------------- #