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add in TB19

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ShepardSiegel committed Oct 12, 2012
1 parent 6b075e1 commit 579ce6e750e3925c615b5f8f1638fb4267f06518
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@@ -10,6 +10,7 @@ BTEST15 ?= TB15
BTEST16 ?= TB16
BTEST17 ?= TB17
BTEST18 ?= TB18
+BTEST19 ?= TB19
BTEST_WMEMI ?= WmemiTB
ITEST ?= TB2
ITEST1 ?= TB1
@@ -23,6 +24,7 @@ ITEST15 ?= TB15
ITEST16 ?= TB16
ITEST17 ?= TB17
ITEST18 ?= TB18
+ITEST19 ?= TB19
OPED ?= OPED
A4LS ?= A4LS
NFT ?= TB_nft
@@ -274,6 +276,27 @@ bsim18: $(OBJ)
# run bluesim executable
$(OBJ)/mk$(BTEST18).bexe -V
+######################################################################
+bsim19: $(OBJ)
+
+ # compile to bluesim backend
+ bsc -u -sim -elab -keep-inlined-boundaries -no-warn-action-shadowing \
+ -aggressive-conditions \
+ -keep-fires \
+ -vdir $(RTL) -bdir $(OBJ) -simdir $(OBJ) \
+ -p $(BSVDIRS):lib:+ \
+ -D DEFINE_NDW=1 \
+ -D USE_NDW1 \
+ $(BSVTST)/$(BTEST19).bsv
+
+ # create bluesim executable
+ bsc -sim -keep-inlined-boundaries -keep-fires \
+ -vdir $(RTL) -bdir $(OBJ) -simdir $(OBJ) \
+ -o $(OBJ)/mk$(BTEST19).bexe -e mk$(BTEST19) $(OBJ)/*.ba
+
+ # run bluesim executable
+ $(OBJ)/mk$(BTEST19).bexe -V
+
######################################################################
bsim_wmemi: $(OBJ)
@@ -539,6 +562,24 @@ isim18: $(OBJ)
#@# test to be sure the word "PASSED" is in the log file
#@ if !(grep -c PASSED $(OBJ)/mk$(ITEST).runlog) then exit 2; fi
+######################################################################
+isim19: $(OBJ)
+
+ # compile to verilog backend for ISim
+ #echo Bit#\(32\) compileTime = `date +%s`\; // ISim `date` > bsv/utl/CompileTime.bsv
+ bsc -u -verilog -elab \
+ -keep-inlined-boundaries -no-warn-action-shadowing \
+ -aggressive-conditions -no-show-method-conf \
+ -vdir $(RTL) -bdir $(OBJ) -simdir $(OBJ) \
+ -p $(BSVDIRS):lib:+ \
+ -D DEFINE_NDW=1 \
+ -D USE_NDW1 \
+ $(BSVTST)/$(ITEST19).bsv
+
+ bsc -vsim isim -D BSV_TIMESCALE=1ns/1ps -vdir $(RTL) -bdir $(OBJ) -vsearch $(VLG_HDL):+ -e mk$(ITEST19) -o runsim
+ # uncomment next line to run
+ #./runsim -testplusarg bscvcd
+
######################################################################
vls18: $(OBJ)
View
@@ -92,7 +92,7 @@ module mkCTop#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (CTopIfc#(ndw))
// for (Integer i=0; i<iNwti_app; i=i+1) mkConnection(wtiM[i].mas, app.wti_s[i]);
// We can't quite use these functions as is as per 2012-01-12 dialog with Joe Stoy
- // zipWithM(mkConnection, wtiM.mas, app.wti_s); // mkConnection zipped over argumernts
+ // zipWithM(mkConnection, wtiM.mas, app.wti_s); // mkConnection zipped over arguments
// mkConnection(wtiM.mas, app.wti_s); // mkConnection understands Vectors of Connectable
// So we write a functon to select the desired subinterface of the master...
View
@@ -0,0 +1,47 @@
+// TB19.bsv - A testbench for a OpenCPI that uses a DCP byte stream - TB18 adapted to use OCApp
+// Copyright (c) 2009-2012 Atomic Rules LLC - ALL RIGHTS RESERVED
+
+import Config ::*;
+import OCApp ::*;
+import OCWip ::*;
+import OCCP ::*;
+import SimDCP ::*;
+import SimIO ::*;
+
+import ClientServer ::*;
+import Connectable ::*;
+import FIFO ::*;
+import GetPut ::*;
+import Vector ::*;
+import Real ::*;
+
+(* synthesize *)
+module mkTB19(Empty);
+
+ Clock sys1_clk <- exposeCurrentClock;
+ Reset sys1_rst <- exposeCurrentReset;
+
+ Reg#(Bit#(16)) simCycle <- mkReg(0); // simulation cycle counter
+ SimIOIfc simIO <- mkSimIO; // simulator file IO
+ SimDCPIfc simDCP <- mkSimDCP; // decode DCP to control plane
+ OCCPIfc#(Nwcit) cp <- mkOCCP(
+ ?, // pciDevice (not used)
+ sys1_clk, // time_clk timebase
+ sys1_rst, // time_rst reset
+ clocked_by sys1_clk, reset_by sys1_rst);
+
+ mkConnection(simIO.host,simDCP.host); // Connect simIO to simDCP
+ mkConnection(simDCP.client,cp.server); // Connect simDCP to Control Plane
+
+ Vector#(Nwcit, WciEM) vWci = cp.wci_Vm; // Vector of WciEM Interfaces
+ Vector#(iNwci_ctop, Reset) resetVec = newVector; // Vector of WCI Resets
+ for (Integer i=0; i<iNwci_app; i=i+1) resetVec[i] = vWci[i].mReset_n; // Reset Vector for the Application
+ OCApp4BIfc app <- mkOCApp4B(resetVec,True); // Instance the Application
+ for (Integer i=0; i<iNwci_app; i=i+1) mkConnection(vWci[i], app.wci_s[i]); // Connect WCI between INF/APP
+
+ // Simulation Control...
+ rule increment_simCycle;
+ simCycle <= simCycle + 1;
+ endrule
+
+endmodule: mkTB19
View
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:34 EDT 2012
+// On Fri Oct 12 14:07:53 EDT 2012
//
//
// Ports:
@@ -543,7 +543,8 @@ module mkBiasWorker16B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
@@ -742,6 +743,8 @@ module mkBiasWorker16B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -767,7 +770,7 @@ module mkBiasWorker16B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -959,11 +962,11 @@ module mkBiasWorker16B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:35 EDT 2012
+// On Fri Oct 12 14:07:54 EDT 2012
//
//
// Ports:
@@ -543,7 +543,8 @@ module mkBiasWorker32B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
@@ -742,6 +743,8 @@ module mkBiasWorker32B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -767,7 +770,7 @@ module mkBiasWorker32B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -959,11 +962,11 @@ module mkBiasWorker32B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:32 EDT 2012
+// On Fri Oct 12 14:07:51 EDT 2012
//
//
// Ports:
@@ -542,7 +542,8 @@ module mkBiasWorker4B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
@@ -741,6 +742,8 @@ module mkBiasWorker4B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -766,7 +769,7 @@ module mkBiasWorker4B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -958,11 +961,11 @@ module mkBiasWorker4B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:33 EDT 2012
+// On Fri Oct 12 14:07:52 EDT 2012
//
//
// Ports:
@@ -541,7 +541,8 @@ module mkBiasWorker8B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
@@ -740,6 +741,8 @@ module mkBiasWorker8B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -765,7 +768,7 @@ module mkBiasWorker8B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -957,11 +960,11 @@ module mkBiasWorker8B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
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