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add in TB19

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commit 579ce6e750e3925c615b5f8f1638fb4267f06518 1 parent 6b075e1
@ShepardSiegel authored
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41 Makefile
@@ -10,6 +10,7 @@ BTEST15 ?= TB15
BTEST16 ?= TB16
BTEST17 ?= TB17
BTEST18 ?= TB18
+BTEST19 ?= TB19
BTEST_WMEMI ?= WmemiTB
ITEST ?= TB2
ITEST1 ?= TB1
@@ -23,6 +24,7 @@ ITEST15 ?= TB15
ITEST16 ?= TB16
ITEST17 ?= TB17
ITEST18 ?= TB18
+ITEST19 ?= TB19
OPED ?= OPED
A4LS ?= A4LS
NFT ?= TB_nft
@@ -275,6 +277,27 @@ bsim18: $(OBJ)
$(OBJ)/mk$(BTEST18).bexe -V
######################################################################
+bsim19: $(OBJ)
+
+ # compile to bluesim backend
+ bsc -u -sim -elab -keep-inlined-boundaries -no-warn-action-shadowing \
+ -aggressive-conditions \
+ -keep-fires \
+ -vdir $(RTL) -bdir $(OBJ) -simdir $(OBJ) \
+ -p $(BSVDIRS):lib:+ \
+ -D DEFINE_NDW=1 \
+ -D USE_NDW1 \
+ $(BSVTST)/$(BTEST19).bsv
+
+ # create bluesim executable
+ bsc -sim -keep-inlined-boundaries -keep-fires \
+ -vdir $(RTL) -bdir $(OBJ) -simdir $(OBJ) \
+ -o $(OBJ)/mk$(BTEST19).bexe -e mk$(BTEST19) $(OBJ)/*.ba
+
+ # run bluesim executable
+ $(OBJ)/mk$(BTEST19).bexe -V
+
+######################################################################
bsim_wmemi: $(OBJ)
# compile to bluesim backend
@@ -540,6 +563,24 @@ isim18: $(OBJ)
#@ if !(grep -c PASSED $(OBJ)/mk$(ITEST).runlog) then exit 2; fi
######################################################################
+isim19: $(OBJ)
+
+ # compile to verilog backend for ISim
+ #echo Bit#\(32\) compileTime = `date +%s`\; // ISim `date` > bsv/utl/CompileTime.bsv
+ bsc -u -verilog -elab \
+ -keep-inlined-boundaries -no-warn-action-shadowing \
+ -aggressive-conditions -no-show-method-conf \
+ -vdir $(RTL) -bdir $(OBJ) -simdir $(OBJ) \
+ -p $(BSVDIRS):lib:+ \
+ -D DEFINE_NDW=1 \
+ -D USE_NDW1 \
+ $(BSVTST)/$(ITEST19).bsv
+
+ bsc -vsim isim -D BSV_TIMESCALE=1ns/1ps -vdir $(RTL) -bdir $(OBJ) -vsearch $(VLG_HDL):+ -e mk$(ITEST19) -o runsim
+ # uncomment next line to run
+ #./runsim -testplusarg bscvcd
+
+######################################################################
vls18: $(OBJ)
# compile to verilog backend for ISim
View
2  bsv/inf/CTop.bsv
@@ -92,7 +92,7 @@ module mkCTop#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (CTopIfc#(ndw))
// for (Integer i=0; i<iNwti_app; i=i+1) mkConnection(wtiM[i].mas, app.wti_s[i]);
// We can't quite use these functions as is as per 2012-01-12 dialog with Joe Stoy
- // zipWithM(mkConnection, wtiM.mas, app.wti_s); // mkConnection zipped over argumernts
+ // zipWithM(mkConnection, wtiM.mas, app.wti_s); // mkConnection zipped over arguments
// mkConnection(wtiM.mas, app.wti_s); // mkConnection understands Vectors of Connectable
// So we write a functon to select the desired subinterface of the master...
View
47 bsv/tst/TB19.bsv
@@ -0,0 +1,47 @@
+// TB19.bsv - A testbench for a OpenCPI that uses a DCP byte stream - TB18 adapted to use OCApp
+// Copyright (c) 2009-2012 Atomic Rules LLC - ALL RIGHTS RESERVED
+
+import Config ::*;
+import OCApp ::*;
+import OCWip ::*;
+import OCCP ::*;
+import SimDCP ::*;
+import SimIO ::*;
+
+import ClientServer ::*;
+import Connectable ::*;
+import FIFO ::*;
+import GetPut ::*;
+import Vector ::*;
+import Real ::*;
+
+(* synthesize *)
+module mkTB19(Empty);
+
+ Clock sys1_clk <- exposeCurrentClock;
+ Reset sys1_rst <- exposeCurrentReset;
+
+ Reg#(Bit#(16)) simCycle <- mkReg(0); // simulation cycle counter
+ SimIOIfc simIO <- mkSimIO; // simulator file IO
+ SimDCPIfc simDCP <- mkSimDCP; // decode DCP to control plane
+ OCCPIfc#(Nwcit) cp <- mkOCCP(
+ ?, // pciDevice (not used)
+ sys1_clk, // time_clk timebase
+ sys1_rst, // time_rst reset
+ clocked_by sys1_clk, reset_by sys1_rst);
+
+ mkConnection(simIO.host,simDCP.host); // Connect simIO to simDCP
+ mkConnection(simDCP.client,cp.server); // Connect simDCP to Control Plane
+
+ Vector#(Nwcit, WciEM) vWci = cp.wci_Vm; // Vector of WciEM Interfaces
+ Vector#(iNwci_ctop, Reset) resetVec = newVector; // Vector of WCI Resets
+ for (Integer i=0; i<iNwci_app; i=i+1) resetVec[i] = vWci[i].mReset_n; // Reset Vector for the Application
+ OCApp4BIfc app <- mkOCApp4B(resetVec,True); // Instance the Application
+ for (Integer i=0; i<iNwci_app; i=i+1) mkConnection(vWci[i], app.wci_s[i]); // Connect WCI between INF/APP
+
+ // Simulation Control...
+ rule increment_simCycle;
+ simCycle <= simCycle + 1;
+ endrule
+
+endmodule: mkTB19
View
17 rtl/mkBiasWorker16B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:34 EDT 2012
+// On Fri Oct 12 14:07:53 EDT 2012
//
//
// Ports:
@@ -543,7 +543,8 @@ module mkBiasWorker16B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
@@ -742,6 +743,8 @@ module mkBiasWorker16B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -767,7 +770,7 @@ module mkBiasWorker16B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -959,11 +962,11 @@ module mkBiasWorker16B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
17 rtl/mkBiasWorker32B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:35 EDT 2012
+// On Fri Oct 12 14:07:54 EDT 2012
//
//
// Ports:
@@ -543,7 +543,8 @@ module mkBiasWorker32B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
@@ -742,6 +743,8 @@ module mkBiasWorker32B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -767,7 +770,7 @@ module mkBiasWorker32B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -959,11 +962,11 @@ module mkBiasWorker32B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
17 rtl/mkBiasWorker4B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:32 EDT 2012
+// On Fri Oct 12 14:07:51 EDT 2012
//
//
// Ports:
@@ -542,7 +542,8 @@ module mkBiasWorker4B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
@@ -741,6 +742,8 @@ module mkBiasWorker4B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -766,7 +769,7 @@ module mkBiasWorker4B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -958,11 +961,11 @@ module mkBiasWorker4B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
17 rtl/mkBiasWorker8B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:33 EDT 2012
+// On Fri Oct 12 14:07:52 EDT 2012
//
//
// Ports:
@@ -541,7 +541,8 @@ module mkBiasWorker8B(wciS0_Clk,
MUX_biasValue$write_1__SEL_2,
MUX_controlReg$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
- MUX_wci_wslv_illegalEdge$write_1__VAL_1,
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2,
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
@@ -740,6 +741,8 @@ module mkBiasWorker8B(wciS0_Clk,
assign MUX_controlReg$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
@@ -765,7 +768,7 @@ module mkBiasWorker8B(wciS0_Clk,
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 ;
- assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
+ assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
@@ -957,11 +960,11 @@ module mkBiasWorker8B(wciS0_Clk,
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
- MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
+ !MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
+ MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
- MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
- WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
+ WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
+ MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
View
50 rtl/mkMemiTestWorker.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Sat Sep 29 14:29:49 EDT 2012
+// On Fri Oct 12 14:07:56 EDT 2012
//
//
// Ports:
@@ -513,7 +513,7 @@ module mkMemiTestWorker(wciS0_Clk,
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
wire [145 : 0] MUX_wmemi_dhF_q_0$write_1__VAL_1,
MUX_wmemi_dhF_q_0$write_1__VAL_2,
- MUX_wmemi_dhF_q_1$write_1__VAL_1;
+ MUX_wmemi_dhF_q_1$write_1__VAL_2;
wire [51 : 0] MUX_wmemi_reqF_q_0$write_1__VAL_1,
MUX_wmemi_reqF_q_0$write_1__VAL_2,
MUX_wmemi_reqF_q_1$write_1__VAL_1,
@@ -538,8 +538,8 @@ module mkMemiTestWorker(wciS0_Clk,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
- MUX_wmemi_dhF_q_0$write_1__SEL_2,
- MUX_wmemi_dhF_q_1$write_1__SEL_2,
+ MUX_wmemi_dhF_q_0$write_1__SEL_1,
+ MUX_wmemi_dhF_q_1$write_1__SEL_1,
MUX_wmemi_reqF_q_0$write_1__SEL_2,
MUX_wmemi_reqF_q_1$write_1__SEL_2;
@@ -798,9 +798,9 @@ module mkMemiTestWorker(wciS0_Clk,
assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
- assign MUX_wmemi_dhF_q_0$write_1__SEL_2 =
+ assign MUX_wmemi_dhF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ;
- assign MUX_wmemi_dhF_q_1$write_1__SEL_2 =
+ assign MUX_wmemi_dhF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ;
assign MUX_wmemi_reqF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ;
@@ -846,14 +846,14 @@ module mkMemiTestWorker(wciS0_Clk,
assign MUX_wmemi_dhF_c_r$write_1__VAL_1 = wmemi_dhF_c_r + 2'd1 ;
assign MUX_wmemi_dhF_c_r$write_1__VAL_2 = wmemi_dhF_c_r - 2'd1 ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_1 =
+ { 2'd3, wgen_gsF$D_OUT, 16'd65535 } ;
+ assign MUX_wmemi_dhF_q_0$write_1__VAL_2 =
(wmemi_dhF_c_r == 2'd1) ?
- MUX_wmemi_dhF_q_0$write_1__VAL_2 :
+ MUX_wmemi_dhF_q_0$write_1__VAL_1 :
wmemi_dhF_q_1 ;
- assign MUX_wmemi_dhF_q_0$write_1__VAL_2 =
- { 2'd3, wgen_gsF$D_OUT, 16'd65535 } ;
- assign MUX_wmemi_dhF_q_1$write_1__VAL_1 =
+ assign MUX_wmemi_dhF_q_1$write_1__VAL_2 =
(wmemi_dhF_c_r == 2'd2) ?
- MUX_wmemi_dhF_q_0$write_1__VAL_2 :
+ MUX_wmemi_dhF_q_0$write_1__VAL_1 :
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_1 = wmemi_reqF_c_r + 2'd1 ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_2 = wmemi_reqF_c_r - 2'd1 ;
@@ -905,7 +905,7 @@ module mkMemiTestWorker(wciS0_Clk,
assign wmemi_reqF_x_wire$wget = MUX_wmemi_reqF_q_0$write_1__VAL_2 ;
assign wmemi_reqF_x_wire$whas =
WILL_FIRE_RL_write_req || WILL_FIRE_RL_read_req ;
- assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_2 ;
+ assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_1 ;
assign wmemi_dhF_x_wire$whas = WILL_FIRE_RL_write_req ;
assign wmemi_wmemiResponse$wget =
{ wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ;
@@ -1198,16 +1198,16 @@ module mkMemiTestWorker(wciS0_Clk,
WILL_FIRE_RL_wmemi_dhF_incCtr || WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_0
- always@(WILL_FIRE_RL_wmemi_dhF_both or
+ always@(MUX_wmemi_dhF_q_0$write_1__SEL_1 or
MUX_wmemi_dhF_q_0$write_1__VAL_1 or
- MUX_wmemi_dhF_q_0$write_1__SEL_2 or
+ WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
- WILL_FIRE_RL_wmemi_dhF_both:
+ MUX_wmemi_dhF_q_0$write_1__SEL_1:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1;
- MUX_wmemi_dhF_q_0$write_1__SEL_2:
+ WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_0$D_IN = wmemi_dhF_q_1;
default: wmemi_dhF_q_0$D_IN =
@@ -1215,21 +1215,21 @@ module mkMemiTestWorker(wciS0_Clk,
endcase
end
assign wmemi_dhF_q_0$EN =
- WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ||
+ WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_1
- always@(WILL_FIRE_RL_wmemi_dhF_both or
- MUX_wmemi_dhF_q_1$write_1__VAL_1 or
- MUX_wmemi_dhF_q_1$write_1__SEL_2 or
- MUX_wmemi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr)
+ always@(MUX_wmemi_dhF_q_1$write_1__SEL_1 or
+ MUX_wmemi_dhF_q_0$write_1__VAL_1 or
+ WILL_FIRE_RL_wmemi_dhF_both or
+ MUX_wmemi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
+ MUX_wmemi_dhF_q_1$write_1__SEL_1:
+ wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wmemi_dhF_both:
- wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_1;
- MUX_wmemi_dhF_q_1$write_1__SEL_2:
- wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
+ wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr:
wmemi_dhF_q_1$D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: wmemi_dhF_q_1$D_IN =
@@ -1237,8 +1237,8 @@ module mkMemiTestWorker(wciS0_Clk,
endcase
end
assign wmemi_dhF_q_1$EN =
- WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ||
+ WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_errorSticky
View
4 rtl/mkOCApp4B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Sat Sep 29 14:30:08 EDT 2012
+// On Fri Oct 12 14:37:43 EDT 2012
//
//
// Ports:
@@ -87,7 +87,7 @@
// wsi_m_dac_MByteEn O 4 reg
// wsi_m_dac_MReqInfo O 8
// wsi_m_dac_MReset_n O 1
-// uuid O 512 const
+// uuid O 512
// RST_N_rst_0 I 1 unused
// RST_N_rst_1 I 1 reset
// RST_N_rst_2 I 1 reset
View
6,620 rtl/mkOCCP.v
3,272 additions, 3,348 deletions not shown
View
155 rtl/mkPktFork.v
@@ -1,20 +1,20 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:32:25 EDT 2012
+// On Fri Oct 12 14:37:47 EDT 2012
//
//
// Ports:
// Name I/O size props
-// RDY_iport_put O 1
-// oport0_get O 153
-// RDY_oport0_get O 1
-// oport1_get O 153
-// RDY_oport1_get O 1
+// RDY_iport_put O 1 reg
+// oport0_get O 153 reg
+// RDY_oport0_get O 1 reg
+// oport1_get O 153 reg
+// RDY_oport1_get O 1 reg
// pfk I 14
// CLK I 1 clock
// RST_N I 1 reset
-// iport_put I 153
+// iport_put I 153 reg
// EN_iport_put I 1
// EN_oport0_get I 1
// EN_oport1_get I 1
@@ -103,12 +103,12 @@ module mkPktFork(pfk,
wire MUX_f0Active$write_1__SEL_1, MUX_f1Active$write_1__SEL_1;
// remaining internal signals
- reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69;
- wire [6 : 0] y__h617, y__h842;
- wire IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33,
- IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42,
- fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47,
- fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66;
+ reg IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59;
+ wire [6 : 0] y__h729, y__h954;
+ wire IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d31,
+ IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d40,
+ fi_first_BITS_63_TO_56_3_EQ_pfk_BITS_7_TO_0_4___d55,
+ fi_i_notEmpty_AND_IF_IF_pfk_BITS_13_TO_12_3_EQ_ETC___d45;
// action method iport_put
assign RDY_iport_put = fi$FULL_N ;
@@ -122,67 +122,66 @@ module mkPktFork(pfk,
assign RDY_oport1_get = fo1$EMPTY_N ;
// submodule fi
- arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi(.CLK(CLK),
- .RST_N(RST_N),
- .D_IN(fi$D_IN),
- .CLR(fi$CLR),
- .DEQ(fi$DEQ),
- .ENQ(fi$ENQ),
- .D_OUT(fi$D_OUT),
- .EMPTY_N(fi$EMPTY_N),
- .FULL_N(fi$FULL_N));
+ FIFO2 #(.width(32'd153), .guarded(32'd1)) fi(.RST(RST_N),
+ .CLK(CLK),
+ .D_IN(fi$D_IN),
+ .ENQ(fi$ENQ),
+ .DEQ(fi$DEQ),
+ .CLR(fi$CLR),
+ .D_OUT(fi$D_OUT),
+ .FULL_N(fi$FULL_N),
+ .EMPTY_N(fi$EMPTY_N));
// submodule fo0
- arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo0(.CLK(CLK),
- .RST_N(RST_N),
- .D_IN(fo0$D_IN),
- .CLR(fo0$CLR),
- .DEQ(fo0$DEQ),
- .ENQ(fo0$ENQ),
- .D_OUT(fo0$D_OUT),
- .EMPTY_N(fo0$EMPTY_N),
- .FULL_N(fo0$FULL_N));
+ FIFO2 #(.width(32'd153), .guarded(32'd1)) fo0(.RST(RST_N),
+ .CLK(CLK),
+ .D_IN(fo0$D_IN),
+ .ENQ(fo0$ENQ),
+ .DEQ(fo0$DEQ),
+ .CLR(fo0$CLR),
+ .D_OUT(fo0$D_OUT),
+ .FULL_N(fo0$FULL_N),
+ .EMPTY_N(fo0$EMPTY_N));
// submodule fo1
- arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo1(.CLK(CLK),
- .RST_N(RST_N),
- .D_IN(fo1$D_IN),
- .CLR(fo1$CLR),
- .DEQ(fo1$DEQ),
- .ENQ(fo1$ENQ),
- .D_OUT(fo1$D_OUT),
- .EMPTY_N(fo1$EMPTY_N),
- .FULL_N(fo1$FULL_N));
+ FIFO2 #(.width(32'd153), .guarded(32'd1)) fo1(.RST(RST_N),
+ .CLK(CLK),
+ .D_IN(fo1$D_IN),
+ .ENQ(fo1$ENQ),
+ .DEQ(fo1$DEQ),
+ .CLR(fo1$CLR),
+ .D_OUT(fo1$D_OUT),
+ .FULL_N(fo1$FULL_N),
+ .EMPTY_N(fo1$EMPTY_N));
// rule RL_fo0_advance
- assign WILL_FIRE_RL_fo0_advance = fo0$FULL_N && fi$EMPTY_N && f0Active ;
+ assign WILL_FIRE_RL_fo0_advance = fi$EMPTY_N && fo0$FULL_N && f0Active ;
// rule RL_fo1_advance
assign WILL_FIRE_RL_fo1_advance =
- fo1$FULL_N && fi$EMPTY_N && f1Active &&
+ fi$EMPTY_N && fo1$FULL_N && f1Active &&
!WILL_FIRE_RL_fo0_advance ;
// rule RL_select
assign WILL_FIRE_RL_select =
- fi$EMPTY_N &&
- fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47 &&
+ fi_i_notEmpty_AND_IF_IF_pfk_BITS_13_TO_12_3_EQ_ETC___d45 &&
!f0Active &&
!f1Active ;
// inputs to muxes for submodule ports
assign MUX_f0Active$write_1__SEL_1 =
WILL_FIRE_RL_select &&
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ;
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ;
assign MUX_f1Active$write_1__SEL_1 =
WILL_FIRE_RL_select &&
- !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ;
+ !IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ;
// register f0Active
assign f0Active$D_IN =
MUX_f0Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ;
assign f0Active$EN =
WILL_FIRE_RL_select &&
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ||
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ||
WILL_FIRE_RL_fo0_advance ;
// register f1Active
@@ -190,74 +189,74 @@ module mkPktFork(pfk,
MUX_f1Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ;
assign f1Active$EN =
WILL_FIRE_RL_select &&
- !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ||
+ !IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ||
WILL_FIRE_RL_fo1_advance ;
// submodule fi
assign fi$D_IN = iport_put ;
- assign fi$CLR = 1'b0 ;
+ assign fi$ENQ = EN_iport_put ;
assign fi$DEQ =
WILL_FIRE_RL_select || WILL_FIRE_RL_fo1_advance ||
WILL_FIRE_RL_fo0_advance ;
- assign fi$ENQ = EN_iport_put ;
+ assign fi$CLR = 1'b0 ;
// submodule fo0
assign fo0$D_IN = fi$D_OUT ;
- assign fo0$CLR = 1'b0 ;
- assign fo0$DEQ = EN_oport0_get ;
assign fo0$ENQ =
WILL_FIRE_RL_select &&
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ||
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ||
WILL_FIRE_RL_fo0_advance ;
+ assign fo0$DEQ = EN_oport0_get ;
+ assign fo0$CLR = 1'b0 ;
// submodule fo1
assign fo1$D_IN = fi$D_OUT ;
- assign fo1$CLR = 1'b0 ;
- assign fo1$DEQ = EN_oport1_get ;
assign fo1$ENQ =
WILL_FIRE_RL_select &&
- !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ||
+ !IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ||
WILL_FIRE_RL_fo1_advance ;
+ assign fo1$DEQ = EN_oport1_get ;
+ assign fo1$CLR = 1'b0 ;
// remaining internal signals
- assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33 =
+ assign IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d31 =
(fi$D_OUT[124:120] == 5'b01010) ?
fi$D_OUT[50:48] == pfk[2:0] :
- fi$D_OUT[150:144] == y__h842 && pfk[3] == fi$D_OUT[47] ;
- assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42 =
+ fi$D_OUT[150:144] == y__h954 && pfk[3] == fi$D_OUT[47] ;
+ assign IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d40 =
(fi$D_OUT[124:120] == 5'b01010) ?
- fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 :
+ fi_first_BITS_63_TO_56_3_EQ_pfk_BITS_7_TO_0_4___d55 :
pfk[11:8] == fi$D_OUT[60:57] ;
- assign fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47 =
+ assign fi_first_BITS_63_TO_56_3_EQ_pfk_BITS_7_TO_0_4___d55 =
+ fi$D_OUT[63:56] == pfk[7:0] ;
+ assign fi_i_notEmpty_AND_IF_IF_pfk_BITS_13_TO_12_3_EQ_ETC___d45 =
fi$EMPTY_N &&
- (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ?
+ (IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 ?
fo0$FULL_N :
fo1$FULL_N) ;
- assign fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 =
- fi$D_OUT[63:56] == pfk[7:0] ;
- assign y__h617 = 7'd1 << pfk[2:0] ;
- assign y__h842 = 7'd1 << pfk[6:4] ;
+ assign y__h729 = 7'd1 << pfk[2:0] ;
+ assign y__h954 = 7'd1 << pfk[6:4] ;
always@(pfk or
- IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42 or
+ IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d40 or
fi$D_OUT or
- y__h617 or
- fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 or
- IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33)
+ y__h729 or
+ fi_first_BITS_63_TO_56_3_EQ_pfk_BITS_7_TO_0_4___d55 or
+ IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d31)
begin
case (pfk[13:12])
2'd0:
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 =
- fi$D_OUT[150:144] == y__h617;
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 =
+ fi$D_OUT[150:144] == y__h729;
2'd1:
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 =
- fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 &&
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 =
+ fi_first_BITS_63_TO_56_3_EQ_pfk_BITS_7_TO_0_4___d55 &&
fi$D_OUT[124:120] == 5'b01010;
2'd2:
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 =
- IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33;
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 =
+ IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d31;
2'd3:
- IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 =
- IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42;
+ IF_pfk_BITS_13_TO_12_3_EQ_0_4_THEN_fi_first_BI_ETC___d59 =
+ IF_fi_first_BITS_124_TO_120_0_EQ_0b1010_1_THEN_ETC___d40;
endcase
end
View
94 rtl/mkPktMerge.v
@@ -1,19 +1,19 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:32:25 EDT 2012
+// On Fri Oct 12 14:37:47 EDT 2012
//
//
// Ports:
// Name I/O size props
-// RDY_iport0_put O 1
-// RDY_iport1_put O 1
-// oport_get O 153
-// RDY_oport_get O 1
+// RDY_iport0_put O 1 reg
+// RDY_iport1_put O 1 reg
+// oport_get O 153 reg
+// RDY_oport_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
-// iport0_put I 153
-// iport1_put I 153
+// iport0_put I 153 reg
+// iport1_put I 153 reg
// EN_iport0_put I 1
// EN_iport1_put I 1
// EN_oport_get I 1
@@ -109,8 +109,8 @@ module mkPktMerge(CLK,
MUX_fi1Active$write_1__SEL_1;
// remaining internal signals
- reg [63 : 0] v__h900;
- wire fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24;
+ reg [63 : 0] v__h1016;
+ wire fo_i_notFull_AND_IF_fi0HasPrio_8_THEN_fi0_i_no_ETC___d20;
// action method iport0_put
assign RDY_iport0_put = fi0$FULL_N ;
@@ -123,41 +123,41 @@ module mkPktMerge(CLK,
assign RDY_oport_get = fo$EMPTY_N ;
// submodule fi0
- arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi0(.CLK(CLK),
- .RST_N(RST_N),
- .D_IN(fi0$D_IN),
- .CLR(fi0$CLR),
- .DEQ(fi0$DEQ),
- .ENQ(fi0$ENQ),
- .D_OUT(fi0$D_OUT),
- .EMPTY_N(fi0$EMPTY_N),
- .FULL_N(fi0$FULL_N));
+ FIFO2 #(.width(32'd153), .guarded(32'd1)) fi0(.RST(RST_N),
+ .CLK(CLK),
+ .D_IN(fi0$D_IN),
+ .ENQ(fi0$ENQ),
+ .DEQ(fi0$DEQ),
+ .CLR(fi0$CLR),
+ .D_OUT(fi0$D_OUT),
+ .FULL_N(fi0$FULL_N),
+ .EMPTY_N(fi0$EMPTY_N));
// submodule fi1
- arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi1(.CLK(CLK),
- .RST_N(RST_N),
- .D_IN(fi1$D_IN),
- .CLR(fi1$CLR),
- .DEQ(fi1$DEQ),
- .ENQ(fi1$ENQ),
- .D_OUT(fi1$D_OUT),
- .EMPTY_N(fi1$EMPTY_N),
- .FULL_N(fi1$FULL_N));
+ FIFO2 #(.width(32'd153), .guarded(32'd1)) fi1(.RST(RST_N),
+ .CLK(CLK),
+ .D_IN(fi1$D_IN),
+ .ENQ(fi1$ENQ),
+ .DEQ(fi1$DEQ),
+ .CLR(fi1$CLR),
+ .D_OUT(fi1$D_OUT),
+ .FULL_N(fi1$FULL_N),
+ .EMPTY_N(fi1$EMPTY_N));
// submodule fo
- arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo(.CLK(CLK),
- .RST_N(RST_N),
- .D_IN(fo$D_IN),
- .CLR(fo$CLR),
- .DEQ(fo$DEQ),
- .ENQ(fo$ENQ),
- .D_OUT(fo$D_OUT),
- .EMPTY_N(fo$EMPTY_N),
- .FULL_N(fo$FULL_N));
+ FIFO2 #(.width(32'd153), .guarded(32'd1)) fo(.RST(RST_N),
+ .CLK(CLK),
+ .D_IN(fo$D_IN),
+ .ENQ(fo$ENQ),
+ .DEQ(fo$DEQ),
+ .CLR(fo$CLR),
+ .D_OUT(fo$D_OUT),
+ .FULL_N(fo$FULL_N),
+ .EMPTY_N(fo$EMPTY_N));
// rule RL_fi0_advance
assign WILL_FIRE_RL_fi0_advance =
- fo$FULL_N && fi0$EMPTY_N && !fi1Active &&
+ fi0$EMPTY_N && fo$FULL_N && !fi1Active &&
!WILL_FIRE_RL_arbitrate ;
// rule RL_fi1_advance
@@ -168,7 +168,7 @@ module mkPktMerge(CLK,
// rule RL_arbitrate
assign WILL_FIRE_RL_arbitrate =
- fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 &&
+ fo_i_notFull_AND_IF_fi0HasPrio_8_THEN_fi0_i_no_ETC___d20 &&
fi0$EMPTY_N &&
fi1$EMPTY_N &&
!fi0Active &&
@@ -217,19 +217,19 @@ module mkPktMerge(CLK,
// submodule fi0
assign fi0$D_IN = iport0_put ;
- assign fi0$CLR = 1'b0 ;
+ assign fi0$ENQ = EN_iport0_put ;
assign fi0$DEQ =
WILL_FIRE_RL_arbitrate && fi0HasPrio ||
WILL_FIRE_RL_fi0_advance ;
- assign fi0$ENQ = EN_iport0_put ;
+ assign fi0$CLR = 1'b0 ;
// submodule fi1
assign fi1$D_IN = iport1_put ;
- assign fi1$CLR = 1'b0 ;
+ assign fi1$ENQ = EN_iport1_put ;
assign fi1$DEQ =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ||
WILL_FIRE_RL_fi1_advance ;
- assign fi1$ENQ = EN_iport1_put ;
+ assign fi1$CLR = 1'b0 ;
// submodule fo
always@(WILL_FIRE_RL_arbitrate or
@@ -245,14 +245,14 @@ module mkPktMerge(CLK,
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
- assign fo$CLR = 1'b0 ;
- assign fo$DEQ = EN_oport_get ;
assign fo$ENQ =
WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance ||
WILL_FIRE_RL_fi1_advance ;
+ assign fo$DEQ = EN_oport_get ;
+ assign fo$CLR = 1'b0 ;
// remaining internal signals
- assign fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 =
+ assign fo_i_notFull_AND_IF_fi0HasPrio_8_THEN_fi0_i_no_ETC___d20 =
fo$FULL_N && (fi0HasPrio ? fi0$EMPTY_N : fi1$EMPTY_N) ;
// handling of inlined registers
@@ -295,13 +295,13 @@ module mkPktMerge(CLK,
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_arbitrate)
begin
- v__h900 = $time;
+ v__h1016 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_arbitrate)
$display("[%0d]: %m: Merge from:%d Data:%x",
- v__h900,
+ v__h1016,
fi0HasPrio,
fi0HasPrio ? fi0$D_OUT[127:0] : fi1$D_OUT[127:0]);
end
View
117 rtl/mkSMAdapter16B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:44 EDT 2012
+// On Fri Oct 12 14:08:05 EDT 2012
//
//
// Ports:
@@ -921,9 +921,7 @@ module mkSMAdapter16B(wciS0_Clk,
WILL_FIRE_RL_wmi_reqF_decCtr,
WILL_FIRE_RL_wmi_reqF_deq,
WILL_FIRE_RL_wmi_reqF_incCtr,
- WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyRequest,
- WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmrd_mesgResptoWsi,
WILL_FIRE_RL_wmwt_doAbort,
WILL_FIRE_RL_wmwt_mesgBegin,
@@ -943,8 +941,8 @@ module mkSMAdapter16B(wciS0_Clk,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3;
wire [145 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1,
- MUX_wmi_dhF_q_0$write_1__VAL_2,
- MUX_wmi_dhF_q_1$write_1__VAL_1;
+ MUX_wmi_dhF_q_1$write_1__VAL_1,
+ MUX_wmi_dhF_q_1$write_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
@@ -980,6 +978,8 @@ module mkSMAdapter16B(wciS0_Clk,
wire MUX_endOfMessage$write_1__SEL_1,
MUX_mesgCount$write_1__SEL_1,
MUX_mesgReqOK$write_1__SEL_3,
+ MUX_unrollCnt$write_1__SEL_1,
+ MUX_unrollCnt$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
@@ -1009,7 +1009,7 @@ module mkSMAdapter16B(wciS0_Clk,
v__h3904,
v__h4048;
reg [31 : 0] g_data__h24868;
- wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930;
+ wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928;
wire [31 : 0] rdat__h24911,
rdat__h24917,
rdat__h24923,
@@ -1069,7 +1069,7 @@ module mkSMAdapter16B(wciS0_Clk,
y__h23183,
y__h23195,
y__h23207;
- wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918;
+ wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920;
wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524,
wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542,
wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670,
@@ -1281,23 +1281,6 @@ module mkSMAdapter16B(wciS0_Clk,
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
- // rule RL_wmrd_mesgBegin
- assign WILL_FIRE_RL_wmrd_mesgBegin =
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- !wmi_sThreadBusy_d &&
- !wmi_sDataThreadBusy_d &&
- unrollCnt == 16'd0 ;
-
- // rule RL_wmrd_mesgBodyResponse
- assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
- wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 &&
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- unrollCnt != 16'd0 ;
-
// rule RL_wmwt_mesgBegin
assign CAN_FIRE_RL_wmwt_mesgBegin =
wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N &&
@@ -1475,10 +1458,23 @@ module mkSMAdapter16B(wciS0_Clk,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[165] ;
assign MUX_mesgCount$write_1__SEL_1 =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ;
assign MUX_mesgReqOK$write_1__SEL_3 =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ;
+ assign MUX_unrollCnt$write_1__SEL_1 =
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ !wmi_sThreadBusy_d &&
+ !wmi_sDataThreadBusy_d &&
+ unrollCnt == 16'd0 ;
+ assign MUX_unrollCnt$write_1__SEL_2 =
+ wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 &&
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ unrollCnt != 16'd0 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
@@ -1583,12 +1579,12 @@ module mkSMAdapter16B(wciS0_Clk,
assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ;
assign MUX_wmi_dhF_q_0$write_1__VAL_1 =
(wmi_dhF_c_r == 2'd1) ?
- MUX_wmi_dhF_q_0$write_1__VAL_2 :
+ MUX_wmi_dhF_q_1$write_1__VAL_2 :
wmi_dhF_q_1 ;
- assign MUX_wmi_dhF_q_0$write_1__VAL_2 =
- { 1'd1, wsiS_reqFifo$D_OUT[165], wsiS_reqFifo$D_OUT[151:8] } ;
assign MUX_wmi_dhF_q_1$write_1__VAL_1 =
- (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_2 : 146'd0 ;
+ (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_1$write_1__VAL_2 : 146'd0 ;
+ assign MUX_wmi_dhF_q_1$write_1__VAL_2 =
+ { 1'd1, wsiS_reqFifo$D_OUT[165], wsiS_reqFifo$D_OUT[151:8] } ;
assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ;
assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ;
assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 =
@@ -1671,7 +1667,7 @@ module mkSMAdapter16B(wciS0_Clk,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ;
assign wmi_mFlagF_x_wire$wget = value__h6702 ;
assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ;
- assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ;
+ assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_1$write_1__VAL_2 ;
assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ;
assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ;
assign wmi_wmiResponse$whas = 1'd1 ;
@@ -1788,8 +1784,7 @@ module mkSMAdapter16B(wciS0_Clk,
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ;
- assign respF_pwEnqueue$whas =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ;
+ assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
@@ -1835,11 +1830,11 @@ module mkSMAdapter16B(wciS0_Clk,
// register fabWordsRemain
assign fabWordsRemain$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
MUX_fabWordsRemain$write_1__VAL_1 :
MUX_fabWordsRemain$write_1__VAL_2 ;
assign fabWordsRemain$EN =
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ;
// register firstMsgReq
@@ -1849,13 +1844,13 @@ module mkSMAdapter16B(wciS0_Clk,
// register lastMesg
assign lastMesg$D_IN =
(MUX_endOfMessage$write_1__SEL_1 ||
- WILL_FIRE_RL_wmrd_mesgBegin) ?
+ MUX_unrollCnt$write_1__SEL_1) ?
thisMesg :
32'hFEFEFFFE ;
assign lastMesg$EN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[165] ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgCount
@@ -1873,7 +1868,7 @@ module mkSMAdapter16B(wciS0_Clk,
endcase
end
assign mesgCount$EN =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wci_ctrl_IsO ;
@@ -1892,22 +1887,21 @@ module mkSMAdapter16B(wciS0_Clk,
// register mesgReqAddr
assign mesgReqAddr$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
14'd0 :
MUX_mesgReqAddr$write_1__VAL_2 ;
assign mesgReqAddr$EN =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
- WILL_FIRE_RL_wmrd_mesgBegin ;
+ MUX_unrollCnt$write_1__SEL_1 ;
// register mesgReqOK
assign mesgReqOK$D_IN =
- WILL_FIRE_RL_wmrd_mesgBodyResponse ||
- WILL_FIRE_RL_wmrd_mesgBegin ;
+ MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ;
assign mesgReqOK$EN =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
- WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ MUX_unrollCnt$write_1__SEL_1 ||
+ MUX_unrollCnt$write_1__SEL_2 ;
// register opcode
assign opcode$D_IN =
@@ -1937,10 +1931,10 @@ module mkSMAdapter16B(wciS0_Clk,
assign respF_rCache$D_IN =
{ 1'd1,
respF_rWrPtr,
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918,
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920,
respF_pwEnqueue$whas && respF_wDataIn$wget[165],
respF_pwEnqueue$whas && respF_wDataIn$wget[164],
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930 } ;
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928 } ;
assign respF_rCache$EN = respF_pwEnqueue$whas ;
// register respF_rRdPtr
@@ -1959,13 +1953,13 @@ module mkSMAdapter16B(wciS0_Clk,
// register thisMesg
always@(MUX_endOfMessage$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_1 or
- WILL_FIRE_RL_wmrd_mesgBegin or
+ MUX_unrollCnt$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_endOfMessage$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1;
- WILL_FIRE_RL_wmrd_mesgBegin:
+ MUX_unrollCnt$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2;
WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE;
default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
@@ -1974,17 +1968,16 @@ module mkSMAdapter16B(wciS0_Clk,
assign thisMesg$EN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[165] ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register unrollCnt
assign unrollCnt$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
assign unrollCnt$EN =
- WILL_FIRE_RL_wmrd_mesgBegin ||
- WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ;
// register valExpect
assign valExpect$D_IN = valExpect + 128'd1 ;
@@ -2134,14 +2127,14 @@ module mkSMAdapter16B(wciS0_Clk,
always@(WILL_FIRE_RL_wmi_dhF_both or
MUX_wmi_dhF_q_0$write_1__VAL_1 or
MUX_wmi_dhF_q_0$write_1__SEL_2 or
- MUX_wmi_dhF_q_0$write_1__VAL_2 or
+ MUX_wmi_dhF_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_dhF_both:
wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1;
MUX_wmi_dhF_q_0$write_1__SEL_2:
- wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2;
+ wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0$D_IN = wmi_dhF_q_1;
default: wmi_dhF_q_0$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
@@ -2156,13 +2149,13 @@ module mkSMAdapter16B(wciS0_Clk,
always@(WILL_FIRE_RL_wmi_dhF_both or
MUX_wmi_dhF_q_1$write_1__VAL_1 or
MUX_wmi_dhF_q_1$write_1__SEL_2 or
- MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr)
+ MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_dhF_both:
wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1;
MUX_wmi_dhF_q_1$write_1__SEL_2:
- wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2;
+ wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 146'd0;
default: wmi_dhF_q_1$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
@@ -2543,10 +2536,10 @@ module mkSMAdapter16B(wciS0_Clk,
x__h16878[10:0] :
respF_rRdPtr[10:0] ;
assign respF_memory$DIA =
- { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918,
+ { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920,
respF_pwEnqueue$whas && respF_wDataIn$wget[165],
respF_pwEnqueue$whas && respF_wDataIn$wget[164],
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930 } ;
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928 } ;
assign respF_memory$DIB =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign respF_memory$WEA = respF_pwEnqueue$whas ;
@@ -2565,7 +2558,7 @@ module mkSMAdapter16B(wciS0_Clk,
assign wmi_respF$ENQ =
wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady &&
wmi_wmiResponse$wget[129:128] != 2'd0 ;
- assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ;
assign wmi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
@@ -2575,9 +2568,9 @@ module mkSMAdapter16B(wciS0_Clk,
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
- assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918 =
+ assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920 =
respF_pwEnqueue$whas ? respF_wDataIn$wget[168:166] : 3'd0 ;
- assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930 =
+ assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928 =
respF_pwEnqueue$whas ? respF_wDataIn$wget[163:0] : 164'd0 ;
assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 =
wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady &&
@@ -3210,13 +3203,13 @@ module mkSMAdapter16B(wciS0_Clk,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
- if (WILL_FIRE_RL_wmrd_mesgBegin)
+ if (MUX_unrollCnt$write_1__SEL_1)
begin
v__h18699 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
- if (WILL_FIRE_RL_wmrd_mesgBegin)
+ if (MUX_unrollCnt$write_1__SEL_1)
$display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h",
v__h18699,
mesgCount,
View
97 rtl/mkSMAdapter32B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:47 EDT 2012
+// On Fri Oct 12 14:08:08 EDT 2012
//
//
// Ports:
@@ -920,9 +920,7 @@ module mkSMAdapter32B(wciS0_Clk,
WILL_FIRE_RL_wmi_reqF_decCtr,
WILL_FIRE_RL_wmi_reqF_deq,
WILL_FIRE_RL_wmi_reqF_incCtr,
- WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyRequest,
- WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmrd_mesgResptoWsi,
WILL_FIRE_RL_wmwt_doAbort,
WILL_FIRE_RL_wmwt_mesgBegin,
@@ -979,6 +977,8 @@ module mkSMAdapter32B(wciS0_Clk,
wire MUX_endOfMessage$write_1__SEL_1,
MUX_mesgCount$write_1__SEL_1,
MUX_mesgReqOK$write_1__SEL_3,
+ MUX_unrollCnt$write_1__SEL_1,
+ MUX_unrollCnt$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
@@ -1008,7 +1008,7 @@ module mkSMAdapter32B(wciS0_Clk,
v__h3904,
v__h4048;
reg [31 : 0] g_data__h25524;
- wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964;
+ wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968;
wire [31 : 0] rdat__h25567,
rdat__h25573,
rdat__h25579,
@@ -1097,7 +1097,7 @@ module mkSMAdapter32B(wciS0_Clk,
y__h23375,
y__h23387,
y__h23399;
- wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965;
+ wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966;
wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524,
wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542,
wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669,
@@ -1309,23 +1309,6 @@ module mkSMAdapter32B(wciS0_Clk,
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
- // rule RL_wmrd_mesgBegin
- assign WILL_FIRE_RL_wmrd_mesgBegin =
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- !wmi_sThreadBusy_d &&
- !wmi_sDataThreadBusy_d &&
- unrollCnt == 16'd0 ;
-
- // rule RL_wmrd_mesgBodyResponse
- assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
- wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 &&
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- unrollCnt != 16'd0 ;
-
// rule RL_wmwt_mesgBegin
assign CAN_FIRE_RL_wmwt_mesgBegin =
wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N &&
@@ -1503,10 +1486,23 @@ module mkSMAdapter32B(wciS0_Clk,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[309] ;
assign MUX_mesgCount$write_1__SEL_1 =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ;
assign MUX_mesgReqOK$write_1__SEL_3 =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ;
+ assign MUX_unrollCnt$write_1__SEL_1 =
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ !wmi_sThreadBusy_d &&
+ !wmi_sDataThreadBusy_d &&
+ unrollCnt == 16'd0 ;
+ assign MUX_unrollCnt$write_1__SEL_2 =
+ wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 &&
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ unrollCnt != 16'd0 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
@@ -1816,8 +1812,7 @@ module mkSMAdapter32B(wciS0_Clk,
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ;
- assign respF_pwEnqueue$whas =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ;
+ assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
@@ -1863,11 +1858,11 @@ module mkSMAdapter32B(wciS0_Clk,
// register fabWordsRemain
assign fabWordsRemain$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
MUX_fabWordsRemain$write_1__VAL_1 :
MUX_fabWordsRemain$write_1__VAL_2 ;
assign fabWordsRemain$EN =
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ;
// register firstMsgReq
@@ -1877,13 +1872,13 @@ module mkSMAdapter32B(wciS0_Clk,
// register lastMesg
assign lastMesg$D_IN =
(MUX_endOfMessage$write_1__SEL_1 ||
- WILL_FIRE_RL_wmrd_mesgBegin) ?
+ MUX_unrollCnt$write_1__SEL_1) ?
thisMesg :
32'hFEFEFFFE ;
assign lastMesg$EN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[309] ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgCount
@@ -1901,7 +1896,7 @@ module mkSMAdapter32B(wciS0_Clk,
endcase
end
assign mesgCount$EN =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wci_ctrl_IsO ;
@@ -1920,22 +1915,21 @@ module mkSMAdapter32B(wciS0_Clk,
// register mesgReqAddr
assign mesgReqAddr$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
14'd0 :
MUX_mesgReqAddr$write_1__VAL_2 ;
assign mesgReqAddr$EN =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
- WILL_FIRE_RL_wmrd_mesgBegin ;
+ MUX_unrollCnt$write_1__SEL_1 ;
// register mesgReqOK
assign mesgReqOK$D_IN =
- WILL_FIRE_RL_wmrd_mesgBodyResponse ||
- WILL_FIRE_RL_wmrd_mesgBegin ;
+ MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ;
assign mesgReqOK$EN =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
- WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ MUX_unrollCnt$write_1__SEL_1 ||
+ MUX_unrollCnt$write_1__SEL_2 ;
// register opcode
assign opcode$D_IN =
@@ -1965,10 +1959,10 @@ module mkSMAdapter32B(wciS0_Clk,
assign respF_rCache$D_IN =
{ 1'd1,
respF_rWrPtr,
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965,
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966,
respF_pwEnqueue$whas && respF_wDataIn$wget[309],
respF_pwEnqueue$whas && respF_wDataIn$wget[308],
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 } ;
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968 } ;
assign respF_rCache$EN = respF_pwEnqueue$whas ;
// register respF_rRdPtr
@@ -1987,13 +1981,13 @@ module mkSMAdapter32B(wciS0_Clk,
// register thisMesg
always@(MUX_endOfMessage$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_1 or
- WILL_FIRE_RL_wmrd_mesgBegin or
+ MUX_unrollCnt$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_endOfMessage$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1;
- WILL_FIRE_RL_wmrd_mesgBegin:
+ MUX_unrollCnt$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2;
WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE;
default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
@@ -2002,17 +1996,16 @@ module mkSMAdapter32B(wciS0_Clk,
assign thisMesg$EN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[309] ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register unrollCnt
assign unrollCnt$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
assign unrollCnt$EN =
- WILL_FIRE_RL_wmrd_mesgBegin ||
- WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ;
// register valExpect
assign valExpect$D_IN = valExpect + 256'd1 ;
@@ -2571,10 +2564,10 @@ module mkSMAdapter32B(wciS0_Clk,
x__h16878[10:0] :
respF_rRdPtr[10:0] ;
assign respF_memory$DIA =
- { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965,
+ { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966,
respF_pwEnqueue$whas && respF_wDataIn$wget[309],
respF_pwEnqueue$whas && respF_wDataIn$wget[308],
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 } ;
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968 } ;
assign respF_memory$DIB =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign respF_memory$WEA = respF_pwEnqueue$whas ;
@@ -2593,7 +2586,7 @@ module mkSMAdapter32B(wciS0_Clk,
assign wmi_respF$ENQ =
wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady &&
wmi_wmiResponse$wget[257:256] != 2'd0 ;
- assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ;
assign wmi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
@@ -2603,10 +2596,10 @@ module mkSMAdapter32B(wciS0_Clk,
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
- assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 =
- respF_pwEnqueue$whas ? respF_wDataIn$wget[307:0] : 308'd0 ;
- assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965 =
+ assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966 =
respF_pwEnqueue$whas ? respF_wDataIn$wget[312:310] : 3'd0 ;
+ assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968 =
+ respF_pwEnqueue$whas ? respF_wDataIn$wget[307:0] : 308'd0 ;
assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 =
wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady &&
(!x__h18954 || wmi_mFlagF_c_r != 2'd2) ;
@@ -3280,13 +3273,13 @@ module mkSMAdapter32B(wciS0_Clk,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
- if (WILL_FIRE_RL_wmrd_mesgBegin)
+ if (MUX_unrollCnt$write_1__SEL_1)
begin
v__h18699 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
- if (WILL_FIRE_RL_wmrd_mesgBegin)
+ if (MUX_unrollCnt$write_1__SEL_1)
$display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h",
v__h18699,
mesgCount,
View
134 rtl/mkSMAdapter4B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:39 EDT 2012
+// On Fri Oct 12 14:08:00 EDT 2012
//
//
// Ports:
@@ -919,9 +919,7 @@ module mkSMAdapter4B(wciS0_Clk,
WILL_FIRE_RL_wmi_reqF_decCtr,
WILL_FIRE_RL_wmi_reqF_deq,
WILL_FIRE_RL_wmi_reqF_incCtr,
- WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyRequest,
- WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmrd_mesgResptoWsi,
WILL_FIRE_RL_wmwt_doAbort,
WILL_FIRE_RL_wmwt_mesgBegin,
@@ -950,8 +948,8 @@ module mkSMAdapter4B(wciS0_Clk,
wire [31 : 0] MUX_mesgCount$write_1__VAL_2,
MUX_thisMesg$write_1__VAL_1,
MUX_thisMesg$write_1__VAL_2,
- MUX_wmi_mFlagF_q_0$write_1__VAL_2,
- MUX_wmi_mFlagF_q_1$write_1__VAL_2,
+ MUX_wmi_mFlagF_q_0$write_1__VAL_1,
+ MUX_wmi_mFlagF_q_1$write_1__VAL_1,
MUX_wmi_mFlagF_x_wire$wset_1__VAL_2,
MUX_wmi_reqF_q_0$write_1__VAL_1,
MUX_wmi_reqF_q_0$write_1__VAL_2,
@@ -977,14 +975,16 @@ module mkSMAdapter4B(wciS0_Clk,
wire MUX_endOfMessage$write_1__SEL_1,
MUX_mesgCount$write_1__SEL_1,
MUX_mesgReqOK$write_1__SEL_3,
+ MUX_unrollCnt$write_1__SEL_1,
+ MUX_unrollCnt$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wmi_dhF_q_0$write_1__SEL_1,
MUX_wmi_dhF_q_1$write_1__SEL_1,
- MUX_wmi_mFlagF_q_0$write_1__SEL_1,
- MUX_wmi_mFlagF_q_1$write_1__SEL_1,
+ MUX_wmi_mFlagF_q_0$write_1__SEL_2,
+ MUX_wmi_mFlagF_q_1$write_1__SEL_2,
MUX_wmi_mFlagF_x_wire$wset_1__SEL_1,
MUX_wmi_reqF_q_0$write_1__SEL_2,
MUX_wmi_reqF_q_1$write_1__SEL_2,
@@ -1034,7 +1034,7 @@ module mkSMAdapter4B(wciS0_Clk,
wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878;
wire [7 : 0] mesgMetaF_opcode__h23695;
wire [3 : 0] sendData_byteEn__h19245;
- wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881,
+ wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d876,
x__h23735,
x__h23747,
x__h23759,
@@ -1251,23 +1251,6 @@ module mkSMAdapter4B(wciS0_Clk,
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
- // rule RL_wmrd_mesgBegin
- assign WILL_FIRE_RL_wmrd_mesgBegin =
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- !wmi_sThreadBusy_d &&
- !wmi_sDataThreadBusy_d &&
- unrollCnt == 16'd0 ;
-
- // rule RL_wmrd_mesgBodyResponse
- assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
- wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 &&
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- unrollCnt != 16'd0 ;
-
// rule RL_wmwt_mesgBegin
assign CAN_FIRE_RL_wmwt_mesgBegin =
wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N &&
@@ -1445,10 +1428,23 @@ module mkSMAdapter4B(wciS0_Clk,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[57] ;
assign MUX_mesgCount$write_1__SEL_1 =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ;
assign MUX_mesgReqOK$write_1__SEL_3 =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ;
+ assign MUX_unrollCnt$write_1__SEL_1 =
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ !wmi_sThreadBusy_d &&
+ !wmi_sDataThreadBusy_d &&
+ unrollCnt == 16'd0 ;
+ assign MUX_unrollCnt$write_1__SEL_2 =
+ wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 &&
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ unrollCnt != 16'd0 ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
@@ -1472,9 +1468,9 @@ module mkSMAdapter4B(wciS0_Clk,
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ;
assign MUX_wmi_dhF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ;
- assign MUX_wmi_mFlagF_q_0$write_1__SEL_1 =
+ assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ;
- assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 =
+ assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ;
assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ;
@@ -1559,9 +1555,9 @@ module mkSMAdapter4B(wciS0_Clk,
(wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_1 : 38'd0 ;
assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ;
assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ;
- assign MUX_wmi_mFlagF_q_0$write_1__VAL_2 =
+ assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 =
(wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ;
- assign MUX_wmi_mFlagF_q_1$write_1__VAL_2 =
+ assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 =
(wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ;
assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 =
{ mesgMetaF_opcode__h23695, mesgMetaF_length__h23696 } ;
@@ -1756,8 +1752,7 @@ module mkSMAdapter4B(wciS0_Clk,
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ;
- assign respF_pwEnqueue$whas =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ;
+ assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
@@ -1803,11 +1798,11 @@ module mkSMAdapter4B(wciS0_Clk,
// register fabWordsRemain
assign fabWordsRemain$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
MUX_fabWordsRemain$write_1__VAL_1 :
MUX_fabWordsRemain$write_1__VAL_2 ;
assign fabWordsRemain$EN =
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ;
// register firstMsgReq
@@ -1817,13 +1812,13 @@ module mkSMAdapter4B(wciS0_Clk,
// register lastMesg
assign lastMesg$D_IN =
(MUX_endOfMessage$write_1__SEL_1 ||
- WILL_FIRE_RL_wmrd_mesgBegin) ?
+ MUX_unrollCnt$write_1__SEL_1) ?
thisMesg :
32'hFEFEFFFE ;
assign lastMesg$EN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[57] ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgCount
@@ -1841,7 +1836,7 @@ module mkSMAdapter4B(wciS0_Clk,
endcase
end
assign mesgCount$EN =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wci_ctrl_IsO ;
@@ -1860,22 +1855,21 @@ module mkSMAdapter4B(wciS0_Clk,
// register mesgReqAddr
assign mesgReqAddr$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
14'd0 :
MUX_mesgReqAddr$write_1__VAL_2 ;
assign mesgReqAddr$EN =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
- WILL_FIRE_RL_wmrd_mesgBegin ;
+ MUX_unrollCnt$write_1__SEL_1 ;
// register mesgReqOK
assign mesgReqOK$D_IN =
- WILL_FIRE_RL_wmrd_mesgBodyResponse ||
- WILL_FIRE_RL_wmrd_mesgBegin ;
+ MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ;
assign mesgReqOK$EN =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
- WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ MUX_unrollCnt$write_1__SEL_1 ||
+ MUX_unrollCnt$write_1__SEL_2 ;
// register opcode
assign opcode$D_IN =
@@ -1905,7 +1899,7 @@ module mkSMAdapter4B(wciS0_Clk,
assign respF_rCache$D_IN =
{ 1'd1,
respF_rWrPtr,
- IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881,
+ IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d876,
respF_pwEnqueue$whas && respF_wDataIn$wget[57],
respF_pwEnqueue$whas && respF_wDataIn$wget[56],
IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878 } ;
@@ -1927,13 +1921,13 @@ module mkSMAdapter4B(wciS0_Clk,
// register thisMesg
always@(MUX_endOfMessage$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_1 or
- WILL_FIRE_RL_wmrd_mesgBegin or
+ MUX_unrollCnt$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_endOfMessage$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1;
- WILL_FIRE_RL_wmrd_mesgBegin:
+ MUX_unrollCnt$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2;
WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE;
default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
@@ -1942,17 +1936,16 @@ module mkSMAdapter4B(wciS0_Clk,
assign thisMesg$EN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[57] ||
- WILL_FIRE_RL_wmrd_mesgBegin ||
+ MUX_unrollCnt$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register unrollCnt
assign unrollCnt$D_IN =
- WILL_FIRE_RL_wmrd_mesgBegin ?
+ MUX_unrollCnt$write_1__SEL_1 ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
assign unrollCnt$EN =
- WILL_FIRE_RL_wmrd_mesgBegin ||
- WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ;
// register valExpect
assign valExpect$D_IN = valExpect + 32'd1 ;
@@ -2157,42 +2150,41 @@ module mkSMAdapter4B(wciS0_Clk,
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_mFlagF_q_0
- always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or
- value__h6702 or
- WILL_FIRE_RL_wmi_mFlagF_both or
- MUX_wmi_mFlagF_q_0$write_1__VAL_2 or
- WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1)
+ always@(WILL_FIRE_RL_wmi_mFlagF_both or
+ MUX_wmi_mFlagF_q_0$write_1__VAL_1 or
+ MUX_wmi_mFlagF_q_0$write_1__SEL_2 or
+ value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1)
begin
case (1'b1) // synopsys parallel_case
- MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = value__h6702;
WILL_FIRE_RL_wmi_mFlagF_both:
- wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_2;
+ wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1;
+ MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702;
WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1;
default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_mFlagF_q_0$EN =
- WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ||
WILL_FIRE_RL_wmi_mFlagF_both ||
+ WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ||
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_mFlagF_q_1
- always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or
- value__h6702 or
- WILL_FIRE_RL_wmi_mFlagF_both or
- MUX_wmi_mFlagF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_mFlagF_decCtr)
+ always@(WILL_FIRE_RL_wmi_mFlagF_both or
+ MUX_wmi_mFlagF_q_1$write_1__VAL_1 or
+ MUX_wmi_mFlagF_q_1$write_1__SEL_2 or
+ value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr)
begin
case (1'b1) // synopsys parallel_case
- MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = value__h6702;
WILL_FIRE_RL_wmi_mFlagF_both:
- wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_2;
+ wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1;
+ MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702;
WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0;
default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_mFlagF_q_1$EN =
- WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ||
WILL_FIRE_RL_wmi_mFlagF_both ||
+ WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ||
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_operateD
@@ -2509,7 +2501,7 @@ module mkSMAdapter4B(wciS0_Clk,
x__h16878[10:0] :
respF_rRdPtr[10:0] ;
assign respF_memory$DIA =
- { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881,
+ { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d876,
respF_pwEnqueue$whas && respF_wDataIn$wget[57],
respF_pwEnqueue$whas && respF_wDataIn$wget[56],
IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878 } ;
@@ -2530,7 +2522,7 @@ module mkSMAdapter4B(wciS0_Clk,
assign wmi_respF$ENQ =
wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady &&
wmi_wmiResponse$wget[33:32] != 2'd0 ;
- assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ;
+ assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ;
assign wmi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
@@ -2540,10 +2532,10 @@ module mkSMAdapter4B(wciS0_Clk,
assign wsiS_reqFifo$CLR = 1'b0 ;
// remaining internal signals
+ assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d876 =
+ respF_pwEnqueue$whas ? respF_wDataIn$wget[60:58] : 3'd0 ;
assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878 =
respF_pwEnqueue$whas ? respF_wDataIn$wget[55:0] : 56'd0 ;
- assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 =
- respF_pwEnqueue$whas ? respF_wDataIn$wget[60:58] : 3'd0 ;
assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 =
wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady &&
(!x__h18954 || wmi_mFlagF_c_r != 2'd2) ;
@@ -3148,13 +3140,13 @@ module mkSMAdapter4B(wciS0_Clk,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
- if (WILL_FIRE_RL_wmrd_mesgBegin)
+ if (MUX_unrollCnt$write_1__SEL_1)
begin
v__h18699 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
- if (WILL_FIRE_RL_wmrd_mesgBegin)
+ if (MUX_unrollCnt$write_1__SEL_1)
$display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h",
v__h18699,
mesgCount,
View
193 rtl/mkSMAdapter8B.v
@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
-// On Fri Oct 12 11:31:41 EDT 2012
+// On Fri Oct 12 14:08:03 EDT 2012
//
//
// Ports:
@@ -919,9 +919,7 @@ module mkSMAdapter8B(wciS0_Clk,
WILL_FIRE_RL_wmi_reqF_decCtr,
WILL_FIRE_RL_wmi_reqF_deq,
WILL_FIRE_RL_wmi_reqF_incCtr,
- WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyRequest,
- WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmrd_mesgResptoWsi,
WILL_FIRE_RL_wmwt_doAbort,
WILL_FIRE_RL_wmwt_mesgBegin,
@@ -938,11 +936,11 @@ module mkSMAdapter8B(wciS0_Clk,
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
wire [96 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
- MUX_wsiM_reqFifo_q_1$write_1__VAL_1,
+ MUX_wsiM_reqFifo_q_1$write_1__VAL_2,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3;
wire [73 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1,
MUX_wmi_dhF_q_0$write_1__VAL_2,
- MUX_wmi_dhF_q_1$write_1__VAL_1;
+ MUX_wmi_dhF_q_1$write_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
@@ -978,19 +976,21 @@ module mkSMAdapter8B(wciS0_Clk,
wire MUX_endOfMessage$write_1__SEL_1,
MUX_mesgCount$write_1__SEL_1,
MUX_mesgReqOK$write_1__SEL_3,
+ MUX_unrollCnt$write_1__SEL_1,
+ MUX_unrollCnt$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
- MUX_wmi_dhF_q_0$write_1__SEL_2,
- MUX_wmi_dhF_q_1$write_1__SEL_2,
+ MUX_wmi_dhF_q_0$write_1__SEL_1,
+ MUX_wmi_dhF_q_1$write_1__SEL_1,
MUX_wmi_mFlagF_q_0$write_1__SEL_2,
MUX_wmi_mFlagF_q_1$write_1__SEL_2,
MUX_wmi_mFlagF_x_wire$wset_1__SEL_1,
MUX_wmi_reqF_q_0$write_1__SEL_2,
MUX_wmi_reqF_q_1$write_1__SEL_2,
- MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
- MUX_wsiM_reqFifo_q_1$write_1__SEL_2,
+ MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
+ MUX_wsiM_reqFifo_q_1$write_1__SEL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3;
@@ -1007,7 +1007,7 @@ module mkSMAdapter8B(wciS0_Clk,
v__h3904,
v__h4048;
reg [31 : 0] g_data__h24540;
- wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893;
+ wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d896;
wire [31 : 0] rdat__h24583,
rdat__h24589,
rdat__h24595,
@@ -1048,7 +1048,7 @@ module mkSMAdapter8B(wciS0_Clk,
y__h23087,
y__h23099,
y__h23111;
- wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d901;
+ wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d904;
wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524,
wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542,
wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670,
@@ -1259,23 +1259,6 @@ module mkSMAdapter8B(wciS0_Clk,
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
- // rule RL_wmrd_mesgBegin
- assign WILL_FIRE_RL_wmrd_mesgBegin =
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- !wmi_sThreadBusy_d &&
- !wmi_sDataThreadBusy_d &&
- unrollCnt == 16'd0 ;
-
- // rule RL_wmrd_mesgBodyResponse
- assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
- wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 &&
- wci_wslv_cState == 3'd2 &&
- (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
- smaCtrl[3:0] == 4'h9) &&
- unrollCnt != 16'd0 ;
-
// rule RL_wmwt_mesgBegin
assign CAN_FIRE_RL_wmwt_mesgBegin =
wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N &&
@@ -1453,10 +1436,23 @@ module mkSMAdapter8B(wciS0_Clk,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 &&
wsiS_reqFifo$D_OUT[93] ;
assign MUX_mesgCount$write_1__SEL_1 =
- WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
+ MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ;
assign MUX_mesgReqOK$write_1__SEL_3 =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ;
+ assign MUX_unrollCnt$write_1__SEL_1 =
+ wci_wslv_cState == 3'd2 &&
+ (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
+ smaCtrl[3:0] == 4'h9) &&
+ !wmi_sThreadBusy_d &&
+ !wmi_sDataThreadBusy_d &&
+ unrollCnt == 16'd0 ;
+ assign MUX_unrollCnt$write_1__SEL_2 =
+ wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 &&