ENH: increase bits of trigger data delay

SiLab-Bonn · Apr 9, 2018 · e3b1516 · e3b1516
1 parent 7418303
commit e3b1516
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Showing 4 changed files with 18 additions and 12 deletions.
diff --git a/basil/HL/tlu.py b/basil/HL/tlu.py
@@ -32,7 +32,6 @@ class tlu(RegisterHardwareLayer):
                   'TRIGGER_MODE': {'descr': {'addr': 1, 'size': 2, 'offset': 0}},
                   'TRIGGER_DATA_MSB_FIRST': {'descr': {'addr': 1, 'size': 1, 'offset': 2}},
                   'TRIGGER_ENABLE': {'descr': {'addr': 1, 'size': 1, 'offset': 3}},
-                  'TRIGGER_DATA_DELAY': {'descr': {'addr': 1, 'size': 4, 'offset': 4}},
                   'DATA_FORMAT': {'descr': {'addr': 2, 'size': 2, 'offset': 0}},
                   'EN_TLU_RESET_TIMESTAMP': {'descr': {'addr': 2, 'size': 1, 'offset': 5}},
                   'EN_TLU_VETO': {'descr': {'addr': 2, 'size': 1, 'offset': 6}},
@@ -49,8 +48,9 @@ class tlu(RegisterHardwareLayer):
                   'TRIGGER_LOW_TIMEOUT_ERROR_COUNTER': {'descr': {'addr': 31, 'size': 8, 'properties': ['ro']}},
                   'TLU_TRIGGER_ACCEPT_ERROR_COUNTER': {'descr': {'addr': 32, 'size': 8, 'properties': ['ro']}},
                   'TRIGGER_THRESHOLD': {'descr': {'addr': 33, 'size': 8}},
-                  'SOFT_TRIGGER': {'descr': {'addr': 34, 'size': 8, 'properties': ['writeonly']}}}
-    _require_version = "==10"
+                  'SOFT_TRIGGER': {'descr': {'addr': 34, 'size': 8, 'properties': ['writeonly']}},
+                  'TRIGGER_DATA_DELAY': {'descr': {'addr': 35, 'size': 8}}}
+    _require_version = "==11"
 
     def __init__(self, intf, conf):
         super(tlu, self).__init__(intf, conf)

diff --git a/firmware/modules/tlu/README.rst b/firmware/modules/tlu/README.rst
@@ -95,8 +95,6 @@ Registers
     +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
     | TRIGGER_ENABLE                         | 1                                | [3]    | r/w   | 0           | enable trigger FSM                                    |
     +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
-    | TRIGGER_DATA_DELAY                     | 1                                | [7:4]  | r/w   | 0           | additional TLU data delay for longer cables           |
-    +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
     | DATA_FORMAT                            | 2                                | [1:0]  | r/w   | 0           | format of trigger number output                       |
     +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
     | EN_TLU_RESET_TIMESTAMP                 | 2                                | [5]    | r/w   | 0           | reset time stamp to 0 on TLU reset (handsh. mode only)|
@@ -131,3 +129,5 @@ Registers
     +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
     | SOFT_TRIGGER                           | 34                               | [7:0]  | wo    | n/a         | manual software trigger (requires TRIGGER_MODE=0)     |
     +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
+    | TRIGGER_DATA_DELAY                     | 35                               | [7:0]  | r/w   | 0           | additional TLU data delay for longer cables           |
+    +----------------------------------------+----------------------------------+--------+-------+-------------+-------------------------------------------------------+
diff --git a/firmware/modules/tlu/tlu_controller_core.v b/firmware/modules/tlu/tlu_controller_core.v
@@ -62,7 +62,7 @@ module tlu_controller_core
     output wire [TIMESTAMP_N_OF_BIT-1:0] TIMESTAMP
 );
 
-localparam VERSION = 10;
+localparam VERSION = 11;
 
 // Registers
 wire SOFT_RST; // Address: 0
@@ -123,8 +123,6 @@ wire TLU_TRIGGER_DATA_MSB_FIRST; // set endianness of TLU number
 assign TLU_TRIGGER_DATA_MSB_FIRST = status_regs[1][2];
 wire CONF_TRIGGER_ENABLE;
 assign CONF_TRIGGER_ENABLE = status_regs[1][3];
-wire [3:0] TLU_TRIGGER_DATA_DELAY;
-assign TLU_TRIGGER_DATA_DELAY = status_regs[1][7:4];
 wire [1:0] CONF_DATA_FORMAT;
 assign CONF_DATA_FORMAT = status_regs[2][1:0];
 wire TLU_ENABLE_RESET_TS;
@@ -147,6 +145,9 @@ wire [7:0] CONF_TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
 assign CONF_TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES = status_regs[30];
 wire [7:0] CONF_TRIGGER_THRESHOLD;
 assign CONF_TRIGGER_THRESHOLD = status_regs[33];
+// at address 34 is SOFT_TRIGGER
+wire [7:0] TLU_TRIGGER_DATA_DELAY;
+assign TLU_TRIGGER_DATA_DELAY = status_regs[35];
 
 always @(posedge BUS_CLK)
 begin
@@ -186,8 +187,10 @@ begin
         status_regs[31] <= 8'b0; // trigger low timeout error
         status_regs[32] <= 8'b0; // trigger accept error
         status_regs[33] <= 8'b0; // trigger threshold
+        // at address 34 is SOFT_TRIGGER
+        status_regs[35] <= 8'b0; // trigger data delay
     end
-    else if(BUS_WR && BUS_ADD < 34)
+    else if(BUS_WR && BUS_ADD < 36)
     begin
         status_regs[BUS_ADD[5:0]] <= BUS_DATA_IN;
     end
@@ -270,6 +273,9 @@ always @ (posedge BUS_CLK) begin
             BUS_DATA_OUT <= TLU_TRIGGER_ACCEPT_ERROR_CNT;
         else if (BUS_ADD == 33)
             BUS_DATA_OUT <= status_regs[33];
+        // at address 34 is SOFT_TRIGGER
+        else if (BUS_ADD == 35)
+            BUS_DATA_OUT <= status_regs[35];
         else
             BUS_DATA_OUT <= 0;
     end
@@ -314,9 +320,9 @@ three_stage_synchronizer #(
 );
 */
 
-wire [3:0] TLU_TRIGGER_DATA_DELAY_SYNC;
+wire [7:0] TLU_TRIGGER_DATA_DELAY_SYNC;
 three_stage_synchronizer #(
-    .WIDTH(4)
+    .WIDTH(8)
 ) three_stage_trigger_data_delay_synchronizer (
     .CLK(TRIGGER_CLK),
     .IN(TLU_TRIGGER_DATA_DELAY),

diff --git a/firmware/modules/tlu/tlu_controller_fsm.v b/firmware/modules/tlu/tlu_controller_fsm.v
@@ -42,7 +42,7 @@ module tlu_controller_fsm
 
     input wire [7:0]            TLU_TRIGGER_LOW_TIME_OUT,
 //    input wire [4:0]            TLU_TRIGGER_CLOCK_CYCLES,
-    input wire [3:0]            TLU_TRIGGER_DATA_DELAY,
+    input wire [7:0]            TLU_TRIGGER_DATA_DELAY,
     input wire                  TLU_TRIGGER_DATA_MSB_FIRST,
     input wire                  TLU_ENABLE_VETO,
     input wire                  TLU_RESET_FLAG,