Skip to content
A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder
VHDL HTML Other
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
db
incremental_db
output_files
4bitCounterParLoad.jpg
4bitCounterParLoad_fpga.jpg
4bitCounterParLoad_modelsim.jpg
4bitCounter_ParLoad.qpf
4bitCounter_ParLoad.qsf
4bitCounter_ParLoad_description.txt
HalfAdder_VHDL.vhd
README.md
TwoInputAND_VHDL.vhd
TwoInputMultiplexor_VHDL.vhd
TwoInputXOR_VHDL.vhd
bcd7seg.vhd
bcd7seg.vhd.bak
clock_div.vhd
clock_div.vhd.bak
dFlipFlop.vhd
dFlipFlop.vhd.bak
nbitReg.vhd
nbitReg.vhd.bak
nbitTwoInputMux_VHDL.vhd
nbitTwoInputMux_VHDL.vhd.bak
nbit_incrementor.vhd
nbit_incrementor.vhd.bak
nbit_syncCount_parLoad.vhd
nbit_syncCount_parLoad.vhd.bak

README.md

4bitCounterParLoad

A 4bit Binary Counter with Parallel Load including a clock divider, a BCD decoder and a 7 segment display.

Information

This is a VHDL project for DSD-I1* a Cyclone IV FPGA made in Quartus 18.1 and is based in the example of pjbal.

Diagram:
Diagram

Behavioral VHDL code: nbit_syncCount_parLoad.vhd
Testbench VHDL code: nbit_syncCount_parLoad_tb.vhd

Modelsim:
Modelsim

FPGA:
FPGA

*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education DOI:10.1109/DSD.2019.00032

Licence

Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) stavros@ubinet.gr. It is free software, and may be redistributed under the terms of the GNU Licence.

You can’t perform that action at this time.