A 4bit Multiplier in VHDL
This is a VHDL project for DSD-I1* a Cyclone IV FPGA built in Quartus 18.1 to build a 2 x 4bit number multiplier using Full Adders and Half Adders.
Behavioral VHDL code: Multiplier4bit.vhd
Testbench VHDL code: Multiplier4bit_tb.vhd
*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education DOI:10.1109/DSD.2019.00032
Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) email@example.com. It is free software, and may be redistributed under the terms of the GNU Licence.