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A 4bit Multiplier in VHDL
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.qsys_edit
db
incremental_db
output_files
Multiplier4bit.jpg
Multiplier4bit.qpf
Multiplier4bit.qsf
Multiplier4bit.qws
Multiplier4bit_description.txt
Multiplier4bit_fpga.jpg
Multiplier4bit_modelsim.jpg
README.md
full_adder_vhdl_code.vhd
half_adder_vhdl_code.vhd
multiplier4bit.vhd
multiplier4bit.vhd.bak
multiplier4bit_dsd.vhd
multiplier4bit_dsd.vhd.bak
multiplier4bit_tb.vhd
multiplier4bit_tb.vhd.bak
multiplier4bit_tb2.vhd.bak

README.md

Multiplier4bit

A 4bit Multiplier in VHDL

Information

This is a VHDL project for DSD-I1* a Cyclone IV FPGA built in Quartus 18.1 to build a 2 x 4bit number multiplier using Full Adders and Half Adders.

Diagram:
Diagram

Behavioral VHDL code: Multiplier4bit.vhd
Testbench VHDL code: Multiplier4bit_tb.vhd

ModelSim:
ModelSim

FPGA:
FPGA

*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education DOI:10.1109/DSD.2019.00032

Licence

Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) stavros@ubinet.gr. It is free software, and may be redistributed under the terms of the GNU Licence.

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