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@SymbiFlow

SymbiFlow

Open source flow for generating bitstreams from Verilog.

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  1. Random ideas and interesting ideas for things we hope to eventually do.

    54 5

  2. Example designs showing different ways to use SymbiFlow toolchains.

    Verilog 116 36

  3. Documentation for SymbiFlow

    Python 42 15

  4. Forked from YosysHQ/icestorm

    Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

    Python 23 5

  5. Documenting the Xilinx 7-series bit-stream format.

    Python 512 94

  6. Forked from YosysHQ/prjtrellis

    Documenting the Lattice ECP5 bit-stream format.

    Python 19 2

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