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SDC/XDC create_clock and set_false_path constraints should propigate through Yosys #1291

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litghost opened this issue Jan 31, 2020 · 5 comments

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@litghost
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@litghost litghost commented Jan 31, 2020

Currently SDC constraints are passed directly to VPR, which means the net names need to be the output net names from Yosys. However, constraints should be specified on the nets in the input verilog, and then a new SDC constraints file should be output from Yosys with the new net names.

Adding this feature to the XDC plugin should work?

@tmichalak / @acomodi I believe this would allow the LiteX XDC constraints to be used throughout the flow?

@mithro FYI

@mithro
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@mithro mithro commented Jan 31, 2020

Yes.

We can also do the clock constraint propagation through PLLs and and other boxes here.

@mithro
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@mithro mithro commented Feb 1, 2020

@daveshah1 - FYI this is the direction we are planning on going with constraints with VPR. Do you think it would be useful for nextpnr at all?

@daveshah1
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@daveshah1 daveshah1 commented Feb 1, 2020

I implemented net aliases in nextpnr, so a constraint in nextpnr can be any of the names that Yosys gives to a net. But this could be useful too

@mithro
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@mithro mithro commented Feb 1, 2020

@daveshah1 How do you figure out the net aliases?

@daveshah1
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@daveshah1 daveshah1 commented Feb 1, 2020

In the JSON, the netnames section format allows more than one name for each net. I don't know if there is a BLIF equivalent.

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