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SDC/XDC create_clock and set_false_path constraints should propigate through Yosys #1291
Currently SDC constraints are passed directly to VPR, which means the net names need to be the output net names from Yosys. However, constraints should be specified on the nets in the input verilog, and then a new SDC constraints file should be output from Yosys with the new net names.
Adding this feature to the XDC plugin should work?