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Improvements to ice40 architecture #125

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Improvements to ice40 architecture #125

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115b07a
ice40: Making names match icebox further.
mithro May 14, 2018
3a727c0
ice40: Making N384 layout square.
mithro May 16, 2018
1a4ebaf
ice40: Improving the debug output.
mithro May 16, 2018
ab0b2a9
ice40: Use the top-routing method by default.
mithro May 16, 2018
8983846
tests: Disable timing analysis.
mithro May 18, 2018
5d66a0c
ice40: Remove io_latch_global
mithro May 18, 2018
cf9ed0a
ice40: node ID to icebox metadata file
JohnDMcMaster May 23, 2018
03a4794
ice40: Output the hlc names instead.
mithro May 23, 2018
3d88d43
Temp.
mithro May 24, 2018
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31 changes: 26 additions & 5 deletions ice40/cells/ff_array/ff_array.interconnect.xml
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@@ -1,8 +1,29 @@
<!-- set: ai sw=1 ts=1 sta et -->
<interconnect>
<direct name="in" input="BLK_IG-FF_ARRAY.in" output="BEL_FF-FF.in" />
<direct name="out" input="BEL_FF-FF.out" output="BLK_IG-FF_ARRAY.out" />
<complete name="clk" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF.clk" />
<complete name="s_r" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF.s_r" />
<complete name="cen" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF.cen" />
<direct name="in" input="BLK_IG-FF_ARRAY.in" output="BEL_FF-FF.in" />
<direct name="out" input="BEL_FF-FF.out" output="BLK_IG-FF_ARRAY.out" />
<direct name="clk0" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[0].clk" />
<direct name="clk1" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[1].clk" />
<direct name="clk2" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[2].clk" />
<direct name="clk3" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[3].clk" />
<direct name="clk4" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[4].clk" />
<direct name="clk5" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[5].clk" />
<direct name="clk6" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[6].clk" />
<direct name="clk7" input="BLK_IG-FF_ARRAY.clk" output="BEL_FF-FF[7].clk" />
<direct name="s_r0" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[0].s_r" />
<direct name="s_r1" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[1].s_r" />
<direct name="s_r2" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[2].s_r" />
<direct name="s_r3" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[3].s_r" />
<direct name="s_r4" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[4].s_r" />
<direct name="s_r5" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[5].s_r" />
<direct name="s_r6" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[6].s_r" />
<direct name="s_r7" input="BLK_IG-FF_ARRAY.s_r" output="BEL_FF-FF[7].s_r" />
<direct name="cen0" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[0].cen" />
<direct name="cen1" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[1].cen" />
<direct name="cen2" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[2].cen" />
<direct name="cen3" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[3].cen" />
<direct name="cen4" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[4].cen" />
<direct name="cen5" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[5].cen" />
<direct name="cen6" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[6].cen" />
<direct name="cen7" input="BLK_IG-FF_ARRAY.cen" output="BEL_FF-FF[7].cen" />
</interconnect>
40 changes: 22 additions & 18 deletions ice40/cells/io_local/io_local.pb_type.xml
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@@ -1,40 +1,44 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="BLK_IG-IO_LOCAL" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- SB_IO inputs -->
<output name="io_0_D_IN" num_pins="2" equivalent="false"/>
<output name="io_1_D_IN" num_pins="2" equivalent="false"/>
<output name="io_0_D_IN" num_pins="2" equivalent="false"/>
<output name="io_1_D_IN" num_pins="2" equivalent="false"/>

<!-- SB_IO outputs -->
<input name="io_0_D_OUT" num_pins="2" equivalent="false"/>
<input name="io_1_D_OUT" num_pins="2" equivalent="false"/>
<input name="io_0_D_OUT" num_pins="2" equivalent="false"/>
<input name="io_1_D_OUT" num_pins="2" equivalent="false"/>

<!-- Control signals -->
<input name="io_0_OUT_ENB" num_pins="1" equivalent="false"/>
<input name="io_1_OUT_ENB" num_pins="1" equivalent="false"/>
<input name="io_0_OUT_ENB" num_pins="1" equivalent="false"/>
<input name="io_1_OUT_ENB" num_pins="1" equivalent="false"/>

<input name="io_global_cen" num_pins="1" equivalent="false"/>
<clock name="io_global_inclk" num_pins="1" equivalent="false"/>
<clock name="io_global_outclk" num_pins="1" equivalent="false"/>
<input name="io_global_latch" num_pins="1" equivalent="false"/>

<pb_type name="BLK_IG-IO" num_pb="2">
<xi:include href="../../primitives/sb_io/sb_io.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
</pb_type>

<interconnect>
<direct name="io_0_D_IN" input="BLK_IG-IO[0].D_IN" output="BLK_IG-IO_LOCAL.io_0_D_IN"/>
<direct name="io_1_D_IN" input="BLK_IG-IO[1].D_IN" output="BLK_IG-IO_LOCAL.io_1_D_IN"/>
<direct name="io_0_D_IN" input="BLK_IG-IO[0].D_IN" output="BLK_IG-IO_LOCAL.io_0_D_IN" />
<direct name="io_1_D_IN" input="BLK_IG-IO[1].D_IN" output="BLK_IG-IO_LOCAL.io_1_D_IN" />

<direct name="io_0_D_OUT" input="BLK_IG-IO_LOCAL.io_0_D_OUT" output="BLK_IG-IO[0].D_OUT"/>
<direct name="io_1_D_OUT" input="BLK_IG-IO_LOCAL.io_1_D_OUT" output="BLK_IG-IO[1].D_OUT"/>
<direct name="io_0_D_OUT" input="BLK_IG-IO_LOCAL.io_0_D_OUT" output="BLK_IG-IO[0].D_OUT" />
<direct name="io_1_D_OUT" input="BLK_IG-IO_LOCAL.io_1_D_OUT" output="BLK_IG-IO[1].D_OUT" />

<direct name="io_0_OUT_ENB" input="BLK_IG-IO_LOCAL.io_0_OUT_ENB" output="BLK_IG-IO[0].OUT_ENB"/>
<direct name="io_1_OUT_ENB" input="BLK_IG-IO_LOCAL.io_1_OUT_ENB" output="BLK_IG-IO[1].OUT_ENB"/>
<direct name="io_0_OUT_ENB" input="BLK_IG-IO_LOCAL.io_0_OUT_ENB" output="BLK_IG-IO[0].OUT_ENB" />
<direct name="io_1_OUT_ENB" input="BLK_IG-IO_LOCAL.io_1_OUT_ENB" output="BLK_IG-IO[1].OUT_ENB" />

<complete name="io_global_cen" input="BLK_IG-IO_LOCAL.io_global_cen" output="BLK_IG-IO.io_global_cen"/>
<complete name="io_global_inclk" input="BLK_IG-IO_LOCAL.io_global_inclk" output="BLK_IG-IO.io_global_inclk"/>
<complete name="io_global_outclk" input="BLK_IG-IO_LOCAL.io_global_outclk" output="BLK_IG-IO.io_global_outclk"/>
<complete name="io_global_latch" input="BLK_IG-IO_LOCAL.io_global_latch" output="BLK_IG-IO.io_global_latch"/>
<direct name="io_global_cen0" input="BLK_IG-IO_LOCAL.io_global_cen" output="BLK_IG-IO[0].CEN" />
<direct name="io_global_cen1" input="BLK_IG-IO_LOCAL.io_global_cen" output="BLK_IG-IO[1].CEN" />
<direct name="io_global_inclk0" input="BLK_IG-IO_LOCAL.io_global_inclk" output="BLK_IG-IO[0].INCLK" />
<direct name="io_global_inclk1" input="BLK_IG-IO_LOCAL.io_global_inclk" output="BLK_IG-IO[1].INCLK" />
<direct name="io_global_outclk0" input="BLK_IG-IO_LOCAL.io_global_outclk" output="BLK_IG-IO[0].OUTCLK" />
<direct name="io_global_outclk1" input="BLK_IG-IO_LOCAL.io_global_outclk" output="BLK_IG-IO[1].OUTCLK" />
<direct name="io_global_latch0" input="BLK_IG-IO_LOCAL.io_global_latch" output="BLK_IG-IO[0].LATCH" />
<direct name="io_global_latch1" input="BLK_IG-IO_LOCAL.io_global_latch" output="BLK_IG-IO[1].LATCH" />
</interconnect>

</pb_type>
48 changes: 30 additions & 18 deletions ice40/cells/plb_local/plb_local.pb_type.xml
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Expand Up @@ -27,6 +27,12 @@
<output name="O6" num_pins="1" equivalent="false"/>
<output name="O7" num_pins="1" equivalent="false"/>

<!-- D flip-flop controls -->
<clock name="CLK" num_pins="1" equivalent="false"/>
<input name="EN" num_pins="1" equivalent="false"/>
<input name="SR" num_pins="1" equivalent="false"/>

<!-- Fast Carry output -->
<output name="FCOUT0" num_pins="1" equivalent="false"/>
<output name="FCOUT1" num_pins="1" equivalent="false"/>
<output name="FCOUT2" num_pins="1" equivalent="false"/>
Expand All @@ -36,12 +42,7 @@
<output name="FCOUT6" num_pins="1" equivalent="false"/>
<output name="FCOUT7" num_pins="1" equivalent="false"/>

<!-- D flip-flop controls -->
<clock name="CLK" num_pins="1" equivalent="false"/>
<input name="EN" num_pins="1" equivalent="false"/>
<input name="SR" num_pins="1" equivalent="false"/>

<!-- Carry chain -->
<!-- Fast Carry chain -->
<input name="FCIN" num_pins="1" equivalent="false"/>
<output name="FCOUT" num_pins="1" equivalent="false"/>

Expand All @@ -54,48 +55,61 @@
</pb_type>

<interconnect>
<!-- SB_LUT4 inputs -->
<direct name="I0[0]" input="BLK_IG-PLB_LOCAL.I0[0]" output="BLK_IG-LUT_CARRY[0].I[0]" />
<direct name="I0[1]" input="BLK_IG-PLB_LOCAL.I0[1]" output="BLK_IG-LUT_CARRY[0].I[1]" />
<direct name="I0[2]" input="BLK_IG-PLB_LOCAL.I0[2]" output="BLK_IG-LUT_CARRY[0].I[2]" />
<direct name="I0[3]" input="BLK_IG-PLB_LOCAL.I0[3]" output="BLK_IG-LUT_CARRY[0].I[3]" />

<direct name="I1[0]" input="BLK_IG-PLB_LOCAL.I1[0]" output="BLK_IG-LUT_CARRY[1].I[0]" />
<direct name="I1[1]" input="BLK_IG-PLB_LOCAL.I1[1]" output="BLK_IG-LUT_CARRY[1].I[1]" />
<mux name="I1[2]" input="BLK_IG-PLB_LOCAL.I1[2] BLK_IG-LUT_CARRY[0].LO" output="BLK_IG-LUT_CARRY[1].I[2]" />
<!-- <mux name="I1[2]" input="BLK_IG-PLB_LOCAL.I1[2] BLK_IG-LUT_CARRY[0].LO" output="BLK_IG-LUT_CARRY[1].I[2]" /> -->
<direct name="I1[2]" input="BLK_IG-PLB_LOCAL.I1[2]" output="BLK_IG-LUT_CARRY[1].I[2]" />
<direct name="I1[3]" input="BLK_IG-PLB_LOCAL.I1[3]" output="BLK_IG-LUT_CARRY[1].I[3]" />

<direct name="I2[0]" input="BLK_IG-PLB_LOCAL.I2[0]" output="BLK_IG-LUT_CARRY[2].I[0]" />
<direct name="I2[1]" input="BLK_IG-PLB_LOCAL.I2[1]" output="BLK_IG-LUT_CARRY[2].I[1]" />
<mux name="I2[2]" input="BLK_IG-PLB_LOCAL.I2[2] BLK_IG-LUT_CARRY[1].LO" output="BLK_IG-LUT_CARRY[2].I[2]" />
<!-- <mux name="I2[2]" input="BLK_IG-PLB_LOCAL.I2[2] BLK_IG-LUT_CARRY[1].LO" output="BLK_IG-LUT_CARRY[2].I[2]" /> -->
<direct name="I2[2]" input="BLK_IG-PLB_LOCAL.I2[2]" output="BLK_IG-LUT_CARRY[2].I[2]" />
<direct name="I2[3]" input="BLK_IG-PLB_LOCAL.I2[3]" output="BLK_IG-LUT_CARRY[2].I[3]" />

<direct name="I3[0]" input="BLK_IG-PLB_LOCAL.I3[0]" output="BLK_IG-LUT_CARRY[3].I[0]" />
<direct name="I3[1]" input="BLK_IG-PLB_LOCAL.I3[1]" output="BLK_IG-LUT_CARRY[3].I[1]" />
<mux name="I3[2]" input="BLK_IG-PLB_LOCAL.I3[2] BLK_IG-LUT_CARRY[2].LO" output="BLK_IG-LUT_CARRY[3].I[2]" />
<!-- <mux name="I3[2]" input="BLK_IG-PLB_LOCAL.I3[2] BLK_IG-LUT_CARRY[2].LO" output="BLK_IG-LUT_CARRY[3].I[2]" /> -->
<direct name="I3[2]" input="BLK_IG-PLB_LOCAL.I3[2]" output="BLK_IG-LUT_CARRY[3].I[2]" />
<direct name="I3[3]" input="BLK_IG-PLB_LOCAL.I3[3]" output="BLK_IG-LUT_CARRY[3].I[3]" />

<direct name="I4[0]" input="BLK_IG-PLB_LOCAL.I4[0]" output="BLK_IG-LUT_CARRY[4].I[0]" />
<direct name="I4[1]" input="BLK_IG-PLB_LOCAL.I4[1]" output="BLK_IG-LUT_CARRY[4].I[1]" />
<mux name="I4[2]" input="BLK_IG-PLB_LOCAL.I4[2] BLK_IG-LUT_CARRY[3].LO" output="BLK_IG-LUT_CARRY[4].I[2]" />
<!-- <mux name="I4[2]" input="BLK_IG-PLB_LOCAL.I4[2] BLK_IG-LUT_CARRY[3].LO" output="BLK_IG-LUT_CARRY[4].I[2]" /> -->
<direct name="I4[2]" input="BLK_IG-PLB_LOCAL.I4[2]" output="BLK_IG-LUT_CARRY[4].I[2]" />
<direct name="I4[3]" input="BLK_IG-PLB_LOCAL.I4[3]" output="BLK_IG-LUT_CARRY[4].I[3]" />

<direct name="I5[0]" input="BLK_IG-PLB_LOCAL.I5[0]" output="BLK_IG-LUT_CARRY[5].I[0]" />
<direct name="I5[1]" input="BLK_IG-PLB_LOCAL.I5[1]" output="BLK_IG-LUT_CARRY[5].I[1]" />
<mux name="I5[2]" input="BLK_IG-PLB_LOCAL.I5[2] BLK_IG-LUT_CARRY[4].LO" output="BLK_IG-LUT_CARRY[5].I[2]" />
<!-- <mux name="I5[2]" input="BLK_IG-PLB_LOCAL.I5[2] BLK_IG-LUT_CARRY[4].LO" output="BLK_IG-LUT_CARRY[5].I[2]" /> -->
<direct name="I5[2]" input="BLK_IG-PLB_LOCAL.I5[2]" output="BLK_IG-LUT_CARRY[5].I[2]" />
<direct name="I5[3]" input="BLK_IG-PLB_LOCAL.I5[3]" output="BLK_IG-LUT_CARRY[5].I[3]" />

<direct name="I6[0]" input="BLK_IG-PLB_LOCAL.I6[0]" output="BLK_IG-LUT_CARRY[6].I[0]" />
<direct name="I6[1]" input="BLK_IG-PLB_LOCAL.I6[1]" output="BLK_IG-LUT_CARRY[6].I[1]" />
<mux name="I6[2]" input="BLK_IG-PLB_LOCAL.I6[2] BLK_IG-LUT_CARRY[5].LO" output="BLK_IG-LUT_CARRY[6].I[2]" />
<!-- <mux name="I6[2]" input="BLK_IG-PLB_LOCAL.I6[2] BLK_IG-LUT_CARRY[5].LO" output="BLK_IG-LUT_CARRY[6].I[2]" /> -->
<direct name="I6[2]" input="BLK_IG-PLB_LOCAL.I6[2]" output="BLK_IG-LUT_CARRY[6].I[2]" />
<direct name="I6[3]" input="BLK_IG-PLB_LOCAL.I6[3]" output="BLK_IG-LUT_CARRY[6].I[3]" />

<direct name="I7[0]" input="BLK_IG-PLB_LOCAL.I7[0]" output="BLK_IG-LUT_CARRY[7].I[0]" />
<direct name="I7[1]" input="BLK_IG-PLB_LOCAL.I7[1]" output="BLK_IG-LUT_CARRY[7].I[1]" />
<mux name="I7[2]" input="BLK_IG-PLB_LOCAL.I7[2] BLK_IG-LUT_CARRY[6].LO" output="BLK_IG-LUT_CARRY[7].I[2]" />
<!-- <mux name="I7[2]" input="BLK_IG-PLB_LOCAL.I7[2] BLK_IG-LUT_CARRY[6].LO" output="BLK_IG-LUT_CARRY[7].I[2]" /> -->
<direct name="I7[2]" input="BLK_IG-PLB_LOCAL.I7[2]" output="BLK_IG-LUT_CARRY[7].I[2]" />
<direct name="I7[3]" input="BLK_IG-PLB_LOCAL.I7[3]" output="BLK_IG-LUT_CARRY[7].I[3]" />

<direct name="LUT2FF" input="BLK_IG-LUT_CARRY[7:0].O" output="BLK_IG-FF_ARRAY.in"/>
<!-- Flip Flops inputs -->
<complete name="CLK" input="BLK_IG-PLB_LOCAL.CLK" output="BLK_IG-FF_ARRAY.clk" />
<complete name="SR" input="BLK_IG-PLB_LOCAL.SR" output="BLK_IG-FF_ARRAY.s_r" />
<complete name="EN" input="BLK_IG-PLB_LOCAL.EN" output="BLK_IG-FF_ARRAY.cen" />
<direct name="LUT2FF" input="BLK_IG-LUT_CARRY[7:0].O" output="BLK_IG-FF_ARRAY.in" />

<!-- Flip Flop outputs -->
<mux name="O0" input="BLK_IG-LUT_CARRY[0].O BLK_IG-FF_ARRAY.out[0]" output="BLK_IG-PLB_LOCAL.O0" />
<mux name="O1" input="BLK_IG-LUT_CARRY[1].O BLK_IG-FF_ARRAY.out[1]" output="BLK_IG-PLB_LOCAL.O1" />
<mux name="O2" input="BLK_IG-LUT_CARRY[2].O BLK_IG-FF_ARRAY.out[2]" output="BLK_IG-PLB_LOCAL.O2" />
Expand All @@ -105,10 +119,7 @@
<mux name="O6" input="BLK_IG-LUT_CARRY[6].O BLK_IG-FF_ARRAY.out[6]" output="BLK_IG-PLB_LOCAL.O6" />
<mux name="O7" input="BLK_IG-LUT_CARRY[7].O BLK_IG-FF_ARRAY.out[7]" output="BLK_IG-PLB_LOCAL.O7" />

<complete name="CLK" input="BLK_IG-PLB_LOCAL.CLK" output="BLK_IG-FF_ARRAY.clk" />
<complete name="SR" input="BLK_IG-PLB_LOCAL.SR" output="BLK_IG-FF_ARRAY.s_r" />
<complete name="EN" input="BLK_IG-PLB_LOCAL.EN" output="BLK_IG-FF_ARRAY.cen" />

<!-- Fast carry outputs -->
<direct name="FCOUT0" input="BLK_IG-LUT_CARRY[0].FCOUT" output="BLK_IG-PLB_LOCAL.FCOUT0" />
<direct name="FCOUT1" input="BLK_IG-LUT_CARRY[1].FCOUT" output="BLK_IG-PLB_LOCAL.FCOUT1" />
<direct name="FCOUT2" input="BLK_IG-LUT_CARRY[2].FCOUT" output="BLK_IG-PLB_LOCAL.FCOUT2" />
Expand All @@ -118,6 +129,7 @@
<direct name="FCOUT6" input="BLK_IG-LUT_CARRY[6].FCOUT" output="BLK_IG-PLB_LOCAL.FCOUT6" />
<direct name="FCOUT7" input="BLK_IG-LUT_CARRY[7].FCOUT" output="BLK_IG-PLB_LOCAL.FCOUT7" />

<!-- Fast carry chain -->
<direct name="FCIN" input="BLK_IG-PLB_LOCAL.FCIN" output="BLK_IG-LUT_CARRY[0].FCIN">
<pack_pattern name="CARRYCHAIN" in_port="BLK_IG-PLB_LOCAL.FCIN" out_port="BLK_IG-LUT_CARRY[0].FCIN"/>
</direct>
Expand Down
4 changes: 3 additions & 1 deletion ice40/devices/layouts/N384/ntemplate.N384.fixed_layout.xml
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@@ -1,10 +1,12 @@
<!-- set: ai sw=1 ts=1 sta et -->
<fixed_layout name="{N}384" width="10" height="12">
<fixed_layout name="{N}384" width="12" height="12">
<col type="EMPTY" startx="0" priority="30"/>
<col type="BLK_TL-PIO_L" startx="1" priority="10"/>
<region type="BLK_TL-PLB" startx="2" endx="7" starty="2" endy="9" priority="4"/> <!-- Logic blocks 8x10 -->
<col type="BLK_TL-PIO_R" startx="8" priority="10"/>
<col type="EMPTY" startx="9" priority="30"/>
<col type="EMPTY" startx="10" priority="30"/>
<col type="EMPTY" startx="11" priority="30"/>

<row type="EMPTY" starty="0" priority="31"/>
<row type="BLK_TL-PIO_B" starty="1" priority="11"/>
Expand Down
5 changes: 5 additions & 0 deletions ice40/devices/top-routing-virt/arch.xml
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Expand Up @@ -50,9 +50,14 @@
</device>

<switchlist>
<switch type="mux" name="short" R="1" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="routing" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="buffer" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--
<switch type="mux" name="short" R="1" Cin="0" />
<switch type="mux" name="routing" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="buffer" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-->
</switchlist>

<segmentlist>
Expand Down