Symbiotic EDA

Repositories

• riscv-formal

  RISC-V Formal Verification Framework
  Verilog ISC 54 310 9 4 Updated Jan 26, 2021

• sedasuitedocs

  Symbiotic EDA Suite Docs
  Makefile 0 0 0 0 Updated Nov 16, 2020

• nerv

  Naive Educational RISC-V -- A simple single-stage RV32I processor
  SystemVerilog 0 8 0 0 Updated Nov 3, 2020

• sva-demos

  SVA examples and demonstration
  SystemVerilog 2 9 0 0 Updated Sep 8, 2020

• getting-started-FV
  VHDL 5 12 0 0 Updated Sep 2, 2020

• continuous-integration-resources
  Shell 0 1 0 0 Updated Jun 19, 2020

• traffic-lights
  Verilog 0 1 0 0 Updated Apr 11, 2020

• MARLANN

  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  Verilog 11 54 0 0 Updated Jul 3, 2019