Adding camera interface to control SoC

Signed-off-by: David Shah <davey1576@gmail.com>

demo/Makefile

@@ -2,21 +2,44 @@ CTRLSOC_DEV =
 MLACCEL_DEV =
 SEED = 1234
 
+CAMERA_RTL =					\
+	camera/phy/dphy_iserdes.v		\
+	camera/phy/byte_aligner.v		\
+	camera/phy/word_combiner.v		\
+	camera/csi/header_ecc.v			\
+	camera/csi/rx_packet_handler.v		\
+	camera/link/csi_rx_ice40.v		\
+	camera/misc/downsample.v		\
+	camera/cameraif.v
+
+SPI_RTL = 					\
+	spiflash.v
+
+SOC_RTL =					\
+	ctrlsoc.v				\
+	picorv32.v
+
+ML_RTL =					\
+	../rtl/top.v				\
+	../rtl/sequencer.v			\
+	../rtl/compute.v			\
+	../rtl/memory.v
+
 #####################################################################
 
 testbench.vcd: testbench flashinit.hex ctrlsoc_fw.hex
 	vvp -N testbench
 
-testbench: testbench.v spiflash.v ctrlsoc.v picorv32.v ../rtl/top.v ../rtl/sequencer.v ../rtl/compute.v ../rtl/memory.v
-	iverilog -s testbench -o $@ testbench.v spiflash.v ctrlsoc.v picorv32.v ../rtl/top.v ../rtl/sequencer.v ../rtl/compute.v ../rtl/memory.v $(shell yosys-config --datdir/ice40/cells_sim.v)
+testbench: testbench.v $(SPI_RTL) $(SOC_RTL) $(ML_RTL) $(CAMERA_RTL)
+	iverilog -s testbench -o $@ $^ $(shell yosys-config --datdir/ice40/cells_sim.v)
 
 flashinit.hex: flashinit.py
 	python3 flashinit.py
 
 #####################################################################
 
-ctrlsoc.json: ctrlsoc.v picorv32.v flashinit.hex
-	yosys -ql ctrlsoc.log -p 'synth_ice40 -top ctrlsoc -json ctrlsoc.json' ctrlsoc.v picorv32.v
+ctrlsoc.json: $(SOC_RTL) $(CAMERA_RTL) flashinit.hex
+	yosys -ql ctrlsoc.log -p 'synth_ice40 -top ctrlsoc -json ctrlsoc.json' $(filter %.v, $^)
 
 ctrlsoc.asc: ctrlsoc.pcf ctrlsoc.json
 	nextpnr-ice40 --freq 13 --up5k --asc ctrlsoc.asc --pcf ctrlsoc.pcf --json ctrlsoc.json
@@ -57,8 +80,8 @@ clean_ctrlsoc:
 #####################################################################
 
 mlaccel.blif: mlaccel.json
-mlaccel.json: ../rtl/top.v ../rtl/sequencer.v ../rtl/compute.v ../rtl/memory.v
-	yosys -ql mlaccel.log -p 'synth_ice40 -top mlaccel_top -json mlaccel.json -blif mlaccel.blif' ../rtl/top.v ../rtl/sequencer.v ../rtl/compute.v ../rtl/memory.v
+mlaccel.json: $(ML_RTL)
+	yosys -ql mlaccel.log -p 'synth_ice40 -top mlaccel_top -json mlaccel.json -blif mlaccel.blif' $(ML_RTL)
 
 mlaccel.asc: mlaccel.pcf mlaccel.json
 	nextpnr-ice40 --seed $(SEED) --freq 25 --up5k --asc mlaccel.asc --pcf mlaccel.pcf --json mlaccel.json

demo/camera/cameraif.v

@@ -115,9 +115,26 @@ module cameraif(
     reg [1:0] i2c_gpio;
     reg [1:0] i2c_read;
 
-    assign i2c_din = {cam_scl, cam_sda};
-    assign cam_sda = i2c_gpio[0] ? 1'bz : 1'b0;
-    assign cam_scl = i2c_gpio[1] ? 1'bz : 1'b0;
+    SB_IO #(
+        .PIN_TYPE(6'b 1010_01),
+        .PULLUP(1'b 1)
+    ) scl_buf (
+        .PACKAGE_PIN(cam_sda),
+        .OUTPUT_ENABLE(i2c_gpio[0]),
+        .D_OUT_0(1'b0),
+        .D_IN_0(i2c_din[0])
+    );
+
+    SB_IO #(
+        .PIN_TYPE(6'b 1010_01),
+        .PULLUP(1'b 1)
+    ) sda_buf (
+        .PACKAGE_PIN(cam_scl),
+        .OUTPUT_ENABLE(i2c_gpio[1]),
+        .D_OUT_0(1'b0),
+        .D_IN_0(i2c_din[1])
+    );
+
     assign cam_enable = 1'b1;
 
     always @(posedge sys_clk) begin

demo/ctrlsoc.pcf

@@ -27,3 +27,13 @@ set_io led5       26
 # ML QPI (on PMOD2)
 set_io ml_csb     20
 set_io ml_clk     18
+
+# Camera pins
+set_io cam_enable   3 #P1A7
+set_io cam_sda      34 #P1B3
+set_io cam_scl      28 #P1B10
+
+set_io dphy_clk     32 #P1B9
+set_io dphy_data[0] 42 #P1B7
+set_io dphy_data[1] 43 #P1B1
+set_io dphy_lp      48 #P1A8

demo/ctrlsoc.v

@@ -46,7 +46,15 @@ module ctrlsoc (
 
 	// mlaccel ctrl pins
 	output ml_csb,
-	output ml_clk
+	output ml_clk,
+
+	// Camera interface (PMOD 1A/1B)
+	input dphy_clk,
+	input [1:0] dphy_data,
+	input dphy_lp,
+
+	inout cam_sda, cam_scl,
+	output cam_enable,
 );
 	reg resetn = 0;
 	reg [5:0] reset_cnt = 0;
@@ -75,8 +83,10 @@ module ctrlsoc (
 	assign ledg_n = flash_csb || ((|last_flash_clk) == (&last_flash_clk));
 
 	reg led5_r, led4_r, led3_r, led2_r, led1_r;
+	wire camera_heartbeat;
 
-	assign led1 = led1_r;
+	//assign led1 = led1_r;
+	assign led1 = camera_heartbeat;
 	assign led2 = led2_r;
 	assign led3 = led3_r;
 	assign led4 = led4_r;
@@ -101,6 +111,9 @@ module ctrlsoc (
 	wire rxtx_ready;
 	wire [31:0] rxtx_rdata;
 
+	wire camera_ready;
+	wire [31:0] camera_rdata;
+
 	picorv32 #(
 		.ENABLE_COUNTERS(0),
 		.CATCH_MISALIGN(1),
@@ -113,7 +126,7 @@ module ctrlsoc (
 		.trap      (trap     ),
 		.mem_valid (mem_valid),
 		.mem_instr (mem_instr),
-		.mem_ready (mem_ready || flash_ready || rxtx_ready),
+		.mem_ready (mem_ready || flash_ready || rxtx_ready || camera_ready),
 		.mem_addr  (mem_addr ),
 		.mem_wdata (mem_wdata),
 		.mem_wstrb (mem_wstrb),
@@ -123,13 +136,15 @@ module ctrlsoc (
 			spram1_rselect ? spram1_rdata :
 			flash_ready    ? flash_rdata  :
 			rxtx_ready     ? rxtx_rdata   :
+			camera_ready   ? camera_rdata :
 			mem_rdata
 		)
 	);
 
 	wire addr_spram0 = mem_addr < 64*1024;
 	wire addr_spram1 = (mem_addr < 128*1024) && !(mem_addr < 64*1024);
 	wire addr_flash = (mem_addr < 2*16*1024*1024) && !(mem_addr < 128*1024);
+	wire addr_camera = mem_addr[31:24] == 8'h03;
 
 	ctrlsoc_rxtx rxtx (
 		.clk    (clk      ),
@@ -284,6 +299,27 @@ module ctrlsoc (
 		.flash_io2_oe (flash_io2_oe),
 		.flash_io3_oe (flash_io3_oe)
 	);
+
+	cameraif cam (
+		.dphy_clk(dphy_clk),
+		.dphy_data(dphy_data),
+		.dphy_lp(dphy_lp),
+
+		.cam_sda(cam_sda),
+		.cam_scl(cam_scl),
+		.cam_enable(cam_enable),
+
+		.cam_heartbeat(camera_heartbeat),
+
+		.sys_clk(clk),
+		.resetn(resetn),
+		.addr(mem_addr[15:0]),
+		.wdata(mem_wdata),
+		.wstrb(mem_wstrb),
+		.valid(addr_camera && mem_valid && !camera_ready),
+		.rdata(camera_rdata),
+		.ready(camera_ready)
+	);
 endmodule
 
 module ctrlsoc_spram (