Single spi #4
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Single spi #4
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…laccel into single_spi_reg_clock
…laccel into single_spi_reg_clock
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This pull request adds a new verilog file spi_client.v to replace the original qpi module.
The SPI client side is formally verified and tested to 400k cycles with the Raspberry Pi SPI master.
It currently does not handle clock glitching.
A new top level directory called ./pi is created with Python test files and a README.md that explains how to install the required modules and wire the Pi to the UP5K development board.