savefile

rtl/sspi/Makefile

@@ -4,8 +4,8 @@ gtkwave: testbench
 	gtkwave testbench.vcd spi.gtkwave
 
 
-testbench: testbench.v top.v
-	iverilog -DTRACE -s testbench -o testbench testbench.v top.v $(shell yosys-config --datdir/ice40/cells_sim.v)
+testbench: testbench.v top.v memory.v sequencer.v compute.v
+	iverilog -DTRACE -s testbench -o testbench testbench.v top.v memory.v sequencer.v compute.v $(shell yosys-config --datdir/ice40/cells_sim.v)
 	vvp -N testbench > >( tee testbench.log; )
 
 clean:

rtl/sspi/cmd_filter.txt

@@ -0,0 +1,7 @@
+20 = status
+21 = wbuf 
+22 = rbuf 
+23 = wmem 
+24 = rmem 
+25 = run  
+26 = stop 

rtl/sspi/spi.gtkwave

@@ -0,0 +1,139 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Fri Nov 16 14:38:41 2018
+[*]
+[dumpfile] "/home/matt/work/fpga/mlaccel/rtl/sspi/testbench.vcd"
+[dumpfile_mtime] "Fri Nov 16 14:38:13 2018"
+[dumpfile_size] 1538886
+[savefile] "/home/matt/work/fpga/mlaccel/rtl/sspi/spi.gtkwave"
+[timestart] 0
+[size] 1917 1020
+[pos] -1 -1
+*-16.000000 89100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] testbench.
+[treeopen] testbench.uut.
+[treeopen] testbench.uut.mem.
+[treeopen] testbench.uut.mem.ram[0].
+[sst_width] 253
+[signals_width] 492
+[sst_expanded] 1
+[sst_vpaned_height] 306
+@28
+testbench.clock
+@2024
+^1 /tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/state_filter.txt
+testbench.uut.state[5:0]
+@22
+testbench.uut.buffer_ptr[10:0]
+testbench.uut.dout_data[7:0]
+@8025
+testbench.cursor
+@28
+testbench.uut.reset
+testbench.uut.spi.spi_csb_di
+testbench.spi_clk
+@2022
+^2 /tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/cmd_filter.txt
+testbench.uut.din_data[7:0]
+@22
+testbench.uut.dout_data[7:0]
+@28
+testbench.uut.din_start
+testbench.uut.spi.di_start
+testbench.uut.din_valid
+testbench.uut.spi_active
+@c00022
+testbench.xfer[7:0]
+@28
+(0)testbench.xfer[7:0]
+(1)testbench.xfer[7:0]
+(2)testbench.xfer[7:0]
+(3)testbench.xfer[7:0]
+(4)testbench.xfer[7:0]
+(5)testbench.xfer[7:0]
+(6)testbench.xfer[7:0]
+(7)testbench.xfer[7:0]
+@1401200
+-group_end
+@28
+testbench.spi_mosi_reg
+testbench.spi_miso
+@200
+-
+@28
+testbench.uut.dout_valid
+testbench.uut.dout_ready
+testbench.uut.spi.dout_busy
+@c00024
+testbench.uut.spi.do_data[7:0]
+@28
+(0)testbench.uut.spi.do_data[7:0]
+(1)testbench.uut.spi.do_data[7:0]
+(2)testbench.uut.spi.do_data[7:0]
+(3)testbench.uut.spi.do_data[7:0]
+(4)testbench.uut.spi.do_data[7:0]
+(5)testbench.uut.spi.do_data[7:0]
+(6)testbench.uut.spi.do_data[7:0]
+(7)testbench.uut.spi.do_data[7:0]
+@1401200
+-group_end
+@24
+testbench.uut.spi.do_bit[2:0]
+testbench.uut.spi.glitch_guard_do_bit_q0[7:0]
+testbench.uut.spi.glitch_guard_do_bit[7:0]
+@28
+testbench.uut.spi_clk
+testbench.uut.spi.spi_miso
+@200
+-
+@c00028
+testbench.uut.spi.din_data[7:0]
+@28
+(0)testbench.uut.spi.din_data[7:0]
+(1)testbench.uut.spi.din_data[7:0]
+(2)testbench.uut.spi.din_data[7:0]
+(3)testbench.uut.spi.din_data[7:0]
+(4)testbench.uut.spi.din_data[7:0]
+(5)testbench.uut.spi.din_data[7:0]
+(6)testbench.uut.spi.din_data[7:0]
+(7)testbench.uut.spi.din_data[7:0]
+@1401200
+-group_end
+@24
+testbench.uut.spi.di_bit[2:0]
+@c00022
+testbench.uut.spi.di_data[7:0]
+@28
+(0)testbench.uut.spi.di_data[7:0]
+(1)testbench.uut.spi.di_data[7:0]
+(2)testbench.uut.spi.di_data[7:0]
+(3)testbench.uut.spi.di_data[7:0]
+(4)testbench.uut.spi.di_data[7:0]
+(5)testbench.uut.spi.di_data[7:0]
+(6)testbench.uut.spi.di_data[7:0]
+(7)testbench.uut.spi.di_data[7:0]
+@1401200
+-group_end
+@28
+testbench.uut.spi.spi_mosi
+@200
+-
+@28
+testbench.uut.spi.spi_clk_di
+testbench.uut.spi.glitch_guard_clock_q0
+testbench.uut.spi.glitch_guard_negedge
+testbench.uut.spi.glitch_guard_posedge
+testbench.uut.spi.clk_q1
+testbench.uut.spi.clk_q2
+@200
+-
+@22
+testbench.uut.mem.addr0[13:0]
+testbench.uut.mem.addr[15:0]
+testbench.uut.mem.rdata[63:0]
+testbench.uut.mem.wdata[63:0]
+testbench.uut.state[5:0]
+testbench.uut.buffer_ptr[10:0]
+testbench.uut.mem.wen[7:0]
+[pattern_trace] 1
+[pattern_trace] 0

rtl/sspi/state_filter.txt

@@ -0,0 +1,14 @@
+0 = halt 
+1 = status
+2 = wbuf
+3 = rbuf
+4 = wmem0
+5 = wmem1
+6 = wmem2
+7 = wmem3
+8 = rmem0
+9 = rmem1
+10 = rmem2
+11 = rmem3
+12 = run0
+13 = run1

rtl/sspi/testbench.v

@@ -163,16 +163,23 @@ module testbench;
 
 	task xfer_wait;
 		begin
-			xfer_negedge;
-			xfer_posedge;
 
 			xfer_negedge;
+			spi_miso_reg = 1'bz;
 			xfer_posedge;
+
+		//	xfer_negedge;
+		//	xfer_posedge;
+
 		end
 	endtask
 
 	task xfer_recv;
 		begin
+			xfer_negedge;
+			spi_miso_reg = 1'bz;
+			xfer_posedge;
+
 			xfer_negedge;
 			xfer[7] = spi_miso;
             xfer_posedge;
@@ -230,8 +237,8 @@ module testbench;
 	reg [7:0] outdata [0:128*1024-1];
 
 	initial begin
-		$readmemh("../asm/demo.hex", indata);
-		$readmemh("../sim/demo_out.hex", outdata);
+		$readmemh("../../asm/demo.hex", indata);
+		$readmemh("../../sim/demo_out.hex", outdata);
 	end
 
 	initial begin
@@ -242,81 +249,45 @@ module testbench;
 		$display("Uploading demo kernel.");
 		$fflush;
 
+        i= 0;
+        len = 1;
 		cursor = 0;
-		while (cursor < 128*1024) begin
-			if (indata[cursor] !== 8'h XX) begin
-				len = 1;
-				while ((len < 1024) && (len+cursor < 128*1024) &&
-						(indata[cursor+len] !== 8'h XX)) len = len+1;
-
-				if ((cursor % 2) != 0) begin
-					cursor = cursor - 1;
-					len = len + 1;
-				end
-
-				if ((len % 4) != 0) begin
-					len = len - (len % 4) + 4;
-				end
-
-				if (len > 1024) begin
-					len = 1024;
-				end
-
-				$display("  uploading %4d bytes to 0x%05x", len, cursor);
+		while (cursor < 32) begin
+                i = 0;
+				$display("  uploading %4d bytes from 0x%05x", len, cursor);
 				$fflush;
 
 				xfer_start;
 				xfer_send_byte(8'h 21);
-				for (i = 0; i < len; i = i+1)
-					xfer_send_byte(indata[cursor+i]);
+                xfer_send_byte(cursor);
 				xfer_stop;
 
 				xfer_start;
 				xfer_send_byte(8'h 23);
-				xfer_send_hword(cursor >> 1);
-				xfer_send_byte(len >> 2);
+				xfer_send_hword(cursor);
+				xfer_send_byte(len);
 				xfer_wait;
 				xfer_recv;
+
 				while (xfer != 8'h 00)
 					xfer_recv;
 				xfer_stop;
 
 				cursor = cursor + len;
-			end else begin
-				cursor = cursor + 1;
-			end
 		end
-
 		$display("Readback.");
 		$fflush;
 
+        len = 1;
 		cursor = 0;
-		while (cursor < 128*1024) begin
-			if (indata[cursor] !== 8'h XX) begin
-				len = 1;
-				while ((len < 1024) && (len+cursor < 128*1024) &&
-						(indata[cursor+len] !== 8'h XX)) len = len+1;
-
-				if ((cursor % 2) != 0) begin
-					cursor = cursor - 1;
-					len = len + 1;
-				end
-
-				if ((len % 4) != 0) begin
-					len = len - (len % 4) + 4;
-				end
-
-				if (len > 1024) begin
-					len = 1024;
-				end
-
+		while (cursor < 32) begin
 				$display("  downloading %4d bytes from 0x%05x", len, cursor);
 				$fflush;
 
 				xfer_start;
 				xfer_send_byte(8'h 24);
-				xfer_send_hword(cursor >> 1);
-				xfer_send_byte(len >> 2);
+				xfer_send_hword(cursor);
+				xfer_send_byte(len);
 				xfer_wait;
 				xfer_recv;
 				while (xfer != 8'h 00)
@@ -326,20 +297,17 @@ module testbench;
 				xfer_start;
 				xfer_send_byte(8'h 22);
 				xfer_wait;
-				for (i = 0; i < len; i = i+1) begin
-					xfer_recv;
-					if (indata[cursor+i] !== 8'h XX && indata[cursor+i] !== xfer) begin
-						$display("ERROR at %d: expected 0x%02x, got 0x%02x", cursor+i, indata[cursor+i], xfer);
-					end
-				end
+                xfer_recv;
+                if( xfer != cursor) begin
+                    $display("ERROR at %4d: expected 0x%02x, got 0x%02x", cursor, cursor, xfer);
+                end
 				xfer_stop;
 
 				cursor = cursor + len;
-			end else begin
-				cursor = cursor + 1;
-			end
 		end
 
+
+        $finish;
 		$display("Running kernel.");
 		$fflush;