looking at null bytes

rtl/sspi/compute.v

@@ -0,0 +1 @@
+../compute.v

rtl/sspi/memory.v

@@ -0,0 +1 @@
+../memory.v

rtl/sspi/sequencer.v

@@ -0,0 +1 @@
+../sequencer.v

rtl/sspi/spi.gtkwave

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Fri Nov 16 14:38:41 2018
+[*] Fri Nov 16 17:18:13 2018
 [*]
 [dumpfile] "/home/matt/work/fpga/mlaccel/rtl/sspi/testbench.vcd"
-[dumpfile_mtime] "Fri Nov 16 14:38:13 2018"
-[dumpfile_size] 1538886
+[dumpfile_mtime] "Fri Nov 16 17:17:10 2018"
+[dumpfile_size] 1547642
 [savefile] "/home/matt/work/fpga/mlaccel/rtl/sspi/spi.gtkwave"
-[timestart] 0
+[timestart] 103746
 [size] 1917 1020
 [pos] -1 -1
-*-16.000000 89100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-8.000000 104454 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] testbench.
 [treeopen] testbench.uut.
 [treeopen] testbench.uut.mem.
@@ -21,27 +21,30 @@
 @28
 testbench.clock
 @2024
-^1 /tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/state_filter.txt
+^1 /home/matt/work/fpga/mlaccel/rtl/sspi/../../../../../../../tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/../../../../../../../tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/state_filter.txt
 testbench.uut.state[5:0]
 @22
 testbench.uut.buffer_ptr[10:0]
 testbench.uut.dout_data[7:0]
-@8025
+@8024
 testbench.cursor
 @28
 testbench.uut.reset
 testbench.uut.spi.spi_csb_di
 testbench.spi_clk
-@2022
-^2 /tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/cmd_filter.txt
-testbench.uut.din_data[7:0]
 @22
 testbench.uut.dout_data[7:0]
 @28
 testbench.uut.din_start
 testbench.uut.spi.di_start
 testbench.uut.din_valid
 testbench.uut.spi_active
+@22
+testbench.uut.din_data[7:0]
+@29
+testbench.xfer_wait_start
+@28
+testbench.xfer_read_start
 @c00022
 testbench.xfer[7:0]
 @28
@@ -57,6 +60,7 @@ testbench.xfer[7:0]
 -group_end
 @28
 testbench.spi_mosi_reg
+testbench.uut.spi.spi_csb_di
 testbench.spi_miso
 @200
 -
@@ -77,16 +81,19 @@ testbench.uut.spi.do_data[7:0]
 (7)testbench.uut.spi.do_data[7:0]
 @1401200
 -group_end
-@24
+@c00024
 testbench.uut.spi.do_bit[2:0]
-testbench.uut.spi.glitch_guard_do_bit_q0[7:0]
-testbench.uut.spi.glitch_guard_do_bit[7:0]
 @28
-testbench.uut.spi_clk
+(0)testbench.uut.spi.do_bit[2:0]
+(1)testbench.uut.spi.do_bit[2:0]
+(2)testbench.uut.spi.do_bit[2:0]
+@1401200
+-group_end
+@28
 testbench.uut.spi.spi_miso
 @200
 -
-@c00028
+@c00022
 testbench.uut.spi.din_data[7:0]
 @28
 (0)testbench.uut.spi.din_data[7:0]
@@ -101,7 +108,7 @@ testbench.uut.spi.din_data[7:0]
 -group_end
 @24
 testbench.uut.spi.di_bit[2:0]
-@c00022
+@c00028
 testbench.uut.spi.di_data[7:0]
 @28
 (0)testbench.uut.spi.di_data[7:0]
@@ -115,6 +122,7 @@ testbench.uut.spi.di_data[7:0]
 @1401200
 -group_end
 @28
+testbench.uut.spi_clk
 testbench.uut.spi.spi_mosi
 @200
 -
@@ -127,6 +135,20 @@ testbench.uut.spi.clk_q1
 testbench.uut.spi.clk_q2
 @200
 -
+@24
+testbench.uut.spi.di_bit[2:0]
+@22
+testbench.uut.spi.glitch_guard_di_bit_q0[3:0]
+testbench.uut.spi.glitch_guard_di_bit[3:0]
+@200
+-
+@24
+testbench.uut.spi.do_bit[2:0]
+@22
+testbench.uut.spi.glitch_guard_do_bit_q0[3:0]
+testbench.uut.spi.glitch_guard_do_bit[3:0]
+@200
+-
 @22
 testbench.uut.mem.addr0[13:0]
 testbench.uut.mem.addr[15:0]

rtl/sspi/testbench.v

@@ -34,6 +34,8 @@ module testbench;
 	reg spi_miso_reg = 0;
 	reg spi_io2_reg;
 	reg spi_io3_reg;
+    reg xfer_read_start = 0;
+    reg xfer_wait_start = 0;
 
     wire spi_mosi = spi_mosi_reg;
 	wire spi_miso = spi_miso_reg;
@@ -161,21 +163,44 @@ module testbench;
 		end
 	endtask
 
+    // null byte
 	task xfer_wait;
 		begin
 
+            xfer_wait_start = 1;
 			xfer_negedge;
 			spi_miso_reg = 1'bz;
 			xfer_posedge;
 
-		//	xfer_negedge;
-		//	xfer_posedge;
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+            xfer_wait_start = 0;
 
 		end
 	endtask
 
 	task xfer_recv;
 		begin
+            xfer_read_start = 1;
 			xfer_negedge;
 			spi_miso_reg = 1'bz;
 			xfer_posedge;
@@ -211,6 +236,7 @@ module testbench;
 			xfer_negedge;
 			xfer[0] = spi_miso;
             xfer_posedge;
+            xfer_read_start = 0;
 
 		end
 	endtask
@@ -240,7 +266,7 @@ module testbench;
 		$readmemh("../../asm/demo.hex", indata);
 		$readmemh("../../sim/demo_out.hex", outdata);
 	end
-
+    integer num_tests = 32;
 	initial begin
 		xfer_stop;
 
@@ -252,7 +278,7 @@ module testbench;
         i= 0;
         len = 1;
 		cursor = 0;
-		while (cursor < 32) begin
+		while (cursor < num_tests) begin
                 i = 0;
 				$display("  uploading %4d bytes from 0x%05x", len, cursor);
 				$fflush;
@@ -280,7 +306,7 @@ module testbench;
 
         len = 1;
 		cursor = 0;
-		while (cursor < 32) begin
+		while (cursor < num_tests) begin
 				$display("  downloading %4d bytes from 0x%05x", len, cursor);
 				$fflush;
 

rtl/sspi/top.v

@@ -496,10 +496,10 @@ module mlaccel_spi (
 	reg glitch_guard_posedge = 0;
 	reg glitch_guard_negedge = 0;
 	reg glitch_guard_di_stx = 0;
-	reg [7:0] glitch_guard_di_bit;
-	reg [7:0] glitch_guard_di_bit_q0;
-	reg [7:0] glitch_guard_do_bit;
-	reg [7:0] glitch_guard_do_bit_q0;
+	reg [3:0] glitch_guard_di_bit;
+	reg [3:0] glitch_guard_di_bit_q0;
+	reg [3:0] glitch_guard_do_bit;
+	reg [3:0] glitch_guard_do_bit_q0;
     reg di_toggle;
 
 	always @(negedge clock) begin
@@ -514,10 +514,10 @@ module mlaccel_spi (
 		// must have been low before posedge and high before negedge
 		glitch_guard_posedge <= !glitch_guard_clock_q0;
 		glitch_guard_negedge <= glitch_guard_clock_q0;
-		glitch_guard_di_bit <= glitch_guard_di_bit_q0;
-		glitch_guard_do_bit <= glitch_guard_do_bit_q0;
 
 		// delay some signals to protect against double clocking
+		glitch_guard_di_bit <= glitch_guard_di_bit_q0;
+		glitch_guard_do_bit <= glitch_guard_do_bit_q0;
 		glitch_guard_di_stx <= glitch_guard_di_stx_q0;
 	end
 
@@ -552,9 +552,9 @@ module mlaccel_spi (
 		end else begin
 			if (glitch_guard_negedge) begin
                 if(di_start)
-                    do_bit <= 0;
+                    do_bit <= 7;
                 else
-                    do_bit <= do_bit  + 1;
+                    do_bit <= glitch_guard_do_bit + 1;
 
                 // send data
                 spi_miso <= do_data[7-glitch_guard_do_bit];
@@ -580,7 +580,7 @@ module mlaccel_spi (
 	end
 
 	reg dout_busy;
-	assign dout_ready = glitch_guard_do_bit == 0 && dout_valid && !dout_busy;
+	assign dout_ready = glitch_guard_do_bit == 7 && dout_valid && !dout_busy;
 	assign active = active_q1;
 
 	always @(posedge clock) begin
@@ -597,7 +597,7 @@ module mlaccel_spi (
 			do_data <= dout_data;
 			dout_busy <= 1;
 		end
-		if (glitch_guard_do_bit == 7) begin
+		if (glitch_guard_do_bit == 6) begin
 			dout_busy <= 0;
 		end
 		if (!active) begin