Endianness Confusion Load Inst test

[mdxg]

Hey Clifford,

I build a small RiscV processor to get a bit of practice in the topic. The core is working but I want to verify that the core is really ISA conform. For this purpose, is modified your Picorv32 example to work with my core. The tests are starting and working but the checks for the lb, lbu, lh and lhu do always fail with the assertion assert(spec_rd_wdata == rd_wdata) . By looking at the trace files I do not get why.

The spec says that the read mask for a lb for example should be 0b1000. From my understanding the read mask should be 0b0001 since RiscV is said to be a little-endian machine. With the readmask of 0b1000 the spec says hat for a memory read data of 0x00000001 the write back value should be 0x00000000.

Can you explain me why or point me in the direction of the point I miss?

Attached is the trace file of the missing test
insn_lb_ch0.zip

[cliffordwolf]

This looks like you don't have RISCV_FORMAL_ALIGNED_MEM set, but are testing a core that would need this setting to be enabled. See https://github.com/cliffordwolf/riscv-formal/blob/master/docs/config.md#riscv_formal_aligned_mem for details.

Edit: Other way around. It looks like you have RISCV_FORMAL_ALIGNED_MEM set but are testing a core that doesn't need it. :)

[mdxg]

Thanks fixed it :)