RVFIMON generate.py not creating ialign16 #30
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I think I've fixed this in PR #31 |
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I think I've fixed this in PR #31 |
When running monitor/generate.py with default arguments, wire ialign16 is not generated in the output of any instruction module. It appears that print_rewrite_file cannot handle the nested `ifdefs present in the various insn_*.v files.
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