Update checks.cfg

cores/serv/checks.cfg

@@ -16,19 +16,17 @@ causal    1     80
 
 [script-sources]
 read_verilog -sv @basedir@/cores/@core@/wrapper.sv
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_ctrl.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_mem_if.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_decode.v
 read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/ser_add.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_top.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/wb_gpio.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_csr.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_regfile.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/riscv_timer.v
 read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/ser_lt.v
 read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/ser_shift.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/shift_reg.v
 read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_alu.v
 read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_bufreg.v
-read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_clock_gen.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_csr.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_ctrl.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_decode.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_mem_if.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_mpram.v
 read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_params.vh
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_regfile.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_top.v
+read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/shift_reg.v