Small fixes for monitor generation #31
Merged
Conversation
added 3 commits
Sep 18, 2019
This is required to properly handle the BEQ instruction with compressed instructions disabled. Currently in this case invalid verilog output is produced.
This is unfortunate as it requires switching between wire/reg, but otherwise icarus verilog complains that this always block has no sensitivity list.
This should save people one step when checking the repository out on Linux
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Hi Clifford,
It turns out that currently generate.py produces invalid Verilog for RV32I (C extension disabled), particularly you end up with
ialign16not getting defined. This is because some instructions (such as BEQ) have nested ifdefs that aren't handled by the parser. I've extended it to track a stack of ifdefs instead. This also cuts down the lines of code a little and makes it easier to extend for additional flags.The other two changes are just niceties whilst I was in the vicinity.