Switch "const" and "rand" modifier order

The current Yosys only accepts the order: rand const
The other way round results in:
	ERROR: syntax error, unexpected TOK_RAND

And "rand const" is also the way they show it in their README:
https://github.com/YosysHQ/yosys/blob/master/README.md#non-standard-or-systemverilog-features-for-formal-verification

checks/rvfi_macros.py

@@ -18,7 +18,7 @@
 print("")
 print("`ifdef YOSYS")
 print("`define rvformal_rand_reg rand reg")
-print("`define rvformal_const_rand_reg const rand reg")
+print("`define rvformal_const_rand_reg rand const reg")
 print("`else")
 print("`ifdef SIMULATION")
 print("`define rvformal_rand_reg reg")

checks/rvfi_macros.vh

@@ -2,7 +2,7 @@
 
 `ifdef YOSYS
 `define rvformal_rand_reg rand reg
-`define rvformal_const_rand_reg const rand reg
+`define rvformal_const_rand_reg rand const reg
 `else
 `ifdef SIMULATION
 `define rvformal_rand_reg reg

docs/config.md

@@ -141,7 +141,7 @@ For formal verification with Yosys (i.e. when `YOSYS` is defined), this will be
 converted to the following code:
 
     rand reg [7:0] anyseq;
-    const rand reg [7:0] anyconst;
+    rand const reg [7:0] anyconst;
 
 For simulation (i.e. when `SIMULATION` is defined), this will be converted to: