diff --git a/docs/dev_notes/antlr.rst b/docs/dev_notes/antlr.rst
index 76adf2b..d457459 100644
--- a/docs/dev_notes/antlr.rst
+++ b/docs/dev_notes/antlr.rst
@@ -15,7 +15,7 @@ Download antlr4::
 Add some convenience aliases to ``.bash_aliases``::
 
     export CLASSPATH=".:/usr/local/lib/antlr-4.9.3-complete.jar:$CLASSPATH"
-    alias antlr4='java -Xmx500M -cp "/usr/local/lib/aantlr-4.9.3-complete.jar:$CLASSPATH" org.antlr.v4.Tool'
+    alias antlr4='java -Xmx500M -cp "/usr/local/lib/antlr-4.9.3-complete.jar:$CLASSPATH" org.antlr.v4.Tool'
     alias grun='java org.antlr.v4.gui.TestRig'
 
 Extra alias used in py3antlr4book examples::
diff --git a/systemrdl/compiler.py b/systemrdl/compiler.py
index 6ff1a99..4a11429 100644
--- a/systemrdl/compiler.py
+++ b/systemrdl/compiler.py
@@ -420,7 +420,7 @@ def eval(self, expression: str) -> rdltypes.RDLValue:
 
         .. versionadded:: 1.8
         """
-        # Create local message handler that suppresses the usual ouput
+        # Create local message handler that suppresses the usual output
         # to stderr.
         # Instead raises ValueError on any error
         msg_printer = messages.MessageExceptionRaiser()
diff --git a/systemrdl/core/elaborate.py b/systemrdl/core/elaborate.py
index f500404..51fa012 100644
--- a/systemrdl/core/elaborate.py
+++ b/systemrdl/core/elaborate.py
@@ -569,7 +569,7 @@ def exit_Component(self, node: Node) -> None:
         if node.inst.type_name is not None:
             extra_type_name_segments = []
 
-            # Augment based on paramter overrides as per 5.1.1.4
+            # Augment based on parameter overrides as per 5.1.1.4
             if node.inst.original_def is not None:
                 for i, inst_parameter in enumerate(node.inst.parameters):
                     orig_param_value = node.inst.original_def.parameters[i].get_value()
diff --git a/systemrdl/core/properties.py b/systemrdl/core/properties.py
index 963eaa4..024d236 100644
--- a/systemrdl/core/properties.py
+++ b/systemrdl/core/properties.py
@@ -235,21 +235,21 @@ def _validate_width_eq_or_smaller(self, node: m_node.VectorNode, value: Any) ->
         if isinstance(value, int):
             if node.width < value.bit_length():
                 self.env.msg.error(
-                    "A counter's %s cannot refrence a value wider than the counter itself."
+                    "A counter's %s cannot reference a value wider than the counter itself."
                     % (self.get_name()),
                     node.inst.property_src_ref.get(self.get_name(), node.inst.inst_src_ref)
                 )
         elif isinstance(value, m_node.VectorNode):
             if node.width < value.width:
                 self.env.msg.error(
-                    "A counter's %s cannot refrence a value wider than the counter itself."
+                    "A counter's %s cannot reference a value wider than the counter itself."
                     % (self.get_name()),
                     node.inst.property_src_ref.get(self.get_name(), node.inst.inst_src_ref)
                 )
         elif isinstance(value, rdltypes.PropertyReference) and value.width is not None:
             if node.width < value.width:
                 self.env.msg.error(
-                    "A counter's %s cannot refrence a value wider than the counter itself."
+                    "A counter's %s cannot reference a value wider than the counter itself."
                     % (self.get_name()),
                     node.inst.property_src_ref.get(self.get_name(), node.inst.inst_src_ref)
                 )
@@ -1550,7 +1550,7 @@ class Prop_intr_type(PropertyRule):
     @classmethod
     def get_name_cls(cls) -> str:
         # Interrupt modifier type is a "special" hidden property
-        # Intentinally override the property name to something that is impossible
+        # Intentionally override the property name to something that is impossible
         # to define in RDL and collide with: contains a space!
         return "intr type"
 
diff --git a/systemrdl/core/rdlformatcode.py b/systemrdl/core/rdlformatcode.py
index 236ab63..15dd763 100755
--- a/systemrdl/core/rdlformatcode.py
+++ b/systemrdl/core/rdlformatcode.py
@@ -127,12 +127,12 @@ def rdlfc_to_html(text: str, node: Optional[Node]=None, md: Optional['Markdown']
                 is_first_bullet.append(True)
                 list_end_tag.append('</ol>')
             else:
-                # Bad type. re-emit erronous list tag
+                # Bad type. re-emit erroneous list tag
                 text_segs.append(m.group(0))
 
         elif m.lastgroup == 'bullet':
             if len(is_first_bullet) == 0: #pylint: disable=len-as-condition
-                # Not inside a list tag. Re-emit erronous tag
+                # Not inside a list tag. Re-emit erroneous tag
                 text_segs.append("\\[\\*\\]")
             else:
                 if not is_first_bullet[-1]:
@@ -142,7 +142,7 @@ def rdlfc_to_html(text: str, node: Optional[Node]=None, md: Optional['Markdown']
 
         elif m.lastgroup == 'xlist':
             if len(list_end_tag) == 0: #pylint: disable=len-as-condition
-                # Not inside a list tag. Re-emit erronous tag
+                # Not inside a list tag. Re-emit erroneous tag
                 text_segs.append(m.group(0))
             else:
                 if not is_first_bullet[-1]:
diff --git a/systemrdl/node.py b/systemrdl/node.py
index 36352ba..e4ecb11 100644
--- a/systemrdl/node.py
+++ b/systemrdl/node.py
@@ -1069,7 +1069,8 @@ def implements_storage(self) -> bool:
 
 
         .. versionchanged:: 1.22
-            Counter fields always implement storage, regardless of sw/hw access.
+            Counter, interrupt, stickybit, and sticky fields always implement
+            storage, regardless of sw/hw access.
         """
 
         # 9.4.1, Table 12
@@ -1101,6 +1102,14 @@ def implements_storage(self) -> bool:
             # All counters implicitly implement storage
             return True
 
+        if self.get_property('intr'):
+            # All interrupt fields implicitly implement storage
+            return True
+
+        if self.get_property('stickybit') or self.get_property('sticky'):
+            # All sticky fields implicitly implement storage
+            return True
+
         return False
 
     @property
diff --git a/systemrdl/parser/sa_systemrdl.py b/systemrdl/parser/sa_systemrdl.py
index 0bddbab..c6ceb02 100644
--- a/systemrdl/parser/sa_systemrdl.py
+++ b/systemrdl/parser/sa_systemrdl.py
@@ -152,4 +152,4 @@ def _py_parse(stream:InputStream, entry_rule_name:str, sa_err_listener:SA_ErrorL
     entry_rule_func = getattr(parser, entry_rule_name, None)
     if not isinstance(entry_rule_func, types.MethodType):
         raise ValueError("Invalid entry_rule_name '%s'" % entry_rule_name)
-    return entry_rule_func()
\ No newline at end of file
+    return entry_rule_func()
diff --git a/systemrdl/preprocessor/segment_map.py b/systemrdl/preprocessor/segment_map.py
index fb02b51..f5d157a 100644
--- a/systemrdl/preprocessor/segment_map.py
+++ b/systemrdl/preprocessor/segment_map.py
@@ -84,9 +84,9 @@ def translate_offset(self, offset: int, round_up: bool) -> Tuple[int, str]:
     def get_selection(self, start: int, end: int) -> Tuple[int, int, str]:
         """
         Given post-processed start/end character offsets, derives the coordinates
-        witin the original source file.
+        within the original source file.
 
-        If the selection spans two files, the end coordiante is discarded and is
+        If the selection spans two files, the end coordinate is discarded and is
         instead pinned to the start coordinate
         """
         start, path = self.translate_offset(start, round_up=False)
diff --git a/systemrdl/preprocessor/verilog_preprocessor.py b/systemrdl/preprocessor/verilog_preprocessor.py
index f7d6f42..cf78d0c 100644
--- a/systemrdl/preprocessor/verilog_preprocessor.py
+++ b/systemrdl/preprocessor/verilog_preprocessor.py
@@ -733,7 +733,7 @@ def prepare_segments(self, contents: str) -> list:
     def render_macro(self, parent_vpp: VerilogPreprocessor, argv: list, src_ref: SourceRefBase) -> str:
         if len(argv) != len(self.args):
             parent_vpp.env.msg.fatal(
-                "Macro expansion reguires %d arguments. Got %d instead"
+                "Macro expansion requires %d arguments. Got %d instead"
                 % (len(self.args), len(argv)),
                 src_ref
             )
diff --git a/systemrdl/rdltypes.py b/systemrdl/rdltypes.py
index b900d20..3b45633 100644
--- a/systemrdl/rdltypes.py
+++ b/systemrdl/rdltypes.py
@@ -146,7 +146,7 @@ class InterruptType(BuiltinEnum):
 
         The ``nonsticky`` interrupt type is intentionally omitted from this
         enumeration since it is not really a distinct interrupt type. Its use in
-        SystemRDL implies an assignemnt of ``stickybit = false``.
+        SystemRDL implies an assignment of ``stickybit = false``.
     """
     #: Interrupt when asserted and maintained
     level = ()
diff --git a/systemrdl/source_ref.py b/systemrdl/source_ref.py
index 8b9ffe6..aa9cb75 100644
--- a/systemrdl/source_ref.py
+++ b/systemrdl/source_ref.py
@@ -186,7 +186,7 @@ def _resolve_seg_map(self) -> None:
 
 #-------------------------------------------------------------------------------
 def src_ref_from_antlr(antlr_ref: Union[CommonToken, TerminalNodeImpl, ParserRuleContext]) -> 'SourceRefBase':
-    # Normalize to pair of CmmonToken objects
+    # Normalize to pair of CommonToken objects
     if isinstance(antlr_ref, CommonToken):
         token = antlr_ref
         end_token = None