Skip to content
This is the verilog code for the various FPGA in the OpenHPSDR Radios
Verilog Coq Other
Branch: master
Clone or download

Latest commit

JoeMartin-K5SO Tx attenuator fix, major retiming performed
Implemented slower clock speed to be compatible with new attenuator used
in newer radios, completely retimed
design.
Latest commit 2bb4f21 May 5, 2019

Files

Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
Protocol 1 Tx attenuator fix, major retiming performed May 4, 2019
Protocol 2 Add files via upload May 3, 2019
LICENSE Initial commit Mar 25, 2017
README.md Initial commit Mar 25, 2017
TimingClosureFieldGuide.pdf added the K5SO Timing Closure Field Guide document Apr 10, 2017

README.md

OpenHPSDR-Firmware

This is the verilog code for the Varoius FPGA in the OpenHPSDR Radios

You can’t perform that action at this time.