GitHub - TJ178/ece116c_risc-v: Limited instruction set RISC-V processor written in SystemVerilog for ECE116C

Name		Name	Last commit message	Last commit date
db		db
incremental_db		incremental_db
output_files		output_files
questa		questa
simulation/modelsim		simulation/modelsim
22instMem-hex.txt		22instMem-hex.txt
22instMem-sw.txt		22instMem-sw.txt
SystemVerilog2.sv.bak		SystemVerilog2.sv.bak
alu.sv		alu.sv
alu.sv.bak		alu.sv.bak
alu_controller.sv		alu_controller.sv
alu_controller.sv.bak		alu_controller.sv.bak
controller.sv		controller.sv
controller.sv.bak		controller.sv.bak
evaluation-hex.txt		evaluation-hex.txt
evaluation_assembly.txt		evaluation_assembly.txt
immGen.sv		immGen.sv
immGen.sv.bak		immGen.sv.bak
inst_decode.sv		inst_decode.sv
inst_decode.sv.bak		inst_decode.sv.bak
inst_fetch.qpf		inst_fetch.qpf
inst_fetch.qsf		inst_fetch.qsf
inst_fetch.sv		inst_fetch.sv
inst_fetch.sv.bak		inst_fetch.sv.bak
inst_fetch_nativelink_simulation.rpt		inst_fetch_nativelink_simulation.rpt
processor.sv		processor.sv
processor.sv.bak		processor.sv.bak
r-test-assembly.txt		r-test-assembly.txt
r-test-hex.txt		r-test-hex.txt
ram.sv		ram.sv
regFile.sv		regFile.sv
regFile.sv.bak		regFile.sv.bak
rename.sv		rename.sv
rename.sv.bak		rename.sv.bak
rob.sv		rob.sv
rs.sv		rs.sv
rs.sv.bak		rs.sv.bak
test.bin		test.bin
test.hex		test.hex
test.txt		test.txt
test.txt.bak		test.txt.bak
testbench.do		testbench.do
testbench.sv		testbench.sv
testbench.sv.bak		testbench.sv.bak

About

Limited instruction set RISC-V processor written in SystemVerilog for ECE116C

0 stars

1 watching