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Merge commit 'M8260AAABQNLZA30150' into android-msm-3.0-caf

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commit 8ebab31f50cd24f47eb5b83223240b8b331f48a2 2 parents 7020da9 + 60a4c59
@Kali- Kali- authored
Showing with 6,171 additions and 1,911 deletions.
  1. +3 −0  arch/arm/configs/msm7630-perf_defconfig
  2. +3 −0  arch/arm/configs/msm8960_defconfig
  3. +36 −1 arch/arm/mach-msm/Kconfig
  4. +2 −1  arch/arm/mach-msm/Makefile
  5. +23 −17 arch/arm/mach-msm/bam_dmux.c
  6. +86 −0 arch/arm/mach-msm/bms-batterydata-desay.c
  7. +45 −11 arch/arm/mach-msm/bms-batterydata.c
  8. +1 −0  arch/arm/mach-msm/board-8064.c
  9. +9 −5 arch/arm/mach-msm/board-8930-display.c
  10. +1 −0  arch/arm/mach-msm/board-8930.c
  11. +9 −5 arch/arm/mach-msm/board-8960-display.c
  12. +21 −0 arch/arm/mach-msm/board-8960-pmic.c
  13. +14 −4 arch/arm/mach-msm/board-8960.c
  14. +2 −2 arch/arm/mach-msm/board-msm7x27a.c
  15. +15 −6 arch/arm/mach-msm/board-msm8x60.c
  16. +1 −1  arch/arm/mach-msm/board-qrd7627a.c
  17. +26 −11 arch/arm/mach-msm/cache_erp.c
  18. +3 −1 arch/arm/mach-msm/clock-8960.c
  19. +4 −0 arch/arm/mach-msm/clock-8x60.c
  20. +6 −4 arch/arm/mach-msm/cpufreq.c
  21. +9 −1 arch/arm/mach-msm/devices-8960.c
  22. +2 −1  arch/arm/mach-msm/devices-msm7x27.c
  23. +2 −1  arch/arm/mach-msm/devices-msm7x27a.c
  24. +58 −0 arch/arm/mach-msm/devices-msm7x30.c
  25. +1 −0  arch/arm/mach-msm/devices-msm8x60.c
  26. +1 −0  arch/arm/mach-msm/devices.h
  27. +2 −3 arch/arm/mach-msm/idle-v7.S
  28. +1 −0  arch/arm/mach-msm/include/mach/board.h
  29. +3 −2 arch/arm/mach-msm/include/mach/iommu_domains.h
  30. +8 −3 arch/arm/mach-msm/include/mach/memory.h
  31. +4 −1 arch/arm/mach-msm/include/mach/msm_cache_dump.h
  32. +1 −1  arch/arm/mach-msm/include/mach/msm_dcvs_scm.h
  33. +75 −1 arch/arm/mach-msm/include/mach/msm_smd.h
  34. +15 −0 arch/arm/mach-msm/include/mach/msm_smsm.h
  35. +4 −0 arch/arm/mach-msm/include/mach/rpm-regulator.h
  36. +2 −2 arch/arm/mach-msm/iommu_domains.c
  37. +0 −12 arch/arm/mach-msm/lpass-8960.c
  38. +73 −75 arch/arm/mach-msm/memory_topology.c
  39. +1 −1  arch/arm/mach-msm/msm_bus/msm_bus_arb.c
  40. +44 −0 arch/arm/mach-msm/msm_cache_dump.c
  41. +39 −26 arch/arm/mach-msm/msm_dcvs.c
  42. +1 −5 arch/arm/mach-msm/peripheral-loader.c
  43. +27 −0 arch/arm/mach-msm/pil-q6v4.c
  44. +2 −0  arch/arm/mach-msm/pil-q6v4.h
  45. +96 −0 arch/arm/mach-msm/pil-vidc.c
  46. +39 −9 arch/arm/mach-msm/qdsp5v2/audio_lpa.c
  47. +96 −67 arch/arm/mach-msm/qdsp6v2/audio_acdb.c
  48. +165 −117 arch/arm/mach-msm/qdsp6v2/audio_lpa.c
  49. +2 −2 arch/arm/mach-msm/qdsp6v2/audio_lpa.h
  50. +8 −2 arch/arm/mach-msm/qdsp6v2/audio_mp3.c
  51. +107 −60 arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
  52. +6 −7 arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
  53. +30 −6 arch/arm/mach-msm/rpm-regulator.c
  54. +5 −22 arch/arm/mach-msm/rpm.c
  55. +3 −0  arch/arm/mach-msm/scm-pas.h
  56. +489 −110 arch/arm/mach-msm/smd.c
  57. +2 −0  arch/arm/mach-msm/smd_tty.c
  58. +1 −1  arch/arm/mach-msm/wcnss-ssr-8960.c
  59. +1 −4 drivers/char/diag/diagchar.h
  60. +316 −84 drivers/char/diag/diagfwd.c
  61. +3 −2 drivers/char/diag/diagfwd.h
  62. +3 −3 drivers/char/diag/diagfwd_cntl.c
  63. +60 −18 drivers/char/msm_rotator.c
  64. +66 −0 drivers/gpu/ion/ion_iommu_heap.c
  65. +2 −2 drivers/gpu/msm/adreno.c
  66. +1 −1  drivers/gpu/msm/adreno.h
  67. +2 −2 drivers/gpu/msm/kgsl.c
  68. +21 −7 drivers/gpu/msm/kgsl.h
  69. +4 −3 drivers/gpu/msm/kgsl_drm.c
  70. +14 −9 drivers/gpu/msm/kgsl_pwrctrl.c
  71. +1 −0  drivers/gpu/msm/kgsl_pwrctrl.h
  72. +92 −31 drivers/gpu/msm/kgsl_sharedmem.c
  73. +4 −7 drivers/gpu/msm/kgsl_sharedmem.h
  74. +13 −11 drivers/hwmon/pm8xxx-adc.c
  75. +99 −139 drivers/md/dm-crypt.c
  76. +35 −19 drivers/media/radio/radio-iris.c
  77. +39 −16 drivers/media/radio/radio-tavarua.c
  78. +1 −1  drivers/media/video/msm/io/msm_camera_i2c.c
  79. +1 −0  drivers/media/video/msm/wfd/Makefile
  80. +261 −5 drivers/media/video/msm/wfd/enc-subdev.c
  81. +16 −3 drivers/media/video/msm/wfd/vsg-subdev.c
  82. +56 −3 drivers/media/video/msm/wfd/wfd-ioctl.c
  83. +217 −0 drivers/media/video/msm/wfd/wfd-util.c
  84. +60 −1 drivers/media/video/msm/wfd/wfd-util.h
  85. +5 −0 drivers/mfd/pm8921-core.c
  86. +47 −1 drivers/mfd/pm8xxx-pwm.c
  87. +212 −26 drivers/misc/qseecom.c
  88. +2 −1  drivers/mmc/card/mmc_test.c
  89. +65 −22 drivers/mmc/host/msm_sdcc.c
  90. +8 −0 drivers/net/msm_rmnet_bam.c
  91. +603 −136 drivers/power/pm8921-bms.c
  92. +373 −129 drivers/power/pm8921-charger.c
  93. +4 −0 drivers/thermal/msm_thermal.c
  94. +35 −2 drivers/usb/gadget/android.c
  95. +2 −1  drivers/usb/gadget/ci13xxx_msm.c
  96. +3 −15 drivers/usb/gadget/msm72k_udc.c
  97. +1 −0  drivers/usb/gadget/u_data_hsic.c
  98. +1 −1  drivers/usb/gadget/u_sdio.c
  99. +3 −2 drivers/usb/gadget/u_serial.c
  100. +1 −1  drivers/usb/gadget/u_smd.c
  101. +62 −28 drivers/usb/otg/msm_otg.c
  102. +9 −1 drivers/video/msm/external_common.c
  103. +6 −13 drivers/video/msm/hdmi_msm.c
  104. +1 −1  drivers/video/msm/hdmi_msm.h
  105. +0 −2  drivers/video/msm/mdp4_dtv.c
  106. +41 −14 drivers/video/msm/mdp4_overlay.c
  107. +3 −5 drivers/video/msm/mdp4_overlay_atv.c
  108. +3 −6 drivers/video/msm/mdp4_overlay_dsi_video.c
  109. +2 −0  drivers/video/msm/mdp4_overlay_dtv.c
  110. +2 −4 drivers/video/msm/mdp4_overlay_lcdc.c
  111. +11 −7 drivers/video/msm/mdp4_util.c
  112. +4 −2 drivers/video/msm/mdp_dma.c
  113. +9 −8 drivers/video/msm/mdp_dma_dsi_video.c
  114. +8 −3 drivers/video/msm/mdp_dma_lcdc.c
  115. +7 −5 drivers/video/msm/mdp_dma_tv.c
  116. +1 −1  drivers/video/msm/mdp_ppp.c
  117. +90 −25 drivers/video/msm/mdp_ppp_v20.c
  118. +5 −0 drivers/video/msm/msm_dss_io_8960.c
  119. +53 −7 drivers/video/msm/msm_fb.c
  120. +1 −0  drivers/video/msm/msm_fb.h
  121. +2 −1  drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
  122. +1 −1  drivers/video/msm/vidc/1080p/ddl/vcd_ddl_helper.c
  123. +6 −0 drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
  124. +54 −9 drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
  125. +141 −45 drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
  126. +5 −0 drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker_api.h
  127. +11 −0 drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
  128. +2 −0  drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker_api.h
  129. +19 −15 drivers/video/msm/vidc/common/init/vidc_init.c
  130. +3 −0  drivers/video/msm/vidc/common/vcd/vcd.h
  131. +43 −2 drivers/video/msm/vidc/common/vcd/vcd_client_sm.c
  132. +2 −0  drivers/video/msm/vidc/common/vcd/vcd_core.h
  133. +4 −3 drivers/video/msm/vidc/common/vcd/vcd_scheduler.c
  134. +28 −3 drivers/video/msm/vidc/common/vcd/vcd_sub.c
  135. +1 −0  include/linux/ion.h
  136. +58 −13 include/linux/mfd/pm8xxx/pm8921-bms.h
  137. +5 −0 include/linux/mfd/pm8xxx/pm8921-charger.h
  138. +1 −0  include/linux/mfd/pm8xxx/pm8921.h
  139. +8 −0 include/linux/mfd/pm8xxx/pwm.h
  140. +8 −0 include/linux/msm_audio.h
  141. +1 −0  include/linux/msm_kgsl.h
  142. +6 −0 include/linux/qseecom.h
  143. +3 −0  include/linux/videodev2.h
  144. +1 −1  include/media/msm/vcd_api.h
  145. +15 −0 include/media/msm/vcd_property.h
  146. +8 −1 include/media/radio-iris.h
  147. +2 −1  include/media/tavarua.h
  148. +3 −3 include/net/bluetooth/amp.h
  149. +1 −4 include/net/bluetooth/hci_core.h
  150. +1 −1  include/net/bluetooth/l2cap.h
  151. +9 −1 include/sound/q6asm.h
  152. +19 −15 net/bluetooth/amp.c
  153. +8 −41 net/bluetooth/hci_conn.c
  154. +6 −0 net/bluetooth/hci_event.c
  155. +36 −36 net/bluetooth/l2cap_core.c
  156. +5 −9 net/bluetooth/mgmt.c
  157. +709 −227 sound/soc/codecs/wcd9310.c
  158. +1 −0  sound/soc/codecs/wcd9310.h
  159. +2 −2 sound/soc/msm/apq8064.c
  160. +3 −3 sound/soc/msm/msm-pcm-lpa.c
  161. +9 −11 sound/soc/msm/msm-pcm-routing.c
  162. +4 −4 sound/soc/msm/msm8960.c
  163. +1 −3 sound/soc/msm/qdsp6/q6adm.c
  164. +107 −6 sound/soc/msm/qdsp6/q6asm.c
  165. +2 −2 sound/soc/msm/qdsp6/q6voice.c
  166. +1 −1  sound/soc/soc-core.c
  167. +1 −0  sound/soc/soc-dapm.c
View
3  arch/arm/configs/msm7630-perf_defconfig
@@ -295,6 +295,9 @@ CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_MSM7KV2_SOC=y
CONFIG_SND_MVS_SOC=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_SUSPEND=y
View
3  arch/arm/configs/msm8960_defconfig
@@ -64,6 +64,7 @@ CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_PIL_QDSP6V4=y
CONFIG_MSM_PIL_RIVA=y
CONFIG_MSM_PIL_TZAPPS=y
+CONFIG_MSM_PIL_VIDC=y
CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_MODEM_8960=y
CONFIG_MSM_LPASS_8960=y
@@ -85,6 +86,8 @@ CONFIG_MSM_CACHE_ERP=y
CONFIG_MSM_L1_ERR_PANIC=y
CONFIG_MSM_L2_ERP_1BIT_PANIC=y
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
+CONFIG_MSM_CACHE_DUMP=y
+CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
View
37 arch/arm/mach-msm/Kconfig
@@ -1721,6 +1721,12 @@ config MSM_PIL_TZAPPS
used to decrypt data and perform secure operations on the behalf of
the kernel.
+config MSM_PIL_VIDC
+ tristate "Video Core Boot Support"
+ depends on MSM_PIL
+ help
+ Support for authenticating the video core image.
+
config MSM_SCM
bool "Secure Channel Manager (SCM) support"
default n
@@ -2110,10 +2116,23 @@ config MSM_L1_ERR_PANIC
For production builds, you should probably say 'N' here.
+config MSM_L2_ERP_PRINT_ACCESS_ERRORS
+ bool "Report L2 master port slave/decode errors in kernel log"
+ depends on MSM_CACHE_ERP
+ help
+ Master port errors can occur when a memory request is not properly
+ handled by the destination slave. This can occur if the destination
+ register does not exist or is inaccessible due to security
+ restrictions or (in some cases) clock configuration. Enabling this
+ option will cause a backtrace to be printed to the kernel log whenever
+ such an error is encountered. Note that the error is reported as an
+ interrupt rather than as an exception, meaning that the backtrace may
+ have some skid. This option may help with debugging, though production
+ builds should probably say 'N' here.
config MSM_L2_ERP_PORT_PANIC
bool "Panic on L2 master port errors"
- depends on MSM_CACHE_ERP
+ depends on MSM_CACHE_ERP && MSM_L2_ERP_PRINT_ACCESS_ERRORS
help
Master port errors can occur when a memory request is not properly
handled by the destination slave. Enable this option to catch drivers
@@ -2161,4 +2180,20 @@ config MSM_DCVS
algorithm and the algorithm returns a frequency for the core which is
passed to the frequency change driver.
+config MSM_CACHE_DUMP
+ bool "Cache dumping support"
+ help
+ Add infrastructure to dump the L1 and L2 caches to an allocated buffer.
+ This allows for analysis of the caches in case cache corruption is
+ suspected.
+
+config MSM_CACHE_DUMP_ON_PANIC
+ bool "Dump caches on panic"
+ depends on MSM_CACHE_DUMP
+ help
+ By default, the caches are flushed on panic. This means that trying to
+ look at them in a RAM dump will give useless data. Select this if you
+ want to dump the L1 and L2 caches on panic before any flush occurs.
+ If unsure, say N
+
endif
View
3  arch/arm/mach-msm/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_MSM_PIL_QDSP6V3) += pil-q6v3.o
obj-$(CONFIG_MSM_PIL_QDSP6V4) += pil-q6v4.o
obj-$(CONFIG_MSM_PIL_RIVA) += pil-riva.o
obj-$(CONFIG_MSM_PIL_TZAPPS) += pil-tzapps.o
+obj-$(CONFIG_MSM_PIL_VIDC) += pil-vidc.o
obj-$(CONFIG_MSM_PIL_MODEM) += pil-modem.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_ARCH_FSM9XXX) += sirc-fsm9xxx.o
@@ -255,7 +256,7 @@ obj-$(CONFIG_MACH_MSM8960_FLUID) += board-8960-all.o board-8960-regulator.o
obj-$(CONFIG_MACH_MSM8930_CDP) += board-8930-all.o board-8930-regulator.o
obj-$(CONFIG_MACH_MSM8930_MTP) += board-8930-all.o board-8930-regulator.o
obj-$(CONFIG_MACH_MSM8930_FLUID) += board-8930-all.o board-8930-regulator.o
-obj-$(CONFIG_ARCH_MSM8960) += bms-batterydata.o
+obj-$(CONFIG_PM8921_BMS) += bms-batterydata.o bms-batterydata-desay.o
obj-$(CONFIG_MACH_APQ8064_SIM) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_APQ8064_RUMI3) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o board-9615-gpiomux.o board-9615-storage.o
View
40 arch/arm/mach-msm/bam_dmux.c
@@ -190,6 +190,7 @@ static struct workqueue_struct *bam_mux_tx_workqueue;
/* A2 power collaspe */
#define UL_TIMEOUT_DELAY 1000 /* in ms */
+#define ENABLE_DISCONNECT_ACK 0x1
static void toggle_apps_ack(void);
static void reconnect_to_bam(void);
static void disconnect_to_bam(void);
@@ -223,6 +224,7 @@ static DEFINE_SPINLOCK(wakelock_reference_lock);
static int wakelock_reference_count;
static struct delayed_work msm9615_bam_init_work;
static int a2_pc_disabled_wakelock_skipped;
+static int disconnect_ack;
/* End A2 power collaspe */
/* subsystem restart */
@@ -294,9 +296,10 @@ static void bam_dmux_log(const char *fmt, ...)
* W: 1 = Uplink Wait-for-ack
* A: 1 = Uplink ACK received
* #: >=1 On-demand uplink vote
+ * D: 1 = Disconnect ACK active
*/
len += scnprintf(buff, sizeof(buff),
- "<DMUX> %u.%09lu %c%c%c%c %c%c%c%c%d ",
+ "<DMUX> %u.%09lu %c%c%c%c %c%c%c%c%d%c ",
(unsigned)t_now, nanosec_rem,
a2_pc_disabled ? 'D' : 'd',
in_global_reset ? 'R' : 'r',
@@ -306,7 +309,8 @@ static void bam_dmux_log(const char *fmt, ...)
bam_is_connected ? 'U' : 'u',
wait_for_ack ? 'W' : 'w',
ul_wakeup_ack_completion.done ? 'A' : 'a',
- atomic_read(&ul_ondemand_vote)
+ atomic_read(&ul_ondemand_vote),
+ disconnect_ack ? 'D' : 'd'
);
va_start(arg_list, fmt);
@@ -533,6 +537,10 @@ static void handle_bam_mux_cmd(struct work_struct *work)
bam_dmux_log("%s: opening cid %d PC enabled\n", __func__,
rx_hdr->ch_id);
handle_bam_mux_cmd_open(rx_hdr);
+ if (rx_hdr->reserved & ENABLE_DISCONNECT_ACK) {
+ bam_dmux_log("%s: activating disconnect ack\n");
+ disconnect_ack = 1;
+ }
dev_kfree_skb_any(rx_skb);
break;
case BAM_MUX_HDR_CMD_OPEN_NO_A2_PC:
@@ -960,11 +968,13 @@ int msm_bam_dmux_is_ch_full(uint32_t id)
int msm_bam_dmux_is_ch_low(uint32_t id)
{
+ unsigned long flags;
int ret;
if (id >= BAM_DMUX_NUM_CHANNELS)
return -EINVAL;
+ spin_lock_irqsave(&bam_ch[id].lock, flags);
bam_ch[id].use_wm = 1;
ret = bam_ch[id].num_tx_pkts <= LOW_WATERMARK;
DBG("%s: ch %d num tx pkts=%d, LWM=%d\n", __func__,
@@ -973,6 +983,7 @@ int msm_bam_dmux_is_ch_low(uint32_t id)
ret = -ENODEV;
pr_err("%s: port not open: %d\n", __func__, bam_ch[id].status);
}
+ spin_unlock_irqrestore(&bam_ch[id].lock, flags);
return ret;
}
@@ -1236,6 +1247,7 @@ static int debug_log(char *buff, int max, loff_t *ppos)
"\tW: 1 = Uplink Wait-for-ack\n"
"\tA: 1 = Uplink ACK received\n"
"\t#: >=1 On-demand uplink vote\n"
+ "\tD: 1 = Disconnect ACK active\n"
);
buff += i;
}
@@ -1495,21 +1507,11 @@ static void ul_timeout(struct work_struct *work)
static int ssrestart_check(void)
{
- /*
- * if the restart level is RESET_SOC, SSR is not on
- * so the crashed modem will end up crashing the system
- * anyways, so use BUG() to report the error
- * else prepare for the restart event which should
- * happen soon
- */
- DMUX_LOG_KERR("%s: modem timeout\n", __func__);
- if (get_restart_level() <= RESET_SOC) {
- BUG();
- return 0;
- } else {
- in_global_reset = 1;
- return 1;
- }
+ DMUX_LOG_KERR("%s: modem timeout: BAM DMUX disabled\n", __func__);
+ in_global_reset = 1;
+ if (get_restart_level() <= RESET_SOC)
+ DMUX_LOG_KERR("%s: ssrestart not enabled\n", __func__);
+ return 1;
}
static void ul_wakeup(void)
@@ -1656,6 +1658,9 @@ static void disconnect_to_bam(void)
bam_rx_pool_len = 0;
mutex_unlock(&bam_rx_pool_mutexlock);
+ if (disconnect_ack)
+ toggle_apps_ack();
+
verify_tx_queue_is_empty(__func__);
}
@@ -1760,6 +1765,7 @@ static int restart_notifier_cb(struct notifier_block *this,
ul_powerdown_finish();
a2_pc_disabled = 0;
a2_pc_disabled_wakelock_skipped = 0;
+ disconnect_ack = 0;
/* Cleanup Channel States */
for (i = 0; i < BAM_DMUX_NUM_CHANNELS; ++i) {
View
86 arch/arm/mach-msm/bms-batterydata-desay.c
@@ -0,0 +1,86 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/pm8xxx/pm8921-bms.h>
+
+static struct single_row_lut desay_5200_fcc_temp = {
+ .x = {-20, 0, 25, 40},
+ .y = {5690, 5722, 5722, 5727},
+ .cols = 4
+};
+
+static struct single_row_lut desay_5200_fcc_sf = {
+ .x = {0},
+ .y = {100},
+ .cols = 1
+};
+
+static struct pc_temp_ocv_lut desay_5200_pc_temp_ocv = {
+ .rows = 29,
+ .cols = 4,
+ .temp = {-20, 0, 25, 40},
+ .percent = {100, 95, 90, 85, 80, 75, 70, 65, 60, 55,
+ 50, 45, 40, 35, 30, 25, 20, 15, 10, 9, 8,
+ 7, 6, 5, 4, 3, 2, 1, 0
+ },
+ .ocv = {
+ {4185, 4184, 4181, 4178},
+ {4103, 4117, 4120, 4119},
+ {4044, 4067, 4074, 4073},
+ {3987, 4019, 4031, 4030},
+ {3941, 3974, 3992, 3992},
+ {3902, 3936, 3958, 3957},
+ {3866, 3901, 3926, 3926},
+ {3835, 3870, 3891, 3896},
+ {3811, 3842, 3855, 3858},
+ {3792, 3818, 3827, 3827},
+ {3776, 3795, 3806, 3806},
+ {3762, 3778, 3789, 3790},
+ {3748, 3765, 3777, 3777},
+ {3735, 3752, 3767, 3765},
+ {3720, 3739, 3756, 3754},
+ {3704, 3726, 3743, 3736},
+ {3685, 3712, 3723, 3716},
+ {3664, 3697, 3695, 3689},
+ {3623, 3672, 3669, 3664},
+ {3611, 3666, 3666, 3661},
+ {3597, 3659, 3662, 3658},
+ {3579, 3648, 3657, 3653},
+ {3559, 3630, 3644, 3639},
+ {3532, 3600, 3612, 3606},
+ {3497, 3558, 3565, 3559},
+ {3450, 3500, 3504, 3498},
+ {3380, 3417, 3421, 3416},
+ {3265, 3287, 3296, 3293},
+ {3000, 3000, 3000, 3000}
+ },
+};
+
+static struct sf_lut desay_5200_pc_sf = {
+ .rows = 1,
+ .cols = 1,
+ /* row_entries are cycles here */
+ .row_entries = {0},
+ .percent = {100},
+ .sf = {
+ {100}
+ },
+};
+
+struct pm8921_bms_battery_data desay_5200_data = {
+ .fcc = 5200,
+ .fcc_temp_lut = &desay_5200_fcc_temp,
+ .fcc_sf_lut = &desay_5200_fcc_sf,
+ .pc_temp_ocv_lut = &desay_5200_pc_temp_ocv,
+ .pc_sf_lut = &desay_5200_pc_sf,
+ .default_rbatt_mohm = 156,
+};
View
56 arch/arm/mach-msm/bms-batterydata.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -12,22 +12,23 @@
#include <linux/mfd/pm8xxx/pm8921-bms.h>
-static struct single_row_lut fcc_temp = {
+static struct single_row_lut palladium_1500_fcc_temp = {
.x = {-30, -20, -10, 0, 10, 25, 40, 60},
.y = {1103, 1179, 1284, 1330, 1420, 1511, 1541, 1571},
.cols = 8,
};
-static struct single_row_lut fcc_sf = {
+static struct single_row_lut palladium_1500_fcc_sf = {
.x = {100, 200, 300, 400, 500},
.y = {97, 93, 93, 90, 87},
.cols = 5,
};
-static struct pc_sf_lut pc_sf = {
+static struct sf_lut palladium_1500_pc_sf = {
.rows = 10,
.cols = 5,
- .cycles = {100, 200, 300, 400, 500},
+ /* row_entries are chargecycles */
+ .row_entries = {100, 200, 300, 400, 500},
.percent = {100, 90, 80, 70, 60, 50, 40, 30, 20, 10},
.sf = {
{97, 93, 93, 90, 87},
@@ -43,7 +44,37 @@ static struct pc_sf_lut pc_sf = {
},
};
-static struct pc_temp_ocv_lut pc_temp_ocv = {
+static struct sf_lut palladium_1500_rbatt_sf = {
+ .rows = 19,
+ .cols = 5,
+ /* row_entries are temperature */
+ .row_entries = {-20, 0, 20, 40, 65},
+ .percent = {100, 95, 90, 85, 80, 75, 70, 65, 60, 55, 50,
+ 45, 40, 35, 30, 25, 20, 15, 10
+ },
+ .sf = {
+ {645, 301, 100, 80, 69},
+ {616, 290, 100, 79, 69},
+ {586, 279, 100, 78, 68},
+ {564, 270, 100, 78, 68},
+ {546, 262, 100, 78, 68},
+ {537, 256, 100, 79, 68},
+ {536, 253, 100, 79, 69},
+ {552, 258, 100, 81, 71},
+ {618, 284, 100, 80, 72},
+ {643, 290, 100, 77, 68},
+ {673, 294, 100, 77, 68},
+ {720, 296, 100, 77, 69},
+ {769, 294, 100, 76, 68},
+ {821, 288, 100, 74, 67},
+ {892, 284, 100, 74, 61},
+ {1003, 290, 100, 71, 58},
+ {1192, 307, 100, 70, 58},
+ {1579, 345, 100, 68, 57},
+ {1261, 324, 100, 68, 57},
+ }
+};
+static struct pc_temp_ocv_lut palladium_1500_pc_temp_ocv = {
.rows = 29,
.cols = 8,
.temp = {-30, -20, -10, 0, 10, 25, 40, 60},
@@ -84,10 +115,13 @@ static struct pc_temp_ocv_lut pc_temp_ocv = {
},
};
-struct pm8921_bms_battery_data palladium_1500_data = {
+struct pm8921_bms_battery_data palladium_1500_data = {
.fcc = 1500,
- .fcc_temp_lut = &fcc_temp,
- .fcc_sf_lut = &fcc_sf,
- .pc_temp_ocv_lut = &pc_temp_ocv,
- .pc_sf_lut = &pc_sf,
+ .fcc_temp_lut = &palladium_1500_fcc_temp,
+ .fcc_sf_lut = &palladium_1500_fcc_sf,
+ .pc_temp_ocv_lut = &palladium_1500_pc_temp_ocv,
+ .pc_sf_lut = &palladium_1500_pc_sf,
+ .rbatt_sf_lut = &palladium_1500_rbatt_sf,
+ .default_rbatt_mohm = 254,
+ .delta_rbatt_mohm = 60,
};
View
1  arch/arm/mach-msm/board-8064.c
@@ -679,6 +679,7 @@ static struct platform_device *common_devices[] __initdata = {
&apq_cpudai_auxpcm_rx,
&apq_cpudai_auxpcm_tx,
&apq8064_device_cache_erp,
+ &msm_pil_vidc,
};
static struct platform_device *sim_devices[] __initdata = {
View
14 arch/arm/mach-msm/board-8930-display.c
@@ -37,15 +37,19 @@
#endif
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
-#define MSM_FB_PRIM_BUF_SIZE (1376 * 768 * 4 * 3) /* 4 bpp x 3 pages */
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((1376 * 768 * 4), 4096) * 3) /* 4 bpp x 3 pages */
#else
-#define MSM_FB_PRIM_BUF_SIZE (1376 * 768 * 4 * 2) /* 4 bpp x 2 pages */
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((1376 * 768 * 4), 4096) * 2) /* 4 bpp x 2 pages */
#endif
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
-#define MSM_FB_EXT_BUF_SIZE (1920 * 1088 * 2 * 1) /* 2 bpp x 1 page */
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((1920 * 1088 * 2), 4096) * 1) /* 2 bpp x 1 page */
#elif defined(CONFIG_FB_MSM_TVOUT)
-#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((720 * 576 * 2), 4096) * 2) /* 2 bpp x 2 pages */
#else
#define MSM_FB_EXT_BUF_SIZE 0
#endif
@@ -439,7 +443,7 @@ static struct msm_panel_common_pdata mdp_pdata = {
#endif
.mdp_rev = MDP_REV_42,
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
- .mem_hid = ION_CP_MM_HEAP_ID,
+ .mem_hid = BIT(ION_CP_MM_HEAP_ID),
#else
.mem_hid = MEMTYPE_EBI1,
#endif
View
1  arch/arm/mach-msm/board-8930.c
@@ -1764,6 +1764,7 @@ static struct platform_device *common_devices[] __initdata = {
&msm_8960_q6_mss_sw,
&msm_8960_riva,
&msm_pil_tzapps,
+ &msm_pil_vidc,
&msm8960_device_qup_spi_gsbi1,
&msm8960_device_qup_i2c_gsbi3,
&msm8960_device_qup_i2c_gsbi4,
View
14 arch/arm/mach-msm/board-8960-display.c
@@ -28,15 +28,19 @@
#include "board-8960.h"
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
-#define MSM_FB_PRIM_BUF_SIZE (1920 * 1200 * 4 * 3) /* 4 bpp x 3 pages */
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((1920 * 1200 * 4), 4096) * 3) /* 4 bpp x 3 pages */
#else
-#define MSM_FB_PRIM_BUF_SIZE (1920 * 1200 * 4 * 2) /* 4 bpp x 2 pages */
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((1920 * 1200 * 4), 4096) * 2) /* 4 bpp x 2 pages */
#endif
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
-#define MSM_FB_EXT_BUF_SIZE (1920 * 1088 * 2 * 1) /* 2 bpp x 1 page */
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((1920 * 1088 * 2), 4096) * 1) /* 2 bpp x 1 page */
#elif defined(CONFIG_FB_MSM_TVOUT)
-#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((720 * 576 * 2), 4096) * 2) /* 2 bpp x 2 pages */
#else
#define MSM_FB_EXT_BUF_SIZE 0
#endif
@@ -671,7 +675,7 @@ static struct msm_panel_common_pdata mdp_pdata = {
#endif
.mdp_rev = MDP_REV_42,
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
- .mem_hid = ION_CP_MM_HEAP_ID,
+ .mem_hid = BIT(ION_CP_MM_HEAP_ID),
#else
.mem_hid = MEMTYPE_EBI1,
#endif
View
21 arch/arm/mach-msm/board-8960-pmic.c
@@ -419,6 +419,7 @@ static struct pm8921_charger_platform_data pm8921_chg_pdata __devinitdata = {
.warm_bat_voltage = 4100,
.thermal_mitigation = pm8921_therm_mitigation,
.thermal_levels = ARRAY_SIZE(pm8921_therm_mitigation),
+ .rconn_mohm = 18,
};
static struct pm8xxx_misc_platform_data pm8xxx_misc_pdata = {
@@ -426,11 +427,13 @@ static struct pm8xxx_misc_platform_data pm8xxx_misc_pdata = {
};
static struct pm8921_bms_platform_data pm8921_bms_pdata __devinitdata = {
+ .battery_type = BATT_UNKNOWN,
.r_sense = 10,
.i_test = 2500,
.v_failure = 3000,
.calib_delay_ms = 600000,
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
+ .rconn_mohm = 30,
};
#define PM8921_LC_LED_MAX_CURRENT 4 /* I = 4mA */
@@ -547,6 +550,17 @@ static struct pm8xxx_ccadc_platform_data pm8xxx_ccadc_pdata = {
.r_sense = 10,
};
+/**
+ * PM8XXX_PWM_DTEST_CHANNEL_NONE shall be used when no LPG
+ * channel should be in DTEST mode.
+ */
+
+#define PM8XXX_PWM_DTEST_CHANNEL_NONE (-1)
+
+static struct pm8xxx_pwm_platform_data pm8xxx_pwm_pdata = {
+ .dtest_channel = PM8XXX_PWM_DTEST_CHANNEL_NONE,
+};
+
static struct pm8921_platform_data pm8921_platform_data __devinitdata = {
.irq_pdata = &pm8xxx_irq_pdata,
.gpio_pdata = &pm8xxx_gpio_pdata,
@@ -561,6 +575,7 @@ static struct pm8921_platform_data pm8921_platform_data __devinitdata = {
.adc_pdata = &pm8xxx_adc_pdata,
.leds_pdata = &pm8xxx_leds_pdata,
.ccadc_pdata = &pm8xxx_ccadc_pdata,
+ .pwm_pdata = &pm8xxx_pwm_pdata,
};
static struct msm_ssbi_platform_data msm8960_ssbi_pm8921_pdata __devinitdata = {
@@ -585,5 +600,11 @@ void __init msm8960_init_pmic(void)
if (machine_is_msm8960_liquid()) {
pm8921_platform_data.keypad_pdata = &keypad_data_liquid;
pm8921_platform_data.leds_pdata = &pm8xxx_leds_pdata_liquid;
+ pm8921_platform_data.bms_pdata->battery_type = BATT_DESAY;
+ } else if (machine_is_msm8960_mtp()) {
+ pm8921_platform_data.bms_pdata->battery_type = BATT_PALLADIUM;
}
+
+ if (machine_is_msm8960_fluid())
+ pm8921_bms_pdata.rconn_mohm = 20;
}
View
18 arch/arm/mach-msm/board-8960.c
@@ -155,7 +155,7 @@ struct sx150x_platform_data msm8960_sx150x_data[] = {
#define MSM8960_FIXED_AREA_START 0xb0000000
#define MAX_FIXED_AREA_SIZE 0x10000000
-#define MSM_MM_FW_SIZE 0x280000
+#define MSM_MM_FW_SIZE 0x200000
#define MSM8960_FW_START (MSM8960_FIXED_AREA_START - MSM_MM_FW_SIZE)
static unsigned msm_ion_sf_size = MSM_ION_SF_SIZE;
@@ -692,6 +692,7 @@ static void reserve_cache_dump_memory(void)
#ifdef CONFIG_MSM_CACHE_DUMP
unsigned int spare;
unsigned int l1_size;
+ unsigned int l2_size;
unsigned int total;
int ret;
@@ -702,10 +703,18 @@ static void reserve_cache_dump_memory(void)
/* Fall back to something reasonable here */
l1_size = L1_BUFFER_SIZE;
- total = l1_size + L2_BUFFER_SIZE;
+ ret = scm_call(L1C_SERVICE_ID, L2C_BUFFER_GET_SIZE_COMMAND_ID, &spare,
+ sizeof(spare), &l2_size, sizeof(l2_size));
+
+ if (ret)
+ /* Fall back to something reasonable here */
+ l2_size = L2_BUFFER_SIZE;
+
+ total = l1_size + l2_size;
msm8960_reserve_table[MEMTYPE_EBI1].size += total;
msm_cache_dump_pdata.l1_size = l1_size;
+ msm_cache_dump_pdata.l2_size = l2_size;
#endif
}
@@ -854,7 +863,7 @@ static struct tabla_pdata tabla_platform_data = {
.micbias = {
.ldoh_v = TABLA_LDOH_2P85_V,
.cfilt1_mv = 1800,
- .cfilt2_mv = 1800,
+ .cfilt2_mv = 2700,
.cfilt3_mv = 1800,
.bias1_cfilt_sel = TABLA_CFILT1_SEL,
.bias2_cfilt_sel = TABLA_CFILT2_SEL,
@@ -921,7 +930,7 @@ static struct tabla_pdata tabla20_platform_data = {
.micbias = {
.ldoh_v = TABLA_LDOH_2P85_V,
.cfilt1_mv = 1800,
- .cfilt2_mv = 1800,
+ .cfilt2_mv = 2700,
.cfilt3_mv = 1800,
.bias1_cfilt_sel = TABLA_CFILT1_SEL,
.bias2_cfilt_sel = TABLA_CFILT2_SEL,
@@ -2213,6 +2222,7 @@ static struct platform_device *cdp_devices[] __initdata = {
&msm_8960_q6_mss_sw,
&msm_8960_riva,
&msm_pil_tzapps,
+ &msm_pil_vidc,
&msm8960_device_otg,
&msm8960_device_gadget_peripheral,
&msm_device_hsusb_host,
View
4 arch/arm/mach-msm/board-msm7x27a.c
@@ -159,10 +159,10 @@ static struct msm_i2c_platform_data msm_gsbi1_qup_i2c_pdata = {
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
-#define MSM_FB_SIZE 0x260000
+#define MSM_FB_SIZE 0x261000
#define MSM7x25A_MSM_FB_SIZE 0xE1000
#else
-#define MSM_FB_SIZE 0x195000
+#define MSM_FB_SIZE 0x196000
#define MSM7x25A_MSM_FB_SIZE 0x96000
#endif
View
21 arch/arm/mach-msm/board-msm8x60.c
@@ -2619,15 +2619,19 @@ static void __init msm8x60_init_dsps(void)
#endif /* CONFIG_MSM_DSPS */
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
-#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 3) /* 4 bpp x 3 pages */
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((1024 * 600 * 4), 4096) * 3) /* 4 bpp x 3 pages */
#else
-#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 2) /* 4 bpp x 2 pages */
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((1024 * 600 * 4), 4096) * 2) /* 4 bpp x 2 pages */
#endif
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
-#define MSM_FB_EXT_BUF_SIZE (1920 * 1080 * 2 * 1) /* 2 bpp x 1 page */
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((1920 * 1080 * 2), 4096) * 1) /* 2 bpp x 1 page */
#elif defined(CONFIG_FB_MSM_TVOUT)
-#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((720 * 576 * 2), 4096) * 2) /* 2 bpp x 2 pages */
#else
#define MSM_FB_EXT_BUFT_SIZE 0
#endif
@@ -2637,7 +2641,7 @@ static void __init msm8x60_init_dsps(void)
MSM_FB_DSUB_PMEM_ADDER, 4096)
#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
-#define MSM_HDMI_PRIM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
+#define MSM_HDMI_PRIM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
unsigned char hdmi_is_primary = 1;
@@ -2676,7 +2680,12 @@ unsigned char hdmi_is_primary;
#define MSM_ION_MM_FW_SIZE 0x200000 /* (2MB) */
#define MSM_ION_MM_SIZE 0x3600000 /* (54MB) */
#define MSM_ION_MFC_SIZE SZ_8K
+#ifdef CONFIG_FB_MSM_OVERLAY1_WRITEBACK
+#define MSM_ION_WB_SIZE 0xC00000 /* 12MB */
+#else
#define MSM_ION_WB_SIZE 0x600000 /* 6MB */
+#endif
+
#define MSM_ION_QSECOM_SIZE 0x600000 /* (6MB) */
#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE
@@ -9727,7 +9736,7 @@ static struct msm_panel_common_pdata mdp_pdata = {
#endif
.mdp_rev = MDP_REV_41,
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
- .mem_hid = ION_CP_WB_HEAP_ID,
+ .mem_hid = BIT(ION_CP_WB_HEAP_ID),
#else
.mem_hid = MEMTYPE_EBI1,
#endif
View
2  arch/arm/mach-msm/board-qrd7627a.c
@@ -122,7 +122,7 @@ static struct msm_i2c_platform_data msm_gsbi1_qup_i2c_pdata = {
};
#ifdef CONFIG_ARCH_MSM7X27A
-#define MSM_PMEM_MDP_SIZE 0x1DD1000
+#define MSM_PMEM_MDP_SIZE 0x2300000
#define MSM_PMEM_ADSP_SIZE 0x1100000
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
View
37 arch/arm/mach-msm/cache_erp.c
@@ -43,6 +43,8 @@
#define L2ESR_MSE BIT(6)
#define L2ESR_MPLDREXNOK BIT(8)
+#define L2ESR_ACCESS_ERR_MASK 0xFFFC
+
#define L2ESR_CPU_MASK 0x0F
#define L2ESR_CPU_SHIFT 16
@@ -64,6 +66,12 @@
#define ERP_1BIT_ERR(a) do { } while (0)
#endif
+#ifdef CONFIG_MSM_L2_ERP_PRINT_ACCESS_ERRORS
+#define print_access_errors() 1
+#else
+#define print_access_errors() 0
+#endif
+
#ifdef CONFIG_MSM_L2_ERP_2BIT_PANIC
#define ERP_2BIT_ERR(a) panic(a)
#else
@@ -257,6 +265,7 @@ static irqreturn_t msm_l2_erp_irq(int irq, void *dev_id)
int soft_error = 0;
int port_error = 0;
int unrecoverable = 0;
+ int print_alert;
l2esr = get_l2_indirect_reg(L2ESR_IND_ADDR);
l2esynr0 = get_l2_indirect_reg(L2ESYNR0_IND_ADDR);
@@ -264,23 +273,29 @@ static irqreturn_t msm_l2_erp_irq(int irq, void *dev_id)
l2ear0 = get_l2_indirect_reg(L2EAR0_IND_ADDR);
l2ear1 = get_l2_indirect_reg(L2EAR1_IND_ADDR);
- pr_alert("L2 Error detected!\n");
- pr_alert("\tL2ESR = 0x%08x\n", l2esr);
- pr_alert("\tL2ESYNR0 = 0x%08x\n", l2esynr0);
- pr_alert("\tL2ESYNR1 = 0x%08x\n", l2esynr1);
- pr_alert("\tL2EAR0 = 0x%08x\n", l2ear0);
- pr_alert("\tL2EAR1 = 0x%08x\n", l2ear1);
- pr_alert("\tCPU bitmap = 0x%x\n", (l2esr >> L2ESR_CPU_SHIFT) &
- L2ESR_CPU_MASK);
+ print_alert = print_access_errors() || (l2esr & L2ESR_ACCESS_ERR_MASK);
+
+ if (print_alert) {
+ pr_alert("L2 Error detected!\n");
+ pr_alert("\tL2ESR = 0x%08x\n", l2esr);
+ pr_alert("\tL2ESYNR0 = 0x%08x\n", l2esynr0);
+ pr_alert("\tL2ESYNR1 = 0x%08x\n", l2esynr1);
+ pr_alert("\tL2EAR0 = 0x%08x\n", l2ear0);
+ pr_alert("\tL2EAR1 = 0x%08x\n", l2ear1);
+ pr_alert("\tCPU bitmap = 0x%x\n", (l2esr >> L2ESR_CPU_SHIFT) &
+ L2ESR_CPU_MASK);
+ }
if (l2esr & L2ESR_MPDCD) {
- pr_alert("L2 master port decode error\n");
+ if (print_alert)
+ pr_alert("L2 master port decode error\n");
port_error++;
msm_l2_erp_stats.mpdcd++;
}
if (l2esr & L2ESR_MPSLV) {
- pr_alert("L2 master port slave error\n");
+ if (print_alert)
+ pr_alert("L2 master port slave error\n");
port_error++;
msm_l2_erp_stats.mpslv++;
}
@@ -323,7 +338,7 @@ static irqreturn_t msm_l2_erp_irq(int irq, void *dev_id)
msm_l2_erp_stats.mplxrexnok++;
}
- if (port_error)
+ if (port_error && print_alert)
ERP_PORT_ERR("L2 master port error detected");
if (soft_error && !unrecoverable)
View
4 arch/arm/mach-msm/clock-8960.c
@@ -4500,6 +4500,7 @@ static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_tzcom_clk, &dfab_clk.c);
+static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
/*
@@ -5132,6 +5133,7 @@ static struct clk_lookup msm_clocks_8064[] = {
CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
CLK_DUMMY("bus_clk", DFAB_SCM_CLK, "scm", 0),
CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
+ CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
@@ -5393,7 +5395,7 @@ static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
-
+ CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
View
4 arch/arm/mach-msm/clock-8x60.c
@@ -3216,6 +3216,7 @@ static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c);
+static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c);
static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
static DEFINE_CLK_VOTER(ebi1_adm0_clk, &ebi1_clk.c);
@@ -3841,8 +3842,10 @@ static struct clk_lookup msm_clocks_8x60[] = {
CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
+ CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
+ CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "msm_iommu.7"),
@@ -3865,6 +3868,7 @@ static struct clk_lookup msm_clocks_8x60[] = {
CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
+ CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
CLK_LOOKUP("mem_clk", ebi1_adm0_clk.c, "msm_dmov.0"),
CLK_LOOKUP("mem_clk", ebi1_adm1_clk.c, "msm_dmov.1"),
View
10 arch/arm/mach-msm/cpufreq.c
@@ -96,13 +96,13 @@ static int msm_cpufreq_target(struct cpufreq_policy *policy,
struct cpufreq_work_struct *cpu_work = NULL;
cpumask_var_t mask;
- if (!alloc_cpumask_var(&mask, GFP_KERNEL))
- return -ENOMEM;
-
if (!cpu_active(policy->cpu)) {
pr_info("cpufreq: cpu %d is not active.\n", policy->cpu);
return -ENODEV;
}
+
+ if (!alloc_cpumask_var(&mask, GFP_KERNEL))
+ return -ENOMEM;
#endif
mutex_lock(&per_cpu(cpufreq_suspend, policy->cpu).suspend_mutex);
@@ -146,13 +146,15 @@ static int msm_cpufreq_target(struct cpufreq_policy *policy,
wait_for_completion(&cpu_work->complete);
}
- free_cpumask_var(mask);
ret = cpu_work->status;
#else
ret = set_cpu_freq(policy, table[index].frequency);
#endif
done:
+#ifdef CONFIG_SMP
+ free_cpumask_var(mask);
+#endif
mutex_unlock(&per_cpu(cpufreq_suspend, policy->cpu).suspend_mutex);
return ret;
}
View
10 arch/arm/mach-msm/devices-8960.c
@@ -568,6 +568,7 @@ struct msm_vidc_platform_data vidc_platform_data = {
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
.memtype = ION_CP_MM_HEAP_ID,
.enable_ion = 1,
+ .cp_enabled = 1,
#else
.memtype = MEMTYPE_EBI1,
.enable_ion = 0,
@@ -883,6 +884,8 @@ static struct pil_q6v4_pdata msm_8960_q6_mss_fw_data = {
.aclk_reg = SFAB_MSS_Q6_FW_ACLK_CTL,
.jtag_clk_reg = MSS_Q6FW_JTAG_CLK_CTL,
.xo_id = MSM_XO_CXO,
+ .xo1_id = MSM_XO_TCXO_A0,
+ .xo2_id = MSM_XO_TCXO_A1,
.name = "modem_fw",
.depends = "q6",
.pas_id = PAS_MODEM_FW,
@@ -955,6 +958,11 @@ struct platform_device msm_pil_tzapps = {
.id = -1,
};
+struct platform_device msm_pil_vidc = {
+ .name = "pil_vidc",
+ .id = -1,
+};
+
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
@@ -2382,7 +2390,7 @@ static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.init_level = 0,
.num_levels = 5,
.set_grp_async = NULL,
- .idle_timeout = HZ/20,
+ .idle_timeout = HZ/12,
.nap_allowed = true,
.clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE,
#ifdef CONFIG_MSM_BUS_SCALING
View
3  arch/arm/mach-msm/devices-msm7x27.c
@@ -822,7 +822,8 @@ static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.init_level = 0,
.num_levels = 1,
.set_grp_async = NULL,
- .idle_timeout = HZ/5,
+ .idle_timeout = HZ,
+ .strtstp_sleepwake = true,
.clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
View
3  arch/arm/mach-msm/devices-msm7x27a.c
@@ -673,7 +673,8 @@ static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.init_level = 0,
.num_levels = 3,
.set_grp_async = set_grp_xbar_async,
- .idle_timeout = HZ/5,
+ .idle_timeout = HZ,
+ .strtstp_sleepwake = true,
.nap_allowed = false,
.clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM,
};
View
58 arch/arm/mach-msm/devices-msm7x30.c
@@ -581,9 +581,67 @@ struct platform_device msm_device_nand = {
},
};
+static struct resource smd_resource[] = {
+ {
+ .name = "a9_m2a_0",
+ .start = INT_A9_M2A_0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "a9_m2a_5",
+ .start = INT_A9_M2A_5,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "adsp_a11_smsm",
+ .start = INT_ADSP_A11,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct smd_subsystem_config smd_config_list[] = {
+ {
+ .irq_config_id = SMD_MODEM,
+ .subsys_name = "modem",
+ .edge = SMD_APPS_MODEM,
+
+ .smd_int.irq_name = "a9_m2a_0",
+ .smd_int.flags = IRQF_TRIGGER_RISING,
+ .smd_int.irq_id = -1,
+ .smd_int.device_name = "smd_dev",
+ .smd_int.dev_id = 0,
+
+ .smd_int.out_bit_pos = 1 << 0,
+ .smd_int.out_base = (void __iomem *)MSM_GCC_BASE,
+ .smd_int.out_offset = 0x8,
+
+ .smsm_int.irq_name = "a9_m2a_5",
+ .smsm_int.flags = IRQF_TRIGGER_RISING,
+ .smsm_int.irq_id = -1,
+ .smsm_int.device_name = "smd_dev",
+ .smsm_int.dev_id = 0,
+
+ .smsm_int.out_bit_pos = 1 << 5,
+ .smsm_int.out_base = (void __iomem *)MSM_GCC_BASE,
+ .smsm_int.out_offset = 0x8,
+
+ }
+};
+
+static struct smd_platform smd_platform_data = {
+ .num_ss_configs = ARRAY_SIZE(smd_config_list),
+ .smd_ss_configs = smd_config_list,
+};
+
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
+ .resource = smd_resource,
+ .num_resources = ARRAY_SIZE(smd_resource),
+ .dev = {
+ .platform_data = &smd_platform_data,
+ }
+
};
static struct resource msm_dmov_resource[] = {
View
1  arch/arm/mach-msm/devices-msm8x60.c
@@ -2407,6 +2407,7 @@ struct msm_vidc_platform_data vidc_platform_data = {
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
.memtype = ION_CP_MM_HEAP_ID,
.enable_ion = 1,
+ .cp_enabled = 0,
#else
.memtype = MEMTYPE_SMI_KERNEL,
.enable_ion = 0,
View
1  arch/arm/mach-msm/devices.h
@@ -190,6 +190,7 @@ extern struct platform_device msm_cpudai_incall_record_tx;
extern struct platform_device msm_pil_q6v3;
extern struct platform_device msm_pil_modem;
extern struct platform_device msm_pil_tzapps;
+extern struct platform_device msm_pil_vidc;
extern struct platform_device msm_8960_q6_lpass;
extern struct platform_device msm_8960_q6_mss_fw;
extern struct platform_device msm_8960_q6_mss_sw;
View
5 arch/arm/mach-msm/idle-v7.S
@@ -217,12 +217,11 @@ msm_pm_pa_to_va:
biceq r3, r3, #0x400
mcreq p15, 7, r3, c15, c0, 2
#endif
- stmfd sp!, {lr}
- bl v7_flush_kern_cache_all
#ifdef CONFIG_MSM_JTAG
+ stmfd sp!, {lr}
bl msm_jtag_restore_state
-#endif
ldmfd sp!, {lr}
+#endif
mov r0, #1
bx lr
nop
View
1  arch/arm/mach-msm/include/mach/board.h
@@ -448,6 +448,7 @@ struct msm_vidc_platform_data {
u32 enable_ion;
int disable_dmx;
int disable_fullhd;
+ u32 cp_enabled;
#ifdef CONFIG_MSM_BUS_SCALING
struct msm_bus_scale_pdata *vidc_bus_client_pdata;
#endif
View
5 arch/arm/mach-msm/include/mach/iommu_domains.h
@@ -20,8 +20,9 @@ enum {
enum {
VIDEO_FIRMWARE_POOL,
- LOW_256MB_POOL,
- HIGH_POOL,
+ VIDEO_MAIN_POOL,
+ VIDEO_MFC_POOL,
+ GEN_POOL,
};
View
11 arch/arm/mach-msm/include/mach/memory.h
@@ -1,7 +1,7 @@
/* arch/arm/mach-msm/include/mach/memory.h
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -23,8 +23,13 @@
#define MAX_PHYSMEM_BITS 32
#define SECTION_SIZE_BITS 28
-/* Maximum number of Memory Regions */
-#define MAX_NR_REGIONS 4
+/* Maximum number of Memory Regions
+* The largest system can have 4 memory banks, each divided into 8 regions
+*/
+#define MAX_NR_REGIONS 32
+
+/* The number of regions each memory bank is divided into */
+#define NR_REGIONS_PER_BANK 8
/* Certain configurations of MSM7x30 have multiple memory banks.
* One or more of these banks can contain holes in the memory map as well.
View
5 arch/arm/mach-msm/include/mach/msm_cache_dump.h
@@ -58,12 +58,15 @@ struct msm_cache_dump_platform_data {
};
#define L1_BUFFER_SIZE SZ_1M
-#define L2_BUFFER_SIZE (sizeof(struct l2_cache_dump))
+#define L2_BUFFER_SIZE SZ_4M
#define CACHE_BUFFER_DUMP_SIZE (L1_BUFFER_SIZE + L2_BUFFER_SIZE)
#define L1C_SERVICE_ID 3
#define L1C_BUFFER_SET_COMMAND_ID 4
+#define CACHE_BUFFER_DUMP_COMMAND_ID 5
#define L1C_BUFFER_GET_SIZE_COMMAND_ID 6
+#define L2C_BUFFER_SET_COMMAND_ID 7
+#define L2C_BUFFER_GET_SIZE_COMMAND_ID 8
#endif
View
2  arch/arm/mach-msm/include/mach/msm_dcvs_scm.h
@@ -115,7 +115,7 @@ extern int msm_dcvs_scm_set_algo_params(uint32_t core_id,
* @param0: Did the core iowait
* @param1: unused
* @ret0: New clock frequency for the core in KHz
- * @ret1: unused
+ * @ret1: New QoS timer value for the core in usec
* MSM_DCVS_SCM_QOS_TIMER_EXPIRED
* @param0: unused
* @param1: unused
View
76 arch/arm/mach-msm/include/mach/msm_smd.h
@@ -1,7 +1,7 @@
/* linux/include/asm-arm/arch-msm/msm_smd.h
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -18,6 +18,9 @@
#ifndef __ASM_ARCH_MSM_SMD_H
#define __ASM_ARCH_MSM_SMD_H
+#include <linux/io.h>
+#include <mach/msm_smsm.h>
+
typedef struct smd_channel smd_channel_t;
#define SMD_MAX_CH_NAME_LEN 20 /* includes null char at end */
@@ -28,6 +31,24 @@ typedef struct smd_channel smd_channel_t;
#define SMD_EVENT_STATUS 4
#define SMD_EVENT_REOPEN_READY 5
+/*
+ * SMD Processor ID's.
+ *
+ * For all processors that have both SMSM and SMD clients,
+ * the SMSM Processor ID and the SMD Processor ID will
+ * be the same. In cases where a processor only supports
+ * SMD, the entry will only exist in this enum.
+ */
+enum {
+ SMD_APPS = SMSM_APPS,
+ SMD_MODEM = SMSM_MODEM,
+ SMD_Q6 = SMSM_Q6,
+ SMD_WCNSS = SMSM_WCNSS,
+ SMD_DSPS = SMSM_DSPS,
+ SMD_MODEM_Q6_FW,
+ NUM_SMD_SUBSYSTEMS,
+};
+
enum {
SMD_APPS_MODEM = 0,
SMD_APPS_QDSP,
@@ -49,6 +70,59 @@ enum {
};
+/*
+ * SMD IRQ Configuration
+ *
+ * Used to initialize IRQ configurations from platform data
+ *
+ * @irq_name: irq_name to query platform data
+ * @irq_id: initialized to -1 in platform data, stores actual irq id on
+ * successful registration
+ * @out_base: if not null then settings used for outgoing interrupt
+ * initialied from platform data
+ */
+
+struct smd_irq_config {
+ /* incoming interrupt config */
+ const char *irq_name;
+ unsigned long flags;
+ int irq_id;
+ const char *device_name;
+ const void *dev_id;
+
+ /* outgoing interrupt config */
+ uint32_t out_bit_pos;
+ void __iomem *out_base;
+ uint32_t out_offset;
+};
+
+/*
+ * SMD subsystem configurations
+ *
+ * SMD subsystems configurations for platform data. This contains the
+ * M2A and A2M interrupt configurations for both SMD and SMSM per
+ * subsystem.
+ *
+ * @subsys_name: name of subsystem passed to PIL
+ * @irq_config_id: unique id for each subsystem
+ * @edge: maps to actual remote subsystem edge
+ *
+ */
+struct smd_subsystem_config {
+ unsigned irq_config_id;
+ const char *subsys_name;
+ int edge;
+
+ struct smd_irq_config smd_int;
+ struct smd_irq_config smsm_int;
+
+};
+
+struct smd_platform {
+ uint32_t num_ss_configs;
+ struct smd_subsystem_config *smd_ss_configs;
+};
+
#ifdef CONFIG_MSM_SMD
/* warning: notify() may be called before open returns */
int smd_open(const char *name, smd_channel_t **ch, void *priv,
View
15 arch/arm/mach-msm/include/mach/msm_smsm.h
@@ -99,6 +99,21 @@ void *smem_alloc2(unsigned id, unsigned size_in);
void *smem_get_entry(unsigned id, unsigned *size);
int smsm_change_state(uint32_t smsm_entry,
uint32_t clear_mask, uint32_t set_mask);
+
+/*
+ * Changes the global interrupt mask. The set and clear masks are re-applied
+ * every time the global interrupt mask is updated for callback registration
+ * and de-registration.
+ *
+ * The clear mask is applied first, so if a bit is set to 1 in both the clear
+ * mask and the set mask, the result will be that the interrupt is set.
+ *
+ * @smsm_entry SMSM entry to change
+ * @clear_mask 1 = clear bit, 0 = no-op
+ * @set_mask 1 = set bit, 0 = no-op
+ *
+ * @returns 0 for success, < 0 for error
+ */
int smsm_change_intr_mask(uint32_t smsm_entry,
uint32_t clear_mask, uint32_t set_mask);
int smsm_get_intr_mask(uint32_t smsm_entry, uint32_t *intr_mask);
View
4 arch/arm/mach-msm/include/mach/rpm-regulator.h
@@ -161,6 +161,10 @@ enum rpm_vreg_voter {
*
* Consumers can vote to disable a regulator with this function by passing
* min_uV = 0 and max_uV = 0.
+ *
+ * Voltage switch type regulators may be controlled via rpm_vreg_set_voltage
+ * as well. For this type of regulator, max_uV > 0 is treated as an enable
+ * request and max_uV == 0 is treated as a disable request.
*/
int rpm_vreg_set_voltage(int vreg_id, enum rpm_vreg_voter voter, int min_uV,
int max_uV, int sleep_also);
View
4 arch/arm/mach-msm/iommu_domains.c
@@ -216,11 +216,11 @@ unsigned long msm_subsystem_get_partition_no(int subsys_id)
case MSM_SUBSYSTEM_VIDEO_FWARE:
return VIDEO_FIRMWARE_POOL;
case MSM_SUBSYSTEM_VIDEO:
- return LOW_256MB_POOL;
+ return VIDEO_MAIN_POOL;
case MSM_SUBSYSTEM_CAMERA:
case MSM_SUBSYSTEM_DISPLAY:
case MSM_SUBSYSTEM_ROTATOR:
- return HIGH_POOL;
+ return GEN_POOL;
default:
return 0xFFFFFFFF;
}
View
12 arch/arm/mach-msm/lpass-8960.c
@@ -31,12 +31,10 @@
#define SCM_Q6_NMI_CMD 0x1
#define MODULE_NAME "lpass_8960"
-#define Q6SS_SOFT_INTR_WAKEUP 0x28800024
/* Subsystem restart: QDSP6 data, functions */
static void lpass_fatal_fn(struct work_struct *);
static DECLARE_WORK(lpass_fatal_work, lpass_fatal_fn);
-void __iomem *q6_wakeup_intr;
struct lpass_ssr {
void *lpass_ramdump_dev;
} lpass_ssr;
@@ -96,11 +94,6 @@ static void send_q6_nmi(void)
scm_call(SCM_SVC_UTIL, SCM_Q6_NMI_CMD,
&cmd, sizeof(cmd), NULL, 0);
- /* Wakeup the Q6 */
- if (q6_wakeup_intr)
- writel_relaxed(0x01, q6_wakeup_intr);
- mb();
-
/* Q6 requires worstcase 100ms to dump caches etc.*/
mdelay(100);
pr_debug("%s: Q6 NMI was sent.\n", __func__);
@@ -190,9 +183,6 @@ static int __init lpass_fatal_init(void)
__func__, ret);
goto out;
}
- q6_wakeup_intr = ioremap_nocache(Q6SS_SOFT_INTR_WAKEUP, 8);
- if (!q6_wakeup_intr)
- pr_err("%s: Unable to request q6 wakeup interrupt\n", __func__);
lpass_ssr_8960.lpass_ramdump_dev = create_ramdump_device("lpass");
@@ -208,7 +198,6 @@ static int __init lpass_fatal_init(void)
ret = PTR_ERR(ssr_notif_hdle);
pr_err("%s: subsys_register_notifier for Riva: err = %d\n",
__func__, ret);
- iounmap(q6_wakeup_intr);
free_irq(LPASS_Q6SS_WDOG_EXPIRED, NULL);
goto out;
}
@@ -221,7 +210,6 @@ static int __init lpass_fatal_init(void)
static void __exit lpass_fatal_exit(void)
{
subsys_notif_unregister_notifier(ssr_notif_hdle, &rnb);
- iounmap(q6_wakeup_intr);
free_irq(LPASS_Q6SS_WDOG_EXPIRED, NULL);
}
View
148 arch/arm/mach-msm/memory_topology.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -31,11 +31,11 @@ static struct mem_region_t {
/* reserved for future use */
u64 num_partitions;
int state;
- int mask;
- struct mutex state_mutex;
} mem_regions[MAX_NR_REGIONS];
+static struct mutex mem_regions_mutex;
static unsigned int nr_mem_regions;
+static int mem_regions_mask;
enum {
STATE_POWER_DOWN = 0x0,
@@ -43,14 +43,6 @@ enum {
STATE_DEFAULT = STATE_ACTIVE
};
-enum {
- MEM_NO_CHANGE = 0x0,
- MEM_DEEP_POWER_DOWN,
- MEM_SELF_REFRESH,
-};
-
-static unsigned int dmm_mode;
-
static int default_mask = ~0x0;
/* Return the number of chipselects populated with a memory bank */
@@ -112,50 +104,55 @@ static int rpm_change_memory_state(int retention_mask,
}
}
-static int switch_memory_state(int id, int new_state)
+static int switch_memory_state(int mask, int new_state, int start_region,
+ int end_region)
{
- int mask = 0;
- int power_down_masks[MAX_NR_REGIONS] = { 0xFFFFFF00, 0xFFFF00FF,
- 0xFF00FFFF, 0x00FFFFFF };
- int self_refresh_masks[MAX_NR_REGIONS] = { 0xFFFFFFF0, 0xFFFFFF0F,
- 0xFFFFF0FF, 0xFFFF0FFF };
- mutex_lock(&mem_regions[id].state_mutex);
-
- if (new_state == mem_regions[id].state)
- goto no_change;
+ int final_mask = 0;
+ int i;
+
+ mutex_lock(&mem_regions_mutex);
- pr_info("request memory %d state switch (%d->%d) mode %d\n", id,
- mem_regions[id].state, new_state, dmm_mode);
- if (new_state == STATE_POWER_DOWN) {
- if (dmm_mode == MEM_DEEP_POWER_DOWN)
- mask = mem_regions[id].mask & power_down_masks[id];
- else
- mask = mem_regions[id].mask & self_refresh_masks[id];
- } else if (new_state == STATE_ACTIVE) {
- if (dmm_mode == MEM_DEEP_POWER_DOWN)
- mask = mem_regions[id].mask | (~power_down_masks[id]);
- else
- mask = mem_regions[id].mask | (~self_refresh_masks[id]);
+ for (i = start_region; i <= end_region; i++) {
+ if (new_state == mem_regions[i].state)
+ goto no_change;
+ /* All region states must be the same to change them */
+ if (mem_regions[i].state != mem_regions[start_region].state)
+ goto no_change;
}
- if (rpm_change_memory_state(mask, mask) == 0) {
- mem_regions[id].state = new_state;
- mem_regions[id].mask = mask;
- pr_info("completed memory %d state switch to %d mode %d\n",
- id, new_state, dmm_mode);
- mutex_unlock(&mem_regions[id].state_mutex);
+ if (new_state == STATE_POWER_DOWN)
+ final_mask = mem_regions_mask & mask;
+ else if (new_state == STATE_ACTIVE)
+ final_mask = mem_regions_mask | ~mask;
+ else
+ goto no_change;
+
+ pr_info("request memory %d to %d state switch (%d->%d)\n",
+ start_region, end_region, mem_regions[start_region].state,
+ new_state);
+ if (rpm_change_memory_state(final_mask, final_mask) == 0) {
+ for (i = start_region; i <= end_region; i++)
+ mem_regions[i].state = new_state;
+ mem_regions_mask = final_mask;
+
+ pr_info("completed memory %d to %d state switch to %d\n",
+ start_region, end_region, new_state);
+ mutex_unlock(&mem_regions_mutex);
return 0;
}
- pr_err("failed memory %d state switch (%d->%d) mode %d\n", id,
- mem_regions[id].state, new_state, dmm_mode);
+ pr_err("failed memory %d to %d state switch (%d->%d)\n",
+ start_region, end_region, mem_regions[start_region].state,
+ new_state);
+
no_change:
- mutex_unlock(&mem_regions[id].state_mutex);
+ mutex_unlock(&mem_regions_mutex);
return -EINVAL;
}
#else
-static int switch_memory_state(int id, int new_state)
+static int switch_memory_state(int mask, int new_state, int start_region,
+ int end_region)
{
return -EINVAL;
}
@@ -166,29 +163,34 @@ static int switch_memory_state(int id, int new_state)
*/
int soc_change_memory_power(u64 start, u64 size, int change)
{
-
int i = 0;
- int match = 0;
+ int mask = default_mask;
+ u64 end = start + size;
+ int start_region = 0;
+ int end_region = 0;
- /* Find the memory region starting just below start */
+ if (change != STATE_ACTIVE && change != STATE_POWER_DOWN) {
+ pr_info("requested state transition invalid\n");
+ return 0;
+ }
+ /* Find the memory regions that fall within the range */
for (i = 0; i < nr_mem_regions; i++) {
if (mem_regions[i].start <= start &&
- mem_regions[i].start >= mem_regions[match].start) {
- match = i;
+ mem_regions[i].start >=
+ mem_regions[start_region].start) {
+ start_region = i;
+ }
+ if (end <= mem_regions[i].start + mem_regions[i].size) {
+ end_region = i;
+ break;
}
}
- if (start + size > mem_regions[match].start + mem_regions[match].size) {
- pr_info("passed size exceeds size of memory bank\n");
- return 0;
- }
+ /* Set the bitmask for each region in the range */
+ for (i = start_region; i <= end_region; i++)
+ mask &= ~(0x1 << i);
- if (change != STATE_ACTIVE && change != STATE_POWER_DOWN) {
- pr_info("requested state transition invalid\n");
- return 0;
- }
-
- if (!switch_memory_state(match, change))
+ if (!switch_memory_state(mask, change, start_region, end_region))
return size;
else
return 0;
@@ -213,9 +215,10 @@ unsigned int get_memory_bank_start(unsigned int id)
int __init meminfo_init(unsigned int type, unsigned int min_bank_size)
{
- unsigned int i;
+ unsigned int i, j;
unsigned long bank_size;
unsigned long bank_start;
+ unsigned long region_size;
struct smem_ram_ptable *ram_ptable;
/* physical memory banks */
unsigned int nr_mem_banks = 0;
@@ -230,40 +233,35 @@ int __init meminfo_init(unsigned int type, unsigned int min_bank_size)
return -EINVAL;
}
- /* Determine power control mode based on the hw version */
- /* This check will be removed when PASR is fully supported */
- if (cpu_is_msm8960() &&
- SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2)
- dmm_mode = MEM_DEEP_POWER_DOWN;
- else
- dmm_mode = MEM_SELF_REFRESH;
-
pr_info("meminfo_init: smem ram ptable found: ver: %d len: %d\n",
ram_ptable->version, ram_ptable->len);
for (i = 0; i < ram_ptable->len; i++) {
+ /* A bank is valid only if is greater than min_bank_size. If
+ * non-valid memory (e.g. modem memory) became greater than
+ * min_bank_size, there is currently no way to differentiate.
+ */
if (ram_ptable->parts[i].type == type &&
ram_ptable->parts[i].size >= min_bank_size) {
bank_start = ram_ptable->parts[i].start;
bank_size = ram_ptable->parts[i].size;
- /* Divide into logical memory regions of same size */
- while (bank_size) {
+ region_size = bank_size / NR_REGIONS_PER_BANK;
+
+ for (j = 0; j < NR_REGIONS_PER_BANK; j++) {
mem_regions[nr_mem_regions].start =
bank_start;
mem_regions[nr_mem_regions].size =
- MIN_MEMORY_BLOCK_SIZE;
- mutex_init(&mem_regions[nr_mem_regions]
- .state_mutex);
+ region_size;
mem_regions[nr_mem_regions].state =
STATE_DEFAULT;
- mem_regions[nr_mem_regions].mask = default_mask;
- bank_start += MIN_MEMORY_BLOCK_SIZE;
- bank_size -= MIN_MEMORY_BLOCK_SIZE;
+ bank_start += region_size;
nr_mem_regions++;
}
nr_mem_banks++;
}
}
+ mutex_init(&mem_regions_mutex);
+ mem_regions_mask = default_mask;
pr_info("Found %d memory banks grouped into %d memory regions\n",
nr_mem_banks, nr_mem_regions);
return 0;
View
2  arch/arm/mach-msm/msm_bus/msm_bus_arb.c
@@ -192,7 +192,7 @@ static int getpath(int src, int dest)
list_for_each_entry(fabnodeinfo, gateways, list) {
/* see if the destination is at a connected fabric */
if (_dst == (fabnodeinfo->info->node_info->priv_id /
- FABRIC_ID_KEY) && !(fabdev->visited)) {
+ FABRIC_ID_KEY)) {
/* Found the fab on which the device exists */
info = fabnodeinfo->info;
trynextgw = false;
View
44 arch/arm/mach-msm/msm_cache_dump.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/memory_alloc.h>
+#include <linux/notifier.h>
#include <mach/scm.h>
#include <mach/msm_cache_dump.h>
#include <mach/memory.h>
@@ -38,6 +39,25 @@ static unsigned long msm_cache_dump_addr;
static struct l1_cache_dump __used *l1_dump;
static struct l2_cache_dump __used *l2_dump;
+static int msm_cache_dump_panic(struct notifier_block *this,
+ unsigned long event, void *ptr)
+{
+#ifdef CONFIG_MSM_CACHE_DUMP_ON_PANIC
+ scm_call_atomic1(L1C_SERVICE_ID, CACHE_BUFFER_DUMP_COMMAND_ID, 2);
+ scm_call_atomic1(L1C_SERVICE_ID, CACHE_BUFFER_DUMP_COMMAND_ID, 1);
+#endif
+ return 0;
+}
+
+static struct notifier_block msm_cache_dump_blk = {
+ .notifier_call = msm_cache_dump_panic,
+ /*
+ * higher priority to ensure this runs before another panic handler
+ * flushes the caches.
+ */
+ .priority = 1,
+};
+
static int msm_cache_dump_probe(struct platform_device *pdev)
{
struct msm_cache_dump_platform_data *d = pdev->dev.platform_data;
@@ -46,7 +66,9 @@ static int msm_cache_dump_probe(struct platform_device *pdev)
unsigned long buf;
unsigned long size;
} l1_cache_data;
+#ifndef CONFIG_MSM_CACHE_DUMP_ON_PANIC
unsigned int *imem_loc;
+#endif
void *temp;
unsigned long total_size = d->l1_size + d->l2_size;
@@ -72,14 +94,36 @@ static int msm_cache_dump_probe(struct platform_device *pdev)
pr_err("%s: could not register L1 buffer ret = %d.\n",
__func__, ret);
+#if defined(CONFIG_MSM_CACHE_DUMP_ON_PANIC)
+ l1_cache_data.buf = msm_cache_dump_addr + d->l1_size;
+ l1_cache_data.size = d->l2_size;
+
+ ret = scm_call(L1C_SERVICE_ID, L2C_BUFFER_SET_COMMAND_ID,
+ &l1_cache_data, sizeof(l1_cache_data), NULL, 0);
+
+ if (ret)
+ pr_err("%s: could not register L2 buffer ret = %d.\n",
+ __func__, ret);
+#else
imem_loc = ioremap(L2C_IMEM_ADDR, SZ_4K);
__raw_writel(msm_cache_dump_addr + d->l1_size, imem_loc);
iounmap(imem_loc);
+#endif
+ atomic_notifier_chain_register(&panic_notifier_list,
+ &msm_cache_dump_blk);
+ return 0;
+}
+
+static int msm_cache_dump_remove(struct platform_device *pdev)
+{
+ atomic_notifier_chain_unregister(&panic_notifier_list,
+ &msm_cache_dump_blk);
return 0;
}
static struct platform_driver msm_cache_dump_driver = {
+ .remove = __devexit_p(msm_cache_dump_remove),
.driver = {
.name = "msm_cache_dump",
.owner = THIS_MODULE
View
65 arch/arm/mach-msm/msm_dcvs.c
@@ -81,8 +81,9 @@ struct dcvs_core {
uint32_t group_id;
uint32_t freq_pending;
struct hrtimer timer;
- int32_t core_slack_time_us;
int32_t timer_disabled;
+ /* track if kthread for change_freq is active */
+ int32_t change_freq_activated;
};
static int msm_dcvs_debug;
@@ -153,19 +154,12 @@ static int __msm_dcvs_change_freq(struct dcvs_core *core)
if (ret <= 0) {
__err("Core %s failed to set freq %u\n",
core->core_name, requested_freq);
- /* Restart the timers at the current slack time */
- core->timer_disabled = 0;
- ret = hrtimer_start(&core->timer,
- ktime_set(0, core->core_slack_time_us * 1000),
- HRTIMER_MODE_REL_PINNED);
- if (ret)
- __err("Failed to register timer for core %s\n",
- core->core_name);
- return -EFAULT;
+ /* continue to call TZ to get updated slack timer */
+ } else {
+ prev_freq = core->actual_freq;
+ core->actual_freq = ret;
}
- prev_freq = core->actual_freq;
- core->actual_freq = ret;
time_end = ktime_to_ns(ktime_get());
if (msm_dcvs_debug & MSM_DCVS_DEBUG_FREQ_CHANGE)
__info("Core %s Time end %llu Time start: %llu\n",
@@ -201,7 +195,6 @@ static int __msm_dcvs_change_freq(struct dcvs_core *core)
core->actual_freq, (uint32_t)time_end, &slack_us, &ret1);
if (!ret) {
/* Reset the slack timer */
- core->core_slack_time_us = slack_us;
if (slack_us) {
core->timer_disabled = 0;
ret = hrtimer_start(&core->timer,
@@ -221,7 +214,7 @@ static int __msm_dcvs_change_freq(struct dcvs_core *core)
"change time %u us slack time %u us\n",
requested_freq, core->core_name,
core->actual_freq, prev_freq,
- core->freq_change_us, core->core_slack_time_us);
+ core->freq_change_us, slack_us);
/**
* By the time we are done with freq changes, we could be asked to
@@ -230,6 +223,7 @@ static int __msm_dcvs_change_freq(struct dcvs_core *core)
if (core->freq_pending)
goto repeat;
+ core->change_freq_activated = 0;
return ret;
}
@@ -260,17 +254,16 @@ static int msm_dcvs_do_freq(void *data)
}
static int msm_dcvs_update_freq(struct dcvs_core *core,
- enum msm_dcvs_scm_event event, uint32_t param0)
+ enum msm_dcvs_scm_event event, uint32_t param0,
+ uint32_t *ret1, int *freq_changed)
{
int ret = 0;
unsigned long flags = 0;
uint32_t new_freq = 0;
- uint32_t ret1 = 0;
spin_lock_irqsave(&core->cpu_lock, flags);
ret = msm_dcvs_scm_event(core->handle, event, param0,
- core->actual_freq, &new_freq, &ret1);
-
+ core->actual_freq, &new_freq, ret1);
if (ret) {
__err("Error (%d) sending SCM event %d for core %s\n",
ret, event, core->core_name);
@@ -288,8 +281,15 @@ static int msm_dcvs_update_freq(struct dcvs_core *core,
if (!core->task)
__err("Uninitialized task for core %s\n",
core->core_name);
- else
+ else {
+ if (freq_changed)
+ *freq_changed = 1;
+ core->change_freq_activated = 1;
wake_up_process(core->task);
+ }
+ } else {
+ if (freq_changed)
+ *freq_changed = 0;
}
freq_done:
spin_unlock_irqrestore(&core->cpu_lock, flags);
@@ -301,6 +301,8 @@ static enum hrtimer_restart msm_dcvs_core_slack_timer(struct hrtimer *timer)
{
int ret = 0;
struct dcvs_core *core = container_of(timer, struct dcvs_core, timer);
+ uint32_t ret1;
+ uint32_t ret2;
if (msm_dcvs_debug & MSM_DCVS_DEBUG_FREQ_CHANGE)
__info("Slack timer fired for core %s\n", core->core_name);
@@ -309,7 +311,8 @@ static enum hrtimer_restart msm_dcvs_core_slack_timer(struct hrtimer *timer)
* Timer expired, notify TZ