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edm-cf-imx6 : Improve DDR compatibility for imx6DL/Solo

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richard-hu committed Jan 16, 2015
1 parent 067f213 commit b5ff22b241d72b22706999470e660ee8c323807b
Showing with 124 additions and 143 deletions.
  1. +124 −143 board/technexion/edm_cf_imx6/edm_cf_imx6.c
@@ -55,8 +55,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
/*
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define DRIVE_STRENGTH_IMX6SOLO 0x28U
#define DRIVE_STRENGTH_IMX6DL 0x28U
static enum boot_device boot_dev;
enum boot_device get_boot_device(void);
@@ -690,92 +695,78 @@ static void spl_dram_init_mx6solo_512mb(void)
writel(0x000c0000, IOMUXC_BASE_ADDR + 0x774);
writel(0x00000000, IOMUXC_BASE_ADDR + 0x754);
/* CLOCK */
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4ac);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4b0);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4ac);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4b0);
/* ADDRESS */
writel(0x00000030, IOMUXC_BASE_ADDR + 0x464);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x490);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x74c);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x464);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x490);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x74c);
/* CONTROLE */
writel(0x000c0030, IOMUXC_BASE_ADDR + 0x494);
writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a4);
writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a8);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x494);
writel(0x00000000, IOMUXC_BASE_ADDR + 0x4a0);
writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b4);
writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b8);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x76c);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4b4);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4b8);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x76c);
/* DATA STROBE */
writel(0x00020000, IOMUXC_BASE_ADDR + 0x750);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4bc);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4c0);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4c4);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4c8);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4cc);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4d0);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4d4);
writel(0x00000038, IOMUXC_BASE_ADDR + 0x4d8);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4bc);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4c0);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4c4);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x4c8);
/* DATA */
writel(0x00020000, IOMUXC_BASE_ADDR + 0x760);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x764);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x770);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x778);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x77c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x780);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x784);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x78c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x748);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x764);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x770);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x778);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x77c);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x470);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x474);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x478);
writel(DRIVE_STRENGTH_IMX6SOLO, IOMUXC_BASE_ADDR + 0x47c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x470);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x474);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x478);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x47c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x480);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x484);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x488);
writel(0x000C0030, IOMUXC_BASE_ADDR + 0x48c);
/* ZQ */
writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
writel(0xa1390003, MMDC_P1_BASE_ADDR + 0x800);
writel(0xA1390003, MMDC_P0_BASE_ADDR + 0x800);
/* Write leveling */
writel(0x0040003c, MMDC_P0_BASE_ADDR + 0x80c);
writel(0x0032003e, MMDC_P0_BASE_ADDR + 0x810);
writel(0x0053005A, MMDC_P0_BASE_ADDR + 0x80c);
writel(0x00430048, MMDC_P0_BASE_ADDR + 0x810);
writel(0x42350231, MMDC_P0_BASE_ADDR + 0x83c);
writel(0x021a0218, MMDC_P0_BASE_ADDR + 0x840);
writel(0x4b4b4e49, MMDC_P0_BASE_ADDR + 0x848);
writel(0x3f3f3035, MMDC_P0_BASE_ADDR + 0x850);
writel(0x024C0244, MMDC_P0_BASE_ADDR + 0x83c);
writel(0x0234023C, MMDC_P0_BASE_ADDR + 0x840);
writel(0x3E484A44, MMDC_P0_BASE_ADDR + 0x848);
writel(0x3A38302E, MMDC_P0_BASE_ADDR + 0x850);
/* Read data bit delay */
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
/* Complete calibration by forced measurement */
writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
writel(0x0002002d, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00333030, MMDC_P0_BASE_ADDR + 0x008);
writel(0x696d5323, MMDC_P0_BASE_ADDR + 0x00c);
writel(0xb66e8c63, MMDC_P0_BASE_ADDR + 0x010);
writel(0x01ff00db, MMDC_P0_BASE_ADDR + 0x014);
writel(0x00001740, MMDC_P0_BASE_ADDR + 0x018);
writel(0x0002002D, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00333040, MMDC_P0_BASE_ADDR + 0x008);
writel(0x3F435313, MMDC_P0_BASE_ADDR + 0x00c);
writel(0xB66E8B63, MMDC_P0_BASE_ADDR + 0x010);
writel(0x01FF00DB, MMDC_P0_BASE_ADDR + 0x014);
writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x000026d2, MMDC_P0_BASE_ADDR + 0x02c);
writel(0x006d0e21, MMDC_P0_BASE_ADDR + 0x030);
writel(0x00000027, MMDC_P0_BASE_ADDR + 0x040);
writel(0x84190000, MMDC_P0_BASE_ADDR + 0x000);
writel(0x04008032, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
writel(0x00431023, MMDC_P0_BASE_ADDR + 0x030);
writel(0x00000017, MMDC_P0_BASE_ADDR + 0x040);
writel(0x83190000, MMDC_P0_BASE_ADDR + 0x000);
writel(0x02008032, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x07208030, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x05208030, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00005800, MMDC_P0_BASE_ADDR + 0x020);
writel(0x00011117, MMDC_P0_BASE_ADDR + 0x818);
writel(0x00011117, MMDC_P1_BASE_ADDR + 0x818);
writel(0x0002556d, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00011006, MMDC_P1_BASE_ADDR + 0x004);
writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
writel(0x0002556D, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
}
@@ -788,71 +779,70 @@ static void spl_dram_init_mx6dl_1g(void)
writel(0x000c0000, IOMUXC_BASE_ADDR + 0x774);
writel(0x00000000, IOMUXC_BASE_ADDR + 0x754);
/* Clock */
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4ac);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4b0);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4ac);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4b0);
/* Address */
writel(0x00000030, IOMUXC_BASE_ADDR + 0x464);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x490);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x74c);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x464);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x490);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x74c);
/* Control */
writel(0x00000030, IOMUXC_BASE_ADDR + 0x494);
writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a4);
writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a8);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x494);
writel(0x00000000, IOMUXC_BASE_ADDR + 0x4a0);
writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b4);
writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b8);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x76c);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4b4);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4b8);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x76c);
/* Data Strobe */
writel(0x00020000, IOMUXC_BASE_ADDR + 0x750);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4bc);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4c0);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4c4);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4c8);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4cc);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4d0);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4d4);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x4d8);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4bc);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4c0);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4c4);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4c8);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4cc);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4d0);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4d4);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x4d8);
/* DATA */
writel(0x00020000, IOMUXC_BASE_ADDR + 0x760);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x764);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x770);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x778);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x77c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x780);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x784);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x78c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x748);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x470);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x474);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x478);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x47c);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x480);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x484);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x488);
writel(0x00000030, IOMUXC_BASE_ADDR + 0x48c);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x764);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x770);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x778);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x77c);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x780);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x784);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x78c);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x748);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x470);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x474);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x478);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x47c);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x480);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x484);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x488);
writel(DRIVE_STRENGTH_IMX6DL, IOMUXC_BASE_ADDR + 0x48c);
/* Calibrations */
/* ZQ */
writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
writel(0xa1390003, MMDC_P1_BASE_ADDR + 0x800);
writel(0xA1390003, MMDC_P0_BASE_ADDR + 0x800);
/* write leveling */
writel(0x001F001F, MMDC_P0_BASE_ADDR + 0x80c);
writel(0x001F001F, MMDC_P0_BASE_ADDR + 0x810);
writel(0x001F001F, MMDC_P1_BASE_ADDR + 0x80c);
writel(0x001F001F, MMDC_P1_BASE_ADDR + 0x810);
writel(0x003E0047, MMDC_P0_BASE_ADDR + 0x80c);
writel(0x00300036, MMDC_P0_BASE_ADDR + 0x810);
writel(0x0018001B, MMDC_P1_BASE_ADDR + 0x80c);
writel(0x0010002C, MMDC_P1_BASE_ADDR + 0x810);
/* DQS gating, read delay, write delay calibration values
based on calibration compare of 0x00ffff00 */
writel(0x420E020E, MMDC_P0_BASE_ADDR + 0x83c);
writel(0x02000200, MMDC_P0_BASE_ADDR + 0x840);
writel(0x42020202, MMDC_P1_BASE_ADDR + 0x83C);
writel(0x01720172, MMDC_P1_BASE_ADDR + 0x840);
writel(0x494C4F4C, MMDC_P0_BASE_ADDR + 0x848);
writel(0x4A4C4C49, MMDC_P1_BASE_ADDR + 0x848);
writel(0x3F3F3133, MMDC_P0_BASE_ADDR + 0x850);
writel(0x39373F2E, MMDC_P1_BASE_ADDR + 0x850);
writel(0x02380234, MMDC_P0_BASE_ADDR + 0x83c);
writel(0x02300230, MMDC_P0_BASE_ADDR + 0x840);
writel(0x0218021C, MMDC_P1_BASE_ADDR + 0x83C);
writel(0x0210020C, MMDC_P1_BASE_ADDR + 0x840);
writel(0x40464846, MMDC_P0_BASE_ADDR + 0x848);
writel(0x40444640, MMDC_P1_BASE_ADDR + 0x848);
writel(0x3A302E30, MMDC_P0_BASE_ADDR + 0x850);
writel(0x3630302C, MMDC_P1_BASE_ADDR + 0x850);
/* read data bit delay */
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
@@ -867,42 +857,33 @@ static void spl_dram_init_mx6dl_1g(void)
writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
/* MMDC init:
in DDR3, 64-bit mode, only MMDC0 is initiated: */
writel(0x0002002d, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00333030, MMDC_P0_BASE_ADDR + 0x008);
writel(0x0002002D, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00333040, MMDC_P0_BASE_ADDR + 0x008);
writel(0x40445323, MMDC_P0_BASE_ADDR + 0x00c);
writel(0xb66e8c63, MMDC_P0_BASE_ADDR + 0x010);
writel(0x3F435313, MMDC_P0_BASE_ADDR + 0x00c);
writel(0xB66E8B63, MMDC_P0_BASE_ADDR + 0x010);
writel(0x01ff00db, MMDC_P0_BASE_ADDR + 0x014);
writel(0x00081740, MMDC_P0_BASE_ADDR + 0x018);
writel(0x01FF00DB, MMDC_P0_BASE_ADDR + 0x014);
writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x000026d2, MMDC_P0_BASE_ADDR + 0x02c);
writel(0x00440e21, MMDC_P0_BASE_ADDR + 0x030);
writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
writel(0x00431023, MMDC_P0_BASE_ADDR + 0x030);
writel(0x00000027, MMDC_P0_BASE_ADDR + 0x040);
writel(0xc31a0000, MMDC_P0_BASE_ADDR + 0x000);
writel(0x831A0000, MMDC_P0_BASE_ADDR + 0x000);
/* Initialize 2GB DDR3 - Micron MT41J128M */
/* MR2 */
writel(0x04008032, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x0400803a, MMDC_P0_BASE_ADDR + 0x01c);
/* MR3 */
/* MR */
writel(0x02008032, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x0000803b, MMDC_P0_BASE_ADDR + 0x01c);
/* MR1 */
writel(0x00428031, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00428039, MMDC_P0_BASE_ADDR + 0x01c);
/* MR0 */
writel(0x07208030, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x07208038, MMDC_P0_BASE_ADDR + 0x01c);
/* ZQ calibration */
writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x05208030, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
/* final DDR setup */
writel(0x00005800, MMDC_P0_BASE_ADDR + 0x020);
writel(0x00000007, MMDC_P0_BASE_ADDR + 0x818);
writel(0x00000007, MMDC_P1_BASE_ADDR + 0x818);
writel(0x0002556d, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00011006, MMDC_P1_BASE_ADDR + 0x404);
writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
writel(0x0002556D, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
}

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