The focus of this project is to implement an 8-bit gray code counter in skywater 130nm and determine its functional, pre-layout and post layout characteristics (namely power, performance and area).
Note: Circuit requires further optimization to improve performance. Design yet to be modified.
- 1. Introduction
- 2. Application of Gray Counter
- 3. Verilog Implementation of Gray Code Counter
- 4. Functional Simulation
- 5. Synthesis
- 6. Gate Level Simulation GLS
- 7. Creating Custom Cell
- 8. Physical Design
- 9. Results for Mid-Term Examination
- Author
- Acknowledgement
- Contact Information
- References
Gray code counter is a digital counter that counts such that each successive bit patterns differs by only one bit. Unlike normal counters, there are no glitches in the count pattern (0 -> 1 -> 3 -> 2 -> 6 -> 7 ......... ). Since switching is less in gray code counters (i.e., exactly one-bit switches in one clock cycle), the power consumption of the gray code counter is significantly less compared to the normal counter.1
Gray code finds application in multiple electromechanical applications due to its error resilient property. This is achieved due to the single bit change from one code word to the adjacent next code word. This article lists down few more applications of Gray code.
- Since the Gray code reduces the likelihood of mistakes, it is employed in the transmission of digital signals.
- In angle-measuring equipment, the Gray code is chosen over the simple binary code. The likelihood of an angle being misread is virtually eliminated when using the Gray code, compared to when using straight binary to express the angle. The Gray code's cyclic characteristic comes in handy for this application.
- The axes of Karnaugh maps, a graphical method for minimising Boolean equations, are labelled using the Gray code.
- Gray codes are used to access programme memory in computers in a way that uses the least amount of electricity. Less address lines are changing state as the programme counter advances as a result.
- Given that mutations in the code often only allow for gradual modifications, grey codes are also particularly helpful in genetic algorithms. On occasion, though, a little adjustment might cause a significant jump, giving rise to novel traits.
- The gray code counter has applications in analog to digital converters.
The Gray Code counter block diagram is shown below. 2
The digital circuit takes clock, enable and reset as input. It generates an 8-bit gray code sequence at every positive clock edge. The port description of the gray code counter is shown in Table below.
| PORT NAME | PORT TYPE | DESCRIPTION |
|---|---|---|
| clk | input | Clock Input |
| enable | input | Enables the counter to count on positive clk edge |
| reset | input | Resets the counter to 0 |
| gray_count[7:0] | output | 8-bit gray code output |
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. 3
GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing. 4
sudo apt-get install git
sudo apt-get install iverilog
sudo apt-get install gtkwave
git clone https://github.com/TejasBN28/iiitb_gc.git
cd iiitb_gc
iverilog iiitb_gc.v iiitb_gc_tb.v -o iiitb_gc
./iiitb_gc
gtkwave iiitb_gc.vcd
Few count sequence of the gray code counter is displayed in below. At the first positive edge of the clock, the counter resets to 0x00. From the second clock onwards, the counter starts to count in gray code sequence.
The software used to run gate level synthesis is Yosys. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base. 5
sudo apt-get install build-essential clang bison flex \
libreadline-dev gawk tcl-dev libffi-dev git \
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
git clone https://github.com/YosysHQ/yosys.git
make
sudo make install
make test
The commands to run synthesis in yosys are given below. First create an yosys script yosys_run.sh and paste the below commands.
read_liberty -lib lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog iiitb_gc.v
synth -top iiitb_gc
dfflibmap -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.lib
clean
flatten
write_verilog -noattr iiitb_gc_synth.v
stat
show
Then, open terminal in the folder iiitb_gc and type the below command.
yosys -s yosys_run.sh
On running the yosys script, we get the following output:
GLS stands for gate level simulation. When we write the RTL code, we test it by giving it some stimulus through the testbench and check it for the desired specifications. Similarly, we run the netlist as the design under test (dut) with the same testbench. Gate level simulation is done to verify the logical correctness of the design after synthesis. Also, it ensures the timing of the design.
Commands to run the GLS are given below.
iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 iiitb_gc_synth.v iiitb_gc_tb.v verilog_model/primitives.v verilog_model/sky130_fd_sc_hd.v -o iiitb_gc
./iiitb_gc
gtkwave iiitb_gc.vcd
Few count sequence of the gray code counter is displayed in below. At the first positive edge of the clock, the counter resets to 0x00. From the second clock onwards, the counter starts to count in gray code sequence.
First, clone the github repo containing the inverter and prepare for the next steps.
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
cd vsdstdcelldesign
cp ./libs/sky130A.tech sky130A.tech
magic -T sky130A.tech sky130_inv.mag &
On typing the following commands, the following netlist will open.
Now, to extract the spice netlist, type the following commands in the tcl console. Here, parasitic capacitances and resistances of the inverter is extracted by cthresh 0 rthresh 0.
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
The extracted spice model is shown below (which is edited to simulate the inverter).
* SPICE3 file created from sky130_inv.ext - technology: sky130A
.option scale=0.01u
.include ./libs/pshort.lib
.include ./libs/nshort.lib
M1001 Y A VGND VGND nshort_model.0 ad=1435 pd=152 as=1365 ps=148 w=35 l=23
M1000 Y A VPWR VPWR pshort_model.0 ad=1443 pd=152 as=1517 ps=156 w=37 l=23
VDD VPWR 0 3.3V
VSS VGND 0 0V
Va A VGND PULSE(0V 3.3V 0 0.1ns 0.1ns 2ns 4ns)
C0 Y VPWR 0.08fF
C1 A Y 0.02fF
C2 A VPWR 0.08fF
C3 Y VGND 0.18fF
C4 VPWR VGND 0.74fF
.tran 1n 20n
.control
run
.endc
.end
To get a grid and to ensure the ports are placed correctly we type the following command in the tcl console
grid 0.46um 0.34um 0.23um 0.17um
In Magic Layout window, first source the .mag file for the design (here inverter). Then Edit >> Text which opens up a dialogue box. Then do the steps shown in the below figure.
Now, to extract the lef file and save it, type the following command.
lef write
The extracted lef file is shown below.
VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_vsdinv
CLASS CORE ;
FOREIGN sky130_vsdinv ;
ORIGIN 0.000 0.000 ;
SIZE 1.380 BY 2.720 ;
SITE unithd ;
PIN A
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.165600 ;
PORT
LAYER li1 ;
RECT 0.060 1.180 0.510 1.690 ;
END
END A
PIN Y
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.287800 ;
PORT
LAYER li1 ;
RECT 0.760 1.960 1.100 2.330 ;
RECT 0.880 1.690 1.050 1.960 ;
RECT 0.880 1.180 1.330 1.690 ;
RECT 0.880 0.760 1.050 1.180 ;
RECT 0.780 0.410 1.130 0.760 ;
END
END Y
PIN VPWR
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER nwell ;
RECT -0.200 1.140 1.570 3.040 ;
LAYER li1 ;
RECT -0.200 2.580 1.430 2.900 ;
RECT 0.180 2.330 0.350 2.580 ;
RECT 0.100 1.970 0.440 2.330 ;
LAYER mcon ;
RECT 0.230 2.640 0.400 2.810 ;
RECT 1.000 2.650 1.170 2.820 ;
LAYER met1 ;
RECT -0.200 2.480 1.570 2.960 ;
END
END VPWR
PIN VGND
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER li1 ;
RECT 0.100 0.410 0.450 0.760 ;
RECT 0.150 0.210 0.380 0.410 ;
RECT 0.000 -0.150 1.460 0.210 ;
LAYER mcon ;
RECT 0.210 -0.090 0.380 0.080 ;
RECT 1.050 -0.090 1.220 0.080 ;
LAYER met1 ;
RECT -0.110 -0.240 1.570 0.240 ;
END
END VGND
END sky130_vsdinv
END LIBRARY
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.
sudo apt install -y build-essential python3 python3-venv python3-pip
Docker installation process for ubuntu is explained in this link: https://docs.docker.com/engine/install/ubuntu/. Alternatively, the following commands install the docker.
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
sudo make
To test the open lane
sudo make test
It takes approximate time of 5 minutes to complete. After 43 steps, if it ended with saying Basic test passed then open lane installed succesfully.
Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow
Run following commands one by one to fulfill the system requirement.
sudo apt-get install m4
sudo apt-get install tcsh
sudo apt-get install csh
sudo apt-get install libx11-dev
sudo apt-get install tcl-dev tk-dev
sudo apt-get install libcairo2-dev
sudo apt-get install mesa-common-dev libglu1-mesa-dev
sudo apt-get install libncurses-dev
git clone https://github.com/RTimothyEdwards/magic
cd magic/
./configure
sudo make
sudo make install
type magic terminal to check whether it installed succesfully or not. Type exit to exit magic.
Download the config.json file and place it in the OpenLane/designs/iiitb_gc folder. The config.json file is given below as well.
{
"DESIGN_NAME": "iiitb_gc",
"VERILOG_FILES": "dir::src/iiitb_gc.v",
"CLOCK_PORT": "clkin",
"CLOCK_NET": "clkin",
"GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
"CLOCK_PERIOD": 65,
"PL_TARGET_DENSITY": 0.7,
"FP_SIZING" : "relative",
"pdk::sky130*": {
"FP_CORE_UTIL": 30,
"scl::sky130_fd_sc_hd": {
"FP_CORE_UTIL": 20
}
},
"LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB": "dir::/src/*"
}
Now, paste the verilog code iiitb_gc.v, sky130_vsdinv.lef, sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib and sky130_fd_sc_hd__typical.libinside the folder OpenLane/designs/iiitb_gc/src
To invoke OpenLane, type the following commands. On typing the following commands, runs folder is created inside the iiitb_gc folder.
cd OpenLane
make mount
./flow.tcl -interactive
prep -design iiitb_gc
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
Now, we can observe that the sky130_vsdinv is included in merged.nom.lef file.
Now, to run synthesis, type the following command
run_synthesis
The synthesized netlist is present in the results folder and the stats are present in the reports folder.
Here, we notice that our custom cell sky130_vsdinv is displayed in the netlist generated.
Also, sta report post synthesis can be viewed by going to the location logs\synthesis\2-sta.log
The next step is to run floorplan and placement. Type the following commands.
run_floorplan
The floorplan can be viewed by typing the following command.
magic -T /home/tejasbn/Desktop/OpenLane/pdks/volare/sky130/versions/44a43c23c81b45b8e774ae7a84899a5a778b6b0b/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_gc.def &
Also, Die Area and Core Area can be viewed in the reports/floorplan directory.
The placement can be viewed by typing the following command.
run_placement
The placement can be viewed by typing the following command.
magic -T /home/tejasbn/Desktop/OpenLane/pdks/volare/sky130/versions/44a43c23c81b45b8e774ae7a84899a5a778b6b0b/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_gc.def &
The next step is to run run clock tree synthesis. The CTS run adds clock buffers in therefore buffer delays come into picture and our analysis from here on deals with real clocks. To run clock tree synthesis, type the following commands
run_cts
The netlist with clock buffers can be viewed by going to the location results\cts\iiitb_gc.v
Also, sta report post synthesis can be viewed by going to the location logs\synthesis\12-cts.log
The command to run routing is
run_routing
ALso, sky130_vsdinv can be viewed in the routing layout.
The post synthesis gate count for my design is 47 cells.
Area of the chip is 4384.215 sq micrometers.
To find the performance of the chip, the netlist generated after the clock tree synthesis is considered. The generated netlist is analysed and is found to contain 8 flipflops. Now, reg to reg path for all the flipflops are calculated using OpenSTA tool. Then, the reg to reg path with the worst slack is considered for calculating the performance.
The steps followed are
- Invoke OpenSTA with the following commands.
sudo make mount sta - Type the following commands to run the OpenSTA tool for my design.
read_liberty -max /home/tejasbn/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib read_liberty -min /home/tejasbn/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib read_verilog /home/tejasbn/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/iiitb_gc.v link_design iiitb_gc read_sdc /home/tejasbn/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/iiitb_gc.sdc read_spef /home/tejasbn/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/iiitb_gc.spef set_propagated_clock clk create_clock -name clk -period 10 {clk} report_checks -from _71_/CLK -to _76_/D
From here, tsetup is 0.09 ns, path delay is 1.52ns and clock network delay is 0.19ns.
Slack is 8.57ns and clock period is 10ns. So, clock frequency is 1/(10-8.57) = 699.3MHz.
Flop ratio = Number of D Flip flops
______________________
Total Number of cells
dfxtp_2 = 8,
Number of cells = 47,
Flop ratio = 8/47 = 0.1702 = 17.02%
The total power consumed by the chip is 2.17 micro Watt.
- Internal Power = 1.29 micro Watt
- Switching Power = 0.879 micro Watt
- Leakage Power = 0.199 nano Watt
- Tejas B N
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Madhav Rao, Associate Professor, IIIT Bangalore
- V N Muralidhara, Associate Professor, IIIT Bangalore
- Tejas B N, Postgraduate Student, International Institute of Information Technology, Bangalore bntejas@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
Footnotes
-
Varun Akula, Dr. Vishwani D. Agrawal, James J. Danaher. Comparison of power consumption of 4-bit binary counters with various state encodings including gray and one-hot codes. Auburn University ↩
-
8-bit Gray Counter from ASIC World for the verilog design of gray counter. ↩
-
GTK Wave documentation ↩