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The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.
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README.md

TerosHDL

Teros Technology: http://www.terostech.com/

Our philosophy is: think in hardware, develop hardware, take advantage of software tools.

The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.

Currently we support:

  • Ghdl.
  • ModelSim.
  • Vhdl
  • VUnit.

Soon we will support Verilog and others simulators.

Dependencies

For simulation:

  • Ghdl/Modelsim

For code coverage:

  • Ghdl with GCC backend.
  • LCOV

For waveform:

  • GTKWave/ModelSim

Installation

apm install terosHDL

Getting started guide

Runing test

Running_test

Code coverage

Code_coverage

Creating component diagram

diagram

Structure view

diagram

State machine diagram

This is an experimental feature. Not all state machines are supported.

diagram

User Manual

You have a complete user manual.

License

Copyright (c) 2018-Present

TerosHDL is licensed under GPLv3.

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