The idea is that the toolbar has the main functionalities. Each of them is represented as an icon.
This is a representation of the IDE workflow from left to right.
- Create repository
- Create files/testbench.
- Create Vunit file.
- Run test.
- Document design.
Add files or creates a repository estructure with an example design.
Put the mouse inside an VHDL entity and click the button. This will copy to clipboard a component estructure of the entity.
Put the mouse inside an VHDL entity and click the button. This will copy to clipboard an instance of the entity.
Put the mouse inside an VHDL entity and click the button. This will copy to clipboard the signals of the entity ports.
Put the mouse inside an VHDL entity and click the button. This will copy to clipboard a template to create a testbench of the entity with Vunit framework. If AXI lite is being used the testbench will include code to test the bus with UVVM libraries.
This will open a dialog to select the source files and the testbench files. You can also select the location of the file, the name and to include libraries for simulation. You can also mark other checks if you wish to modify the python file manually and add more complex test.
This button open or close the structure view panel.
Run.py arguments configuration
Here you can configure some things about run.py:
- Add custom arguments to be executed each time the run test button is pressed.
- Select the run.py file for run test button
- Select which test should be executed.
- Select the oputput of the test Terminal or waveform.
- Select the waveform file to be opened automatically to view the results.
This is the button used to run the test in your design with the previous configuration.
If you wish to cancel the a launched test you can use this button.
Sometimes you need to recompile the whole design, it can be done that with this button.
Browse code coverage report
Take into acount that the code coverage is the sum of all the test run.
It is necessary to recompile if you want to update the code coverage.
Switch between simulators just pressing this button.
Here you can create an image of the inputs and outputs of the module. You just need to put the cursor selecting the component of a module you want to draw.
Copy as doc.
With this button you will get a port table in markdown format of an entity of your choice.
|in_1||std_logic_vector (4 downto 0)||N/A|
|in_2||std_logic_vector (4 downto 0)||N/A|
|in_3||std_logic_vector (4 downto 0)||N/A|
|sum||std_logic_vector (7 downto 0)||N/A|
Link to this manual.
You will be redirected to the last versión of the manual. Make sure it matches with your TerosHDL version.
Pressing this button you can show or hide the console panel.