From dc930905d502fef196c9d82fa9036442712186c1 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 27 Oct 2025 15:13:54 +0100 Subject: [PATCH 0001/1450] tests: i2c_ram: Fix assert message Being pedantic, the second parameter to zassert_ok() is supposed to be a literal format specifier string. (Just as for printf()). Not directly a variable string to be printed. Let's fix it. Fixes this build warning: `warning: format not a string literal and no format arguments` Signed-off-by: Alberto Escolar Piedras --- tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c b/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c index 5d99f9c7af84a..0429a4841f9da 100644 --- a/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c +++ b/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c @@ -202,7 +202,7 @@ static void check_completion(struct rtio_cqe *cqe, const char *msg) result = cqe->result; rtio_cqe_release(&i2c_rtio, cqe); if (result) { - zassert_ok(result, msg); + zassert_ok(result, "%s", msg); } } From 8fb6cb753768cc35551b379614da76bf54c401d5 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 27 Oct 2025 15:01:46 +0100 Subject: [PATCH 0002/1450] tracing: ctf: Fix arguments for socket tracing functions (again) Zephyr's socklen_t was changed in c546c1cad1f86977dbf3fb3354469db9cda926aa to be uint32_t instea of size_t. Let's fix accordingly the prototypes which expect it. Note this was already fixed in 37ff1b254fdf84c5fd9787cd2223342d7bfb1931 But it was reverted in d849ab12639e9faf754f38fc2bd7315c31fd2fad Signed-off-by: Alberto Escolar Piedras --- subsys/tracing/ctf/ctf_top.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/tracing/ctf/ctf_top.c b/subsys/tracing/ctf/ctf_top.c index 34743b8144e4c..65c41062cfe5b 100644 --- a/subsys/tracing/ctf/ctf_top.c +++ b/subsys/tracing/ctf/ctf_top.c @@ -1010,7 +1010,7 @@ void sys_trace_socket_accept_enter(int sock) ctf_top_socket_accept_enter(sock); } -void sys_trace_socket_accept_exit(int sock, const struct sockaddr *addr, const size_t *addrlen, +void sys_trace_socket_accept_exit(int sock, const struct sockaddr *addr, const uint32_t *addrlen, int ret) { ctf_net_bounded_string_t addr_str = {"unknown"}; From 70fe96122381eebf42342fad1f72089abe9aef5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Fri, 24 Oct 2025 11:04:38 +0200 Subject: [PATCH 0003/1450] drivers: mspi_dw: Use uint32_t for dummy_bytes field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the driver allows transfer lengths up to `UINT16_MAX + 1` bytes, and additionally the `dummy_bytes` field includes bytes sent to provide wait cycles on the bus, the type of this field must be `uint32_t`, otherwise it can be overflowed for RX transfers close to the maximum. Signed-off-by: Andrzej Głąbek --- drivers/mspi/mspi_dw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mspi/mspi_dw.c b/drivers/mspi/mspi_dw.c index d4700a99261aa..49bab8df6f612 100644 --- a/drivers/mspi/mspi_dw.c +++ b/drivers/mspi/mspi_dw.c @@ -59,7 +59,7 @@ struct mspi_dw_data { enum mspi_cpp_mode xip_cpp; #endif - uint16_t dummy_bytes; + uint32_t dummy_bytes; uint8_t bytes_to_discard; uint8_t bytes_per_frame_exp; bool standard_spi; @@ -317,7 +317,7 @@ static bool tx_dummy_bytes(const struct device *dev, bool *repeat) uint8_t fifo_room = dev_config->max_queued_dummy_bytes - FIELD_GET(TXFLR_TXTFL_MASK, read_txflr(dev)); uint8_t rx_fifo_items = FIELD_GET(RXFLR_RXTFL_MASK, read_rxflr(dev)); - uint16_t dummy_bytes = dev_data->dummy_bytes; + uint32_t dummy_bytes = dev_data->dummy_bytes; const uint8_t dummy_val = 0; /* Subtract the number of items that are already stored in the RX From 69bfd434e1d73a79a2ccb0c0fb5b4839fb5b42e1 Mon Sep 17 00:00:00 2001 From: Erik Andersson Date: Thu, 23 Oct 2025 21:57:22 +0200 Subject: [PATCH 0004/1450] drivers: i2c_stm32_v2: fix assert in i2c event isr For systems where the CPU / NVIC bus are considerably faster than the peripheral bus used for I2C, there is a risk that the isr handler returns before I2C controller had time to clear its interrupt status flags This would cause immediate re-entry to isr handler which begins read from ISR register. During time it take to re-enter and read from ISR register, flags had time to be cleared The isr handler expects that a flag is set, and in this case when its not, an assert is triggered The solution here is to make a dummy read from the ISR register before returning from isr handler, this forces CPU to wait as long as needed to ensure all writes to the I2C peripheral are completed Fixes issue #97904 Signed-off-by: Erik Andersson --- drivers/i2c/i2c_ll_stm32_v2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 515548859cd37..01abee6aa9108 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -578,6 +578,11 @@ void i2c_stm32_event(const struct device *dev) __ASSERT_NO_MSG(0); } + /* Make a dummy read from ISR to ensure we don't return before + * i2c controller had a chance to clear its interrupt flags due + * to bus delays + */ + (void)LL_I2C_ReadReg(regs, ISR); return; irq_xfer_completed: From 4bf6a756280be4d90edf96f1a4c088c4620be41d Mon Sep 17 00:00:00 2001 From: David Jewsbury Date: Thu, 23 Oct 2025 18:18:03 +0100 Subject: [PATCH 0005/1450] drivers: mspi_dw: Edit core disable to after PM init There is a scenario where a Bus fault occurs as the power management isn't initialised yet and the core is attempted to be turned off via the ssienr register. This commit edits this so the core register is written to after the initialisation of the power management. Signed-off-by: David Jewsbury --- drivers/mspi/mspi_dw.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mspi/mspi_dw.c b/drivers/mspi/mspi_dw.c index 49bab8df6f612..02cfaad194b57 100644 --- a/drivers/mspi/mspi_dw.c +++ b/drivers/mspi/mspi_dw.c @@ -1864,9 +1864,6 @@ static int dev_init(const struct device *dev) } } - /* Make sure controller is disabled. */ - write_ssienr(dev, 0); - #if defined(CONFIG_PINCTRL) if (IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME)) { rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP); @@ -1877,7 +1874,15 @@ static int dev_init(const struct device *dev) } #endif - return pm_device_driver_init(dev, dev_pm_action_cb); + rc = pm_device_driver_init(dev, dev_pm_action_cb); + if (rc < 0) { + return rc; + } + + /* Make sure controller is disabled. */ + write_ssienr(dev, 0); + + return 0; } static DEVICE_API(mspi, drv_api) = { From 55af2824dc9ab25100f625c24d84cdbc489ecef4 Mon Sep 17 00:00:00 2001 From: David Jewsbury Date: Thu, 23 Oct 2025 18:44:10 +0100 Subject: [PATCH 0006/1450] drivers: mspi_dw: Add CONFIG_MSPI_DW_DDR Dual data rate isn't always supported so this config enables/disables the relevant code in the driver. Signed-off-by: David Jewsbury --- drivers/mspi/Kconfig.dw | 9 +++++++++ drivers/mspi/mspi_dw.c | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/drivers/mspi/Kconfig.dw b/drivers/mspi/Kconfig.dw index 71302a801fdbd..e967671e47238 100644 --- a/drivers/mspi/Kconfig.dw +++ b/drivers/mspi/Kconfig.dw @@ -11,6 +11,13 @@ config MSPI_DW if MSPI_DW +config MSPI_DW_DDR + bool "Dual Data-Rate (DDR) capabilities" + default y + help + Dual data rate is supported by some devices and requires specific + registers to be enabled in the IP. + config MSPI_DW_HANDLE_FIFOS_IN_SYSTEM_WORKQUEUE bool "Handle FIFO in system workqueue" depends on MULTITHREADING @@ -23,6 +30,7 @@ config MSPI_DW_HANDLE_FIFOS_IN_SYSTEM_WORKQUEUE config MSPI_DW_TXD_DIV int "Designware SSI TX Drive edge divisor" + depends on MSPI_DW_DDR default 4 help Division factor to apply to calculated BAUDR value when writing it @@ -31,6 +39,7 @@ config MSPI_DW_TXD_DIV config MSPI_DW_TXD_MUL int "Designware SSI TX Drive edge multiplier" + depends on MSPI_DW_DDR default 1 help Multiplication factor to apply to calculated BAUDR value when writing diff --git a/drivers/mspi/mspi_dw.c b/drivers/mspi/mspi_dw.c index 02cfaad194b57..66bdf670c02d8 100644 --- a/drivers/mspi/mspi_dw.c +++ b/drivers/mspi/mspi_dw.c @@ -937,6 +937,7 @@ static int _api_dev_config(const struct device *dev, switch (cfg->data_rate) { case MSPI_DATA_RATE_SINGLE: break; +#if defined(CONFIG_MSPI_DW_DDR) case MSPI_DATA_RATE_DUAL: dev_data->spi_ctrlr0 |= SPI_CTRLR0_INST_DDR_EN_BIT; /* Also need to set DDR_EN bit */ @@ -944,6 +945,7 @@ static int _api_dev_config(const struct device *dev, case MSPI_DATA_RATE_S_D_D: dev_data->spi_ctrlr0 |= SPI_CTRLR0_SPI_DDR_EN_BIT; break; +#endif default: LOG_ERR("Data rate %d not supported", cfg->data_rate); @@ -1238,6 +1240,7 @@ static int start_next_packet(const struct device *dev) write_spi_ctrlr0(dev, dev_data->spi_ctrlr0); write_baudr(dev, dev_data->baudr); write_rx_sample_dly(dev, dev_data->rx_sample_dly); +#if defined(CONFIG_MSPI_DW_DDR) if (dev_data->spi_ctrlr0 & (SPI_CTRLR0_SPI_DDR_EN_BIT | SPI_CTRLR0_INST_DDR_EN_BIT)) { int txd = (CONFIG_MSPI_DW_TXD_MUL * dev_data->baudr) / @@ -1247,6 +1250,7 @@ static int start_next_packet(const struct device *dev) } else { write_txd_drive_edge(dev, 0); } +#endif if (xip_enabled) { write_ssienr(dev, SSIENR_SSIC_EN_BIT); From d0ab7a2d5582da553b84a1de6d2db92c0c2d1435 Mon Sep 17 00:00:00 2001 From: Qingsong Gou Date: Thu, 23 Oct 2025 20:42:42 +0800 Subject: [PATCH 0007/1450] dts: bindings: clock_control: fix sf32lb clock error fix clock id definition and clock ids Signed-off-by: Qingsong Gou --- include/zephyr/dt-bindings/clock/sf32lb-clocks-common.h | 4 ++-- include/zephyr/dt-bindings/clock/sf32lb52x-clocks.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/zephyr/dt-bindings/clock/sf32lb-clocks-common.h b/include/zephyr/dt-bindings/clock/sf32lb-clocks-common.h index 79f0b2a94c0bf..eb98ca353f994 100644 --- a/include/zephyr/dt-bindings/clock/sf32lb-clocks-common.h +++ b/include/zephyr/dt-bindings/clock/sf32lb-clocks-common.h @@ -28,7 +28,7 @@ * @param bit Configuration bit */ #define SF32LB_CLOCK_CONFIG(offset, bit) \ - ((((offset) & SF32LB_CLOCK_OFFSET_MSK) << SF32LB_CLOCK_OFFSET_POS) | \ - (((bit) & SF32LB_CLOCK_BIT_MSK) << SF32LB_CLOCK_BIT_POS)) + ((((offset) << SF32LB_CLOCK_OFFSET_POS) & SF32LB_CLOCK_OFFSET_MSK) | \ + (((bit) << SF32LB_CLOCK_BIT_POS) & SF32LB_CLOCK_BIT_MSK)) #endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_SF32LB_CLOCKS_COMMON_H_ */ diff --git a/include/zephyr/dt-bindings/clock/sf32lb52x-clocks.h b/include/zephyr/dt-bindings/clock/sf32lb52x-clocks.h index 1bb68e11e1f7e..561130b36de91 100644 --- a/include/zephyr/dt-bindings/clock/sf32lb52x-clocks.h +++ b/include/zephyr/dt-bindings/clock/sf32lb52x-clocks.h @@ -24,8 +24,8 @@ */ #define SF32LB52X_CLOCK_DMAC1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 0U) -#define SF32LB52X_CLOCK_MAILBOX1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR2, 1U) -#define SF32LB52X_CLOCK_PINMUX1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR2, 2U) +#define SF32LB52X_CLOCK_MAILBOX1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 1U) +#define SF32LB52X_CLOCK_PINMUX1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 2U) #define SF32LB52X_CLOCK_USART2 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 4U) #define SF32LB52X_CLOCK_EZIP1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 5U) #define SF32LB52X_CLOCK_EPIC SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 6U) From 533ef581573a84098e45fd5d0f8cf3c90df9abe9 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Tue, 21 Oct 2025 22:14:18 +0200 Subject: [PATCH 0008/1450] Bluetooth: Controller: Fix use-after-release in lll_scan/lll_scan_aux Fix use-after-release in lll_scan/lll_scan_aux when using mayfly_enqueue to defer execution of the offset calculation using ull_sched_mfy_after_cen_offset_get(). Apply suggestion from @Copilot Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/ll_sw/lll_scan.h | 8 ++++++++ .../controller/ll_sw/nordic/lll/lll_scan.c | 16 +++++++++++----- .../controller/ll_sw/nordic/lll/lll_scan_aux.c | 13 ++++++++++--- 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/lll_scan.h b/subsys/bluetooth/controller/ll_sw/lll_scan.h index db0f08a182e1d..b9633f8993839 100644 --- a/subsys/bluetooth/controller/ll_sw/lll_scan.h +++ b/subsys/bluetooth/controller/ll_sw/lll_scan.h @@ -17,6 +17,14 @@ struct lll_scan { uint8_t adv_addr[BDADDR_SIZE]; uint32_t conn_win_offset_us; uint16_t conn_timeout; + +#if defined(CONFIG_BT_CTLR_SCHED_ADVANCED) + /* Stores prepare parameters for deferred mayfly execution. + * This prevents use-after-release issues by ensuring the parameters + * remain valid until execution. + */ + struct lll_prepare_param prepare_param; +#endif /* CONFIG_BT_CTLR_SCHED_ADVANCED */ #endif /* CONFIG_BT_CENTRAL */ uint8_t state:1; diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c index 7ae1f8bb6de23..5cfa63b3bcf5d 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c @@ -509,13 +509,19 @@ static int common_prepare_cb(struct lll_prepare_param *p, bool is_resume) static memq_link_t link; static struct mayfly mfy_after_cen_offset_get = { 0U, 0U, &link, NULL, ull_sched_mfy_after_cen_offset_get}; - uint32_t retval; + struct lll_prepare_param *prepare_param; - mfy_after_cen_offset_get.param = p; + /* Copy the required values to calculate the offsets */ + prepare_param = &lll->prepare_param; + prepare_param->ticks_at_expire = p->ticks_at_expire; + prepare_param->remainder = p->remainder; + prepare_param->param = lll; - retval = mayfly_enqueue(TICKER_USER_ID_LLL, TICKER_USER_ID_ULL_LOW, 1U, - &mfy_after_cen_offset_get); - LL_ASSERT_ERR(!retval); + mfy_after_cen_offset_get.param = prepare_param; + + ret = mayfly_enqueue(TICKER_USER_ID_LLL, TICKER_USER_ID_ULL_LOW, 1U, + &mfy_after_cen_offset_get); + LL_ASSERT_ERR(!ret); } #endif /* CONFIG_BT_CENTRAL && CONFIG_BT_CTLR_SCHED_ADVANCED */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c index 6665dc7390e29..8606a79136098 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c @@ -607,12 +607,19 @@ static int prepare_cb(struct lll_prepare_param *p) static memq_link_t link; static struct mayfly mfy_after_cen_offset_get = { 0U, 0U, &link, NULL, ull_sched_mfy_after_cen_offset_get}; + struct lll_prepare_param *prepare_param; - /* NOTE: LLL scan instance passed, as done when + /* Copy the required values to calculate the offsets + * + * NOTE: LLL scan instance passed, as done when * establishing legacy connections. */ - p->param = lll; - mfy_after_cen_offset_get.param = p; + prepare_param = &lll->prepare_param; + prepare_param->ticks_at_expire = p->ticks_at_expire; + prepare_param->remainder = p->remainder; + prepare_param->param = lll; + + mfy_after_cen_offset_get.param = prepare_param; ret = mayfly_enqueue(TICKER_USER_ID_LLL, TICKER_USER_ID_ULL_LOW, 1U, &mfy_after_cen_offset_get); From 50b1732770b3a01b6a7cf3c7fe5dbc3f15ffa3e6 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 17 Oct 2025 12:16:00 +0100 Subject: [PATCH 0009/1450] dts: arm: nordic: Add ranges and address/size cells to SRAM nodes Allows these nodes to be partitioned Signed-off-by: Jamie McCrae --- dts/arm/nordic/nrf51822.dtsi | 2 ++ dts/arm/nordic/nrf51822_qfaa.dtsi | 1 + dts/arm/nordic/nrf51822_qfab.dtsi | 1 + dts/arm/nordic/nrf51822_qfac.dtsi | 1 + dts/arm/nordic/nrf52805.dtsi | 2 ++ dts/arm/nordic/nrf52805_caaa.dtsi | 1 + dts/arm/nordic/nrf52810.dtsi | 2 ++ dts/arm/nordic/nrf52810_qfaa.dtsi | 1 + dts/arm/nordic/nrf52811.dtsi | 2 ++ dts/arm/nordic/nrf52811_qfaa.dtsi | 1 + dts/arm/nordic/nrf52820.dtsi | 2 ++ dts/arm/nordic/nrf52820_qdaa.dtsi | 1 + dts/arm/nordic/nrf52832.dtsi | 2 ++ dts/arm/nordic/nrf52832_ciaa.dtsi | 1 + dts/arm/nordic/nrf52832_qfaa.dtsi | 1 + dts/arm/nordic/nrf52832_qfab.dtsi | 1 + dts/arm/nordic/nrf52833.dtsi | 2 ++ dts/arm/nordic/nrf52833_qdaa.dtsi | 1 + dts/arm/nordic/nrf52833_qiaa.dtsi | 1 + dts/arm/nordic/nrf52840.dtsi | 2 ++ dts/arm/nordic/nrf52840_qfaa.dtsi | 1 + dts/arm/nordic/nrf52840_qiaa.dtsi | 1 + dts/arm/nordic/nrf5340_cpuapp.dtsi | 2 ++ dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi | 1 + dts/arm/nordic/nrf5340_cpuappns.dtsi | 2 ++ dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi | 1 + dts/arm/nordic/nrf5340_cpunet.dtsi | 4 ++++ dts/arm/nordic/nrf5340_cpunet_qkaa.dtsi | 2 ++ dts/arm/nordic/nrf91.dtsi | 2 ++ dts/arm/nordic/nrf9131_laca.dtsi | 1 + dts/arm/nordic/nrf9131ns_laca.dtsi | 1 + dts/arm/nordic/nrf9151_laca.dtsi | 1 + dts/arm/nordic/nrf9151ns_laca.dtsi | 1 + dts/arm/nordic/nrf9160_sica.dtsi | 1 + dts/arm/nordic/nrf9160ns_sica.dtsi | 1 + dts/arm/nordic/nrf9161_laca.dtsi | 1 + dts/arm/nordic/nrf9161ns_laca.dtsi | 1 + dts/arm/nordic/nrf91ns.dtsi | 2 ++ 38 files changed, 54 insertions(+) diff --git a/dts/arm/nordic/nrf51822.dtsi b/dts/arm/nordic/nrf51822.dtsi index 8f262909d61fd..5644ea2787bf4 100644 --- a/dts/arm/nordic/nrf51822.dtsi +++ b/dts/arm/nordic/nrf51822.dtsi @@ -47,6 +47,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; power: power@40000000 { diff --git a/dts/arm/nordic/nrf51822_qfaa.dtsi b/dts/arm/nordic/nrf51822_qfaa.dtsi index 2aeec68fd8529..b2ce647684e99 100644 --- a/dts/arm/nordic/nrf51822_qfaa.dtsi +++ b/dts/arm/nordic/nrf51822_qfaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(16)>; + ranges = <0x0 0x20000000 DT_SIZE_K(16)>; }; / { diff --git a/dts/arm/nordic/nrf51822_qfab.dtsi b/dts/arm/nordic/nrf51822_qfab.dtsi index 6f6818ac46074..d4327bb2b7559 100644 --- a/dts/arm/nordic/nrf51822_qfab.dtsi +++ b/dts/arm/nordic/nrf51822_qfab.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(16)>; + ranges = <0x0 0x20000000 DT_SIZE_K(16)>; }; / { diff --git a/dts/arm/nordic/nrf51822_qfac.dtsi b/dts/arm/nordic/nrf51822_qfac.dtsi index eae879189c0c2..f41890945e47c 100644 --- a/dts/arm/nordic/nrf51822_qfac.dtsi +++ b/dts/arm/nordic/nrf51822_qfac.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(32)>; + ranges = <0x0 0x20000000 DT_SIZE_K(32)>; }; / { diff --git a/dts/arm/nordic/nrf52805.dtsi b/dts/arm/nordic/nrf52805.dtsi index e940c7a2cdf2c..667f69836d05d 100644 --- a/dts/arm/nordic/nrf52805.dtsi +++ b/dts/arm/nordic/nrf52805.dtsi @@ -52,6 +52,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52805_caaa.dtsi b/dts/arm/nordic/nrf52805_caaa.dtsi index 285d21440599e..38daaff88d0eb 100644 --- a/dts/arm/nordic/nrf52805_caaa.dtsi +++ b/dts/arm/nordic/nrf52805_caaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(24)>; + ranges = <0x0 0x20000000 DT_SIZE_K(24)>; }; / { diff --git a/dts/arm/nordic/nrf52810.dtsi b/dts/arm/nordic/nrf52810.dtsi index c1e5f87631725..bdb592e3fe839 100644 --- a/dts/arm/nordic/nrf52810.dtsi +++ b/dts/arm/nordic/nrf52810.dtsi @@ -56,6 +56,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52810_qfaa.dtsi b/dts/arm/nordic/nrf52810_qfaa.dtsi index bbc76ab759719..344eca772f37e 100644 --- a/dts/arm/nordic/nrf52810_qfaa.dtsi +++ b/dts/arm/nordic/nrf52810_qfaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(24)>; + ranges = <0x0 0x20000000 DT_SIZE_K(24)>; }; / { diff --git a/dts/arm/nordic/nrf52811.dtsi b/dts/arm/nordic/nrf52811.dtsi index 33f6ac38747a3..3a793554c86f3 100644 --- a/dts/arm/nordic/nrf52811.dtsi +++ b/dts/arm/nordic/nrf52811.dtsi @@ -60,6 +60,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52811_qfaa.dtsi b/dts/arm/nordic/nrf52811_qfaa.dtsi index 17b387919dc87..18eacff062341 100644 --- a/dts/arm/nordic/nrf52811_qfaa.dtsi +++ b/dts/arm/nordic/nrf52811_qfaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(24)>; + ranges = <0x0 0x20000000 DT_SIZE_K(24)>; }; / { diff --git a/dts/arm/nordic/nrf52820.dtsi b/dts/arm/nordic/nrf52820.dtsi index 1073b973c22a7..88fc0c76dc5d6 100644 --- a/dts/arm/nordic/nrf52820.dtsi +++ b/dts/arm/nordic/nrf52820.dtsi @@ -59,6 +59,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52820_qdaa.dtsi b/dts/arm/nordic/nrf52820_qdaa.dtsi index a683ddcd2e614..585926d1a1660 100644 --- a/dts/arm/nordic/nrf52820_qdaa.dtsi +++ b/dts/arm/nordic/nrf52820_qdaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(32)>; + ranges = <0x0 0x20000000 DT_SIZE_K(32)>; }; / { diff --git a/dts/arm/nordic/nrf52832.dtsi b/dts/arm/nordic/nrf52832.dtsi index 09a651762db65..39a2dd5b0d3ee 100644 --- a/dts/arm/nordic/nrf52832.dtsi +++ b/dts/arm/nordic/nrf52832.dtsi @@ -56,6 +56,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52832_ciaa.dtsi b/dts/arm/nordic/nrf52832_ciaa.dtsi index 81bed18daf27a..28848a4d12131 100644 --- a/dts/arm/nordic/nrf52832_ciaa.dtsi +++ b/dts/arm/nordic/nrf52832_ciaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(64)>; + ranges = <0x0 0x20000000 DT_SIZE_K(64)>; }; / { diff --git a/dts/arm/nordic/nrf52832_qfaa.dtsi b/dts/arm/nordic/nrf52832_qfaa.dtsi index 81bed18daf27a..28848a4d12131 100644 --- a/dts/arm/nordic/nrf52832_qfaa.dtsi +++ b/dts/arm/nordic/nrf52832_qfaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(64)>; + ranges = <0x0 0x20000000 DT_SIZE_K(64)>; }; / { diff --git a/dts/arm/nordic/nrf52832_qfab.dtsi b/dts/arm/nordic/nrf52832_qfab.dtsi index faecc765efdf7..5c0d3dd8abdbe 100644 --- a/dts/arm/nordic/nrf52832_qfab.dtsi +++ b/dts/arm/nordic/nrf52832_qfab.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(32)>; + ranges = <0x0 0x20000000 DT_SIZE_K(32)>; }; / { diff --git a/dts/arm/nordic/nrf52833.dtsi b/dts/arm/nordic/nrf52833.dtsi index 87e6bccfb53d3..24addb6f3cf4e 100644 --- a/dts/arm/nordic/nrf52833.dtsi +++ b/dts/arm/nordic/nrf52833.dtsi @@ -60,6 +60,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52833_qdaa.dtsi b/dts/arm/nordic/nrf52833_qdaa.dtsi index 64462d29269bb..2c4ebaa0014ab 100644 --- a/dts/arm/nordic/nrf52833_qdaa.dtsi +++ b/dts/arm/nordic/nrf52833_qdaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(128)>; + ranges = <0x0 0x20000000 DT_SIZE_K(128)>; }; / { diff --git a/dts/arm/nordic/nrf52833_qiaa.dtsi b/dts/arm/nordic/nrf52833_qiaa.dtsi index 6ab9a4f1e6eb7..2b15451b3306c 100644 --- a/dts/arm/nordic/nrf52833_qiaa.dtsi +++ b/dts/arm/nordic/nrf52833_qiaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(128)>; + ranges = <0x0 0x20000000 DT_SIZE_K(128)>; }; / { diff --git a/dts/arm/nordic/nrf52840.dtsi b/dts/arm/nordic/nrf52840.dtsi index c0a2545f01378..77e70fa85f114 100644 --- a/dts/arm/nordic/nrf52840.dtsi +++ b/dts/arm/nordic/nrf52840.dtsi @@ -56,6 +56,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@40000000 { diff --git a/dts/arm/nordic/nrf52840_qfaa.dtsi b/dts/arm/nordic/nrf52840_qfaa.dtsi index 6d549a45d1ddc..9c4b70a10d0b8 100644 --- a/dts/arm/nordic/nrf52840_qfaa.dtsi +++ b/dts/arm/nordic/nrf52840_qfaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf52840_qiaa.dtsi b/dts/arm/nordic/nrf52840_qiaa.dtsi index 7986ab41fd6a3..3ad3537a05d7b 100644 --- a/dts/arm/nordic/nrf52840_qiaa.dtsi +++ b/dts/arm/nordic/nrf52840_qiaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; &power { diff --git a/dts/arm/nordic/nrf5340_cpuapp.dtsi b/dts/arm/nordic/nrf5340_cpuapp.dtsi index 2dca938eaad66..0b407935601ed 100644 --- a/dts/arm/nordic/nrf5340_cpuapp.dtsi +++ b/dts/arm/nordic/nrf5340_cpuapp.dtsi @@ -54,6 +54,8 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; peripheral@50000000 { diff --git a/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi b/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi index 76a2af386623b..cd9983d949ecd 100644 --- a/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi +++ b/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(512)>; + ranges = <0x0 0x20000000 DT_SIZE_K(512)>; }; / { diff --git a/dts/arm/nordic/nrf5340_cpuappns.dtsi b/dts/arm/nordic/nrf5340_cpuappns.dtsi index 763e9ca7839b7..8e4aa44aa2600 100644 --- a/dts/arm/nordic/nrf5340_cpuappns.dtsi +++ b/dts/arm/nordic/nrf5340_cpuappns.dtsi @@ -37,6 +37,8 @@ soc { sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; peripheral@40000000 { diff --git a/dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi b/dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi index 37d6a605556ef..6e18f646977d1 100644 --- a/dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi +++ b/dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(512)>; + ranges = <0x0 0x20000000 DT_SIZE_K(512)>; }; / { diff --git a/dts/arm/nordic/nrf5340_cpunet.dtsi b/dts/arm/nordic/nrf5340_cpunet.dtsi index 5010f801e0c01..94e93782fe317 100644 --- a/dts/arm/nordic/nrf5340_cpunet.dtsi +++ b/dts/arm/nordic/nrf5340_cpunet.dtsi @@ -48,11 +48,15 @@ sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; sram1: memory@21000000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "SRAM1"; + #address-cells = <1>; + #size-cells = <1>; }; clock: clock@41005000 { diff --git a/dts/arm/nordic/nrf5340_cpunet_qkaa.dtsi b/dts/arm/nordic/nrf5340_cpunet_qkaa.dtsi index e9948125ba894..be16eedfc5296 100644 --- a/dts/arm/nordic/nrf5340_cpunet_qkaa.dtsi +++ b/dts/arm/nordic/nrf5340_cpunet_qkaa.dtsi @@ -13,10 +13,12 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(512)>; + ranges = <0x0 0x20000000 DT_SIZE_K(512)>; }; &sram1 { reg = <0x21000000 DT_SIZE_K(64)>; + ranges = <0x0 0x21000000 DT_SIZE_K(64)>; }; / { diff --git a/dts/arm/nordic/nrf91.dtsi b/dts/arm/nordic/nrf91.dtsi index 2ef4b9bbab20c..6d03f9d6d7529 100644 --- a/dts/arm/nordic/nrf91.dtsi +++ b/dts/arm/nordic/nrf91.dtsi @@ -34,6 +34,8 @@ soc { sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; peripheral@50000000 { diff --git a/dts/arm/nordic/nrf9131_laca.dtsi b/dts/arm/nordic/nrf9131_laca.dtsi index 77fe73c22af66..30c526af5d32e 100644 --- a/dts/arm/nordic/nrf9131_laca.dtsi +++ b/dts/arm/nordic/nrf9131_laca.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9131ns_laca.dtsi b/dts/arm/nordic/nrf9131ns_laca.dtsi index 6ab80a842a33c..8426efcde26a8 100644 --- a/dts/arm/nordic/nrf9131ns_laca.dtsi +++ b/dts/arm/nordic/nrf9131ns_laca.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9151_laca.dtsi b/dts/arm/nordic/nrf9151_laca.dtsi index 77fe73c22af66..30c526af5d32e 100644 --- a/dts/arm/nordic/nrf9151_laca.dtsi +++ b/dts/arm/nordic/nrf9151_laca.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9151ns_laca.dtsi b/dts/arm/nordic/nrf9151ns_laca.dtsi index 6ab80a842a33c..8426efcde26a8 100644 --- a/dts/arm/nordic/nrf9151ns_laca.dtsi +++ b/dts/arm/nordic/nrf9151ns_laca.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9160_sica.dtsi b/dts/arm/nordic/nrf9160_sica.dtsi index 6bbe048277c12..e00d03fb5afc0 100644 --- a/dts/arm/nordic/nrf9160_sica.dtsi +++ b/dts/arm/nordic/nrf9160_sica.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9160ns_sica.dtsi b/dts/arm/nordic/nrf9160ns_sica.dtsi index 12ec1fcbc8e07..a10a5df325c92 100644 --- a/dts/arm/nordic/nrf9160ns_sica.dtsi +++ b/dts/arm/nordic/nrf9160ns_sica.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9161_laca.dtsi b/dts/arm/nordic/nrf9161_laca.dtsi index 77fe73c22af66..30c526af5d32e 100644 --- a/dts/arm/nordic/nrf9161_laca.dtsi +++ b/dts/arm/nordic/nrf9161_laca.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf9161ns_laca.dtsi b/dts/arm/nordic/nrf9161ns_laca.dtsi index 6ab80a842a33c..8426efcde26a8 100644 --- a/dts/arm/nordic/nrf9161ns_laca.dtsi +++ b/dts/arm/nordic/nrf9161ns_laca.dtsi @@ -13,6 +13,7 @@ &sram0 { reg = <0x20000000 DT_SIZE_K(256)>; + ranges = <0x0 0x20000000 DT_SIZE_K(256)>; }; / { diff --git a/dts/arm/nordic/nrf91ns.dtsi b/dts/arm/nordic/nrf91ns.dtsi index e44bbcde0a433..f4d88a6e635cd 100644 --- a/dts/arm/nordic/nrf91ns.dtsi +++ b/dts/arm/nordic/nrf91ns.dtsi @@ -35,6 +35,8 @@ soc { sram0: memory@20000000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; }; peripheral@40000000 { From f1e18c5e928c04f5a459bfddec4d5d70c5cb5720 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 17 Oct 2025 12:17:30 +0100 Subject: [PATCH 0010/1450] dts: vendor: nordic: nrf91: Fix SRAM partitioning Uses the correct way to partition memory as per the linux binding, also fixes names which were not compliant with the zephyr devicetree guidelines Signed-off-by: Jamie McCrae --- dts/vendor/nordic/nrf91xx_partition.dtsi | 31 +++++++++++------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/dts/vendor/nordic/nrf91xx_partition.dtsi b/dts/vendor/nordic/nrf91xx_partition.dtsi index dd98ce62f8e6f..89bc968a67d77 100644 --- a/dts/vendor/nordic/nrf91xx_partition.dtsi +++ b/dts/vendor/nordic/nrf91xx_partition.dtsi @@ -94,7 +94,7 @@ }; }; -/ { +&sram0 { /* * Default SRAM planning when building for nRF91xx with * ARM TrustZone-M support @@ -104,29 +104,26 @@ * - 40 kB SRAM reserved for and used by the modem library (sram0_ns_modem). * - 128 kB allocated to the application (sram0_ns_app). */ - reserved-memory { + sram0_s: sram@0 { + /* Secure image memory */ + reg = <0x0 DT_SIZE_K(88)>; + }; + + sram0_ns: sram@16000 { + /* Non-Secure image memory */ + reg = <0x16000 DT_SIZE_K(168)>; #address-cells = <1>; #size-cells = <1>; - ranges; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 DT_SIZE_K(88)>; - }; - - sram0_ns: image_ns@20016000 { - /* Non-Secure image memory */ - reg = <0x20016000 DT_SIZE_K(168)>; - }; + ranges = <0x0 0x16000 DT_SIZE_K(168)>; - sram0_ns_modem: image_ns_modem@20016000 { + sram0_ns_modem: sram@0 { /* Modem (shared) memory */ - reg = <0x20016000 DT_SIZE_K(40)>; + reg = <0x0 DT_SIZE_K(40)>; }; - sram0_ns_app: image_ns_app@20020000 { + sram0_ns_app: sram@a000 { /* Non-Secure application memory */ - reg = <0x20020000 DT_SIZE_K(128)>; + reg = <0xa000 DT_SIZE_K(128)>; }; }; }; From dd5a3f1a3e47983614d2665662f3af0f4710e910 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 17 Oct 2025 12:21:00 +0100 Subject: [PATCH 0011/1450] dts: vendor: nordic: nrf5340: Fix SRAM partitioning Uses the correct way to partition memory as per the linux binding, also fixes names which were not compliant with the zephyr devicetree guidelines Signed-off-by: Jamie McCrae --- .../nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts | 8 ++-- .../nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts | 7 +++- .../nordic/nrf5340_shared_sram_partition.dtsi | 14 +++---- dts/vendor/nordic/nrf5340_sram_partition.dtsi | 37 +++++++++---------- .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpunet.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 5 ++- .../nrf5340dk_nrf5340_cpuapp_icbmsg.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpunet.overlay | 5 ++- .../nrf5340dk_nrf5340_cpunet_icbmsg.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpunet.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpunet.overlay | 5 ++- .../boards/nrf5340dk_nrf5340_cpuapp.overlay | 4 +- .../boards/nrf5340dk_nrf5340_cpunet.overlay | 4 +- 16 files changed, 78 insertions(+), 46 deletions(-) diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts index 98447e569938f..32ed9916a382d 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts @@ -16,7 +16,6 @@ /* We need to remove aliases to nodes we delete */ aliases { - /delete-property/ sram-0; /delete-property/ i2c-0; /delete-property/ spi-0; /delete-property/ i2c-1; @@ -48,8 +47,6 @@ }; soc { - /delete-node/ memory@20000000; - peripheral@50000000 { /delete-node/ dcnf@0; /delete-node/ oscillator@4000; @@ -110,6 +107,11 @@ }; }; +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; + ranges = <0x0 0x20000000 DT_SIZE_K(512)>; +}; + &gpiote { status = "okay"; }; diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 317aff9cc00d1..567e87869d393 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -16,7 +16,6 @@ /* We need to remove aliases to nodes we delete */ aliases { - /delete-property/ sram-0; /delete-property/ sram-1; /delete-property/ wdt-0; /delete-property/ i2c-0; @@ -33,7 +32,6 @@ }; soc { - /delete-node/ memory@20000000; /delete-node/ memory@21000000; /delete-node/ watchdog@4100b000; /delete-node/ i2c@41013000; @@ -70,6 +68,11 @@ }; }; +&sram0 { + reg = <0x20000000 DT_SIZE_K(512)>; + ranges = <0x0 0x20000000 DT_SIZE_K(512)>; +}; + &gpiote { status = "okay"; }; diff --git a/dts/vendor/nordic/nrf5340_shared_sram_partition.dtsi b/dts/vendor/nordic/nrf5340_shared_sram_partition.dtsi index a5dc3489e893e..980a6a0f3b7bf 100644 --- a/dts/vendor/nordic/nrf5340_shared_sram_partition.dtsi +++ b/dts/vendor/nordic/nrf5340_shared_sram_partition.dtsi @@ -21,15 +21,11 @@ chosen { zephyr,ipc_shm = &sram0_shared; }; +}; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* Last 64 kB of sram0 */ - reg = <0x20070000 0x10000>; - }; +&sram0 { + sram0_shared: sram@70000 { + /* Last 64 kB of sram0 */ + reg = <0x70000 0x10000>; }; }; diff --git a/dts/vendor/nordic/nrf5340_sram_partition.dtsi b/dts/vendor/nordic/nrf5340_sram_partition.dtsi index db1d9dd4f1603..57f5f3de72e2d 100644 --- a/dts/vendor/nordic/nrf5340_sram_partition.dtsi +++ b/dts/vendor/nordic/nrf5340_sram_partition.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/ { +&sram0 { /* Default SRAM planning when building for nRF5340 with ARM TF-M support * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) * - Upper 256 kB allocated to Non-Secure image (sram0_ns) @@ -13,29 +13,26 @@ * - 64 kB allocated to shared memory (sram0_shared). * (See nrf5340_shared_sram_partition.dtsi) */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - reg = <0x20000000 DT_SIZE_K(448)>; - }; + sram0_image: sram@0 { + /* Zephyr image(s) memory */ + reg = <0x20000000 DT_SIZE_K(448)>; + }; - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 0x40000>; - }; + sram0_s: sram@20000000 { + /* Secure image memory */ + reg = <0x20000000 0x40000>; + }; - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - reg = <0x20040000 0x40000>; - }; + sram0_ns: sram@20040000 { + /* Non-Secure image memory */ + reg = <0x20040000 0x40000>; + ranges = <0x0 0x20040000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; - sram0_ns_app: image_ns_app@20040000 { + sram0_ns_app: sram@0 { /* Non-Secure image memory */ - reg = <0x20040000 0x30000>; + reg = <0x0 0x30000>; }; }; }; diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.overlay index f782bdd85784c..cedc6ffffd2f2 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -4,13 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_tx: memory@20070000 { reg = <0x20070000 0x0800>; diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.overlay index ac222a9fb7840..5df9e30bd8aa1 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -4,13 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_rx: memory@20070000 { reg = <0x20070000 0x0800>; diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.overlay index 216561b349be0..c0381229f9990 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -4,13 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0_tx: memory@20070000 { reg = <0x20070000 0x4000>; diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp_icbmsg.overlay b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp_icbmsg.overlay index 2d85fbbf79c1b..bf5df3e3881dd 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp_icbmsg.overlay +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf5340dk_nrf5340_cpuapp_icbmsg.overlay @@ -4,13 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0_tx: memory@20070000 { reg = <0x20070000 0x4000>; diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.overlay index 13da5a1fd44ab..63e1d6a03a080 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.overlay +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -4,13 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0_rx: memory@20070000 { reg = <0x20070000 0x4000>; diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet_icbmsg.overlay b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet_icbmsg.overlay index 6247ed812aa83..39f513954ffbf 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet_icbmsg.overlay +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf5340dk_nrf5340_cpunet_icbmsg.overlay @@ -4,13 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0_rx: memory@20070000 { reg = <0x20070000 0x4000>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.overlay index f07f75fc9a1a7..dfc4fb164defe 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -6,13 +6,16 @@ #include +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0: memory@20070000 { reg = <0x20070000 0x8000>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.overlay index 2d2297aede51b..cc0f3d7fdb35c 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -6,13 +6,16 @@ #include +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0: memory@20070000 { reg = <0x20070000 0x8000>; diff --git a/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay index c0a84fcb827bf..e58185ee90e46 100644 --- a/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -6,6 +6,8 @@ #include +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; @@ -13,7 +15,8 @@ }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0: memory@20070000 { reg = <0x20070000 0x8000>; diff --git a/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.overlay index 9205396f534d6..7179eb9dff6da 100644 --- a/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.overlay +++ b/samples/subsys/logging/multidomain/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -6,6 +6,8 @@ #include +/delete-node/ &sram0_shared; + / { chosen { /delete-property/ zephyr,ipc_shm; @@ -13,7 +15,8 @@ }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_ipc0: memory@20070000 { reg = <0x20070000 0x8000>; diff --git a/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay index d87bb33b3b314..b5c552f345718 100644 --- a/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -5,6 +5,7 @@ */ /delete-node/ &ipc0; +/delete-node/ &sram0_shared; / { chosen { @@ -13,7 +14,8 @@ }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_tx: memory@20070000 { reg = <0x20070000 0x8000>; diff --git a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay index 1ea1c1a27712c..2e38e5040cbbd 100644 --- a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay +++ b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -5,6 +5,7 @@ */ /delete-node/ &ipc0; +/delete-node/ &sram0_shared; / { chosen { @@ -12,7 +13,8 @@ }; reserved-memory { - /delete-node/ memory@20070000; + #address-cells = <1>; + #size-cells = <1>; sram_rx: memory@20070000 { reg = <0x20070000 0x8000>; From 0ffef90a01f3881777942c569ed6a0c3e6e39dd7 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 27 Oct 2025 09:53:22 +0000 Subject: [PATCH 0012/1450] tests: ipc: ipc_session: Correct name from sample to test This wrongly displayed in CI as a sample failing, when it is a test and not a sample, this changes the name to have test in it Signed-off-by: Jamie McCrae --- tests/subsys/ipc/ipc_sessions/testcase.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/subsys/ipc/ipc_sessions/testcase.yaml b/tests/subsys/ipc/ipc_sessions/testcase.yaml index a4d34a394dd8f..b7dcb84c8f179 100644 --- a/tests/subsys/ipc/ipc_sessions/testcase.yaml +++ b/tests/subsys/ipc/ipc_sessions/testcase.yaml @@ -8,12 +8,12 @@ common: harness: ztest tests: - sample.ipc.ipc_sessions.nrf5340dk: + test.ipc.ipc_sessions.nrf5340dk: platform_allow: - nrf5340dk/nrf5340/cpuapp integration_platforms: - nrf5340dk/nrf5340/cpuapp - sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpurad: + test.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpurad: platform_allow: - nrf54h20dk/nrf54h20/cpuapp integration_platforms: @@ -21,7 +21,7 @@ tests: extra_args: - CONFIG_IPC_TEST_SKIP_CORE_RESET=y - CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y - sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr: + test.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr: platform_allow: - nrf54h20dk/nrf54h20/cpuapp integration_platforms: @@ -29,7 +29,7 @@ tests: extra_args: - FILE_SUFFIX=cpuppr - ipc_sessions_SNIPPET=nordic-ppr - sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_no_unbound_cpuppr: + test.ipc.ipc_sessions.nrf54h20dk_cpuapp_no_unbound_cpuppr: platform_allow: - nrf54h20dk/nrf54h20/cpuapp integration_platforms: @@ -39,7 +39,7 @@ tests: - ipc_sessions_SNIPPET=nordic-ppr - CONFIG_IPC_TEST_SKIP_UNBOUND=y - CONFIG_IPC_SERVICE_BACKEND_ICMSG_V1=y - sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr_no_unbound: + test.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr_no_unbound: platform_allow: - nrf54h20dk/nrf54h20/cpuapp integration_platforms: From b6d45e1def47aa74ea3328603632b8f6d74c1ba6 Mon Sep 17 00:00:00 2001 From: Chris Friedt Date: Mon, 27 Oct 2025 12:34:00 -0400 Subject: [PATCH 0013/1450] testsuite: coverage: use correct path to fnmatch.h The minimal libc does not include `fnmatch.h` in its default search path. This causes an issue when running coverage in CI as shown here. https://github.com/zephyrproject-rtos/zephyr/actions/runs/18839500380/\ job/53748166725 That would technically be fixed with #97855 as well. Testing Done: ``` west twister -c -p qemu_x86/atom -s kernel.pending.minimallibc --coverage\ --coverage-tool gcovr ``` Signed-off-by: Chris Friedt --- subsys/testsuite/coverage/coverage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/testsuite/coverage/coverage.c b/subsys/testsuite/coverage/coverage.c index f189a720e8e95..9b9fcc632cb5c 100644 --- a/subsys/testsuite/coverage/coverage.c +++ b/subsys/testsuite/coverage/coverage.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include "coverage.h" #include #include From be7c2e81cdca11155c557aee2fc6f1877b14a6f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Thu, 16 Oct 2025 18:28:32 +0200 Subject: [PATCH 0014/1450] scripts: gen_boards_catalog.py: add verbose flag to Twister MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass verbose flag to Twister to get better insights into what boards are being built and see progress. Signed-off-by: Benjamin Cabé --- doc/_scripts/gen_boards_catalog.py | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/_scripts/gen_boards_catalog.py b/doc/_scripts/gen_boards_catalog.py index 5fcddddbc176f..96a314c57ef6d 100755 --- a/doc/_scripts/gen_boards_catalog.py +++ b/doc/_scripts/gen_boards_catalog.py @@ -207,6 +207,7 @@ def run_twister_cmake_only(outdir, vendor_filter): *[arg for path in EDT_PICKLE_PATHS for arg in ('--keep-artifacts', path)], *[arg for path in RUNNERS_YAML_PATHS for arg in ('--keep-artifacts', path)], "--cmake-only", + "-v", "--outdir", str(outdir), ] From 4ea4262ab8dfb15abcc314e324b831f7b0b03e4b Mon Sep 17 00:00:00 2001 From: David Leach Date: Mon, 27 Oct 2025 18:45:09 -0500 Subject: [PATCH 0015/1450] samples: usb: uvc: fix target sample filters for board specific overlays Recent addition of UVC Video encoder added sample targets to the sample without the proper filter to ensure twister didn't try to automatically build the sample target. Not all boards have the zephyr_h264enc and zephyr_h264enc in their device tree. Fixes #98275 Signed-off-by: David Leach --- samples/subsys/usb/uvc/sample.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/samples/subsys/usb/uvc/sample.yaml b/samples/subsys/usb/uvc/sample.yaml index 5000b964f509c..558c0c8ee219e 100644 --- a/samples/subsys/usb/uvc/sample.yaml +++ b/samples/subsys/usb/uvc/sample.yaml @@ -34,8 +34,8 @@ tests: extra_configs: - CONFIG_VIDEO_ENCODER_H264=y extra_args: - - EXTRA_DTC_OVERLAY_FILE="app_h264enc.overlay" - - SHIELD=st_b_cams_imx_mb1854 + - platform:stm32n6570_dk/stm32n657xx/sb:EXTRA_DTC_OVERLAY_FILE="app_h264enc.overlay" + - platform:stm32n6570_dk/stm32n657xx/sb:SHIELD=st_b_cams_imx_mb1854 filter: dt_chosen_enabled("zephyr,camera") integration_platforms: - stm32n6570_dk/stm32n657xx/sb @@ -46,8 +46,8 @@ tests: extra_configs: - CONFIG_VIDEO_ENCODER_JPEG=y extra_args: - - EXTRA_DTC_OVERLAY_FILE="app_jpegenc.overlay" - - SHIELD=st_b_cams_imx_mb1854 + - platform:stm32n6570_dk/stm32n657xx/sb:EXTRA_DTC_OVERLAY_FILE="app_jpegenc.overlay" + - platform:stm32n6570_dk/stm32n657xx/sb:SHIELD=st_b_cams_imx_mb1854 filter: dt_chosen_enabled("zephyr,camera") integration_platforms: - stm32n6570_dk/stm32n657xx/sb From 79f26e4bbaf6e449cd20bbb3c8b761037af71362 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Mon, 27 Oct 2025 18:29:38 +0000 Subject: [PATCH 0016/1450] boards: espressif: esp32_devkitc: Duplicit record Remove duplicit string from list of supported peripherals. Signed-off-by: Marek Matej --- boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml index cee4ef8e7b725..a4fcb6e3bee69 100644 --- a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml @@ -14,7 +14,6 @@ supported: - uart - nvs - pwm - - dac - spi - counter - entropy From 169a92e2559036aeece20a5e1299ba450ca71a21 Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Mon, 27 Oct 2025 14:41:13 +0100 Subject: [PATCH 0017/1450] docs: security: vulnerabilities: Add CVE 2025 section title A section title for CVE reported in 2025 was missing. Signed-off-by: Pieter De Gendt --- doc/security/vulnerabilities.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index 4a3f528259b2e..9fb171ba10f4b 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1838,6 +1838,9 @@ This has been fixed in main for v4.0.0 - `PR 81370 fix for 3.7 `_ +CVE-2025 +======== + :cve:`2025-1673` ---------------- From 14bc6564bfd308578d60a05d8de483867db1831c Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 27 Oct 2025 14:39:45 +0100 Subject: [PATCH 0018/1450] tests: drivers: counter: maxim_ds3231: Add missing assert print param Add a missing assert print parameter. Signed-off-by: Alberto Escolar Piedras --- tests/drivers/counter/maxim_ds3231_api/src/test_counter.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/drivers/counter/maxim_ds3231_api/src/test_counter.c b/tests/drivers/counter/maxim_ds3231_api/src/test_counter.c index e2b8ad00495ab..4db7656ba0dd9 100644 --- a/tests/drivers/counter/maxim_ds3231_api/src/test_counter.c +++ b/tests/drivers/counter/maxim_ds3231_api/src/test_counter.c @@ -398,7 +398,7 @@ void test_multiple_alarms_instance(const struct device *dev) err = counter_set_top_value(dev, &top_cfg); zassert_equal(-ENOTSUP, err, - "%s: Counter failed to set top value: %d", dev->name); + "%s: Counter failed to set top value: %d", dev->name, err); k_sleep(K_USEC(3 * (uint32_t)counter_ticks_to_us(dev, alarm_cfg.ticks))); From bde6bdd1688f97617ed2dfde3304c62dc5c38308 Mon Sep 17 00:00:00 2001 From: Khoa Nguyen Date: Mon, 27 Oct 2025 07:08:52 +0000 Subject: [PATCH 0019/1450] drivers: flash: Fix Kconfig style for Renesas RA Flash-HP Kconfig Fix Kconfig style for Renesas RA Flash-HP Kconfig Signed-off-by: Khoa Nguyen --- drivers/flash/Kconfig.renesas_ra | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/flash/Kconfig.renesas_ra b/drivers/flash/Kconfig.renesas_ra index 72d38f1464b16..d9d78ac2696e6 100644 --- a/drivers/flash/Kconfig.renesas_ra +++ b/drivers/flash/Kconfig.renesas_ra @@ -20,7 +20,6 @@ if SOC_FLASH_RENESAS_RA_HP config FLASH_RENESAS_RA_HP_WRITE_PROTECT bool "Extended operation for flash write protection control" - default n help Enables flash extended operation to enable/disable flash write protection from external devices From 9096739a9fbd6576ea900f91c7a7088ea675c5d4 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 24 Oct 2025 11:26:56 +0200 Subject: [PATCH 0020/1450] boards: stm32n6570_dk: Add link to Zephyr computer vision application Put a link to the newly available Zephyr based People detection application. Signed-off-by: Erwan Gouriou --- boards/st/stm32n6570_dk/doc/index.rst | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/boards/st/stm32n6570_dk/doc/index.rst b/boards/st/stm32n6570_dk/doc/index.rst index 31349bc7092b3..3ba9e3a8af192 100644 --- a/boards/st/stm32n6570_dk/doc/index.rst +++ b/boards/st/stm32n6570_dk/doc/index.rst @@ -27,7 +27,7 @@ programmer for the STM32 MCU, with a USB Virtual COM port bridge and the compreh Hardware ******** -- STM32N657X0H3Q Arm® Cortex®‑M55‑based microcontroller featuring ST Neural-ART Accelerator, +- STM32N657X0H3Q Arm® Cortex®‑M55‑based microcontroller featuring ST Neural-ART Accelerator™, H264 encoder, NeoChrom 2.5D GPU, and 4.2 Mbytes of contiguous SRAM, in a VFBGA264 package - 5" LCD module with capacitive touch panel - USB Type-C® with USB 2.0 HS interface, dual‑role‑power (DRP) @@ -73,6 +73,13 @@ STM32N6570-DK features a CSI camera module with a high-resolution 5‑Mpx CMOS R This camera outputs images in RAW Bayer format which require signal processing to be displayed with real life colors. This Image Signal Processing could be done with a dedicated `STM32 ISP module`_. +NPU +=== + +STM32N6570-DK also embeds the ST Neural-ART Accelerator |trade| as NPU engineered for power-efficient edge +AI applications, such as the `Zephyr computer vision application`_ which is available as a separate +Zephyr application. + USB === @@ -389,3 +396,6 @@ To do so, it is advised to use Twister's hardware map feature with the following .. _STM32 ISP module: https://github.com/stm32-hotspot/zephyr-stm32-mw-isp + +.. _Zephyr computer vision application: + https://github.com/stm32-hotspot/zephyr-stm32n6-ai-people-detection From 5a71080638faaf860a4289d17e1dddab226918b2 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 24 Oct 2025 14:38:44 +0200 Subject: [PATCH 0021/1450] boards: stm32n6570_dk: Clean up non-ASCII characters Cf documentation guidelines specific note. Signed-off-by: Erwan Gouriou --- boards/st/stm32n6570_dk/doc/index.rst | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/boards/st/stm32n6570_dk/doc/index.rst b/boards/st/stm32n6570_dk/doc/index.rst index 3ba9e3a8af192..a7685f556b7b1 100644 --- a/boards/st/stm32n6570_dk/doc/index.rst +++ b/boards/st/stm32n6570_dk/doc/index.rst @@ -4,22 +4,22 @@ Overview ******** The STM32N6570_DK Discovery kit is a complete demonstration and development platform -for the Arm® Cortex®‑M55 core‑based STM32N657X0H3Q microcontroller. +for the Arm |reg| Cortex |reg|‑M55 core‑based STM32N657X0H3Q microcontroller. The STM32N6570_DK Discovery kit includes a full range of hardware features that help -the user evaluate many peripherals, such as USB Type-C®, Octo‑SPI flash memory and -Hexadeca‑SPI PSRAM devices, Ethernet, camera module, LCD, microSD™, audio codec, +the user evaluate many peripherals, such as USB Type-C |reg|, Octo‑SPI flash memory and +Hexadeca‑SPI PSRAM devices, Ethernet, camera module, LCD, microSD |trade|, audio codec, digital microphones, ADC, flexible extension connectors, and user button. The four flexible extension connectors feature easy and unlimited expansion capabilities for specific applications such as wireless connectivity, analog applications, and sensors. The STM32N657X0H3Q microcontroller features one USB 2.0 high‑speed/full‑speed Device/Host/OTG controller, one USB 2.0 high‑speed/full‑speed Device/Host/OTG controller -with UCPD (USB Type-C® Power Delivery), one Ethernet with TSN (time-sensitive networking), +with UCPD (USB Type-C |reg| Power Delivery), one Ethernet with TSN (time-sensitive networking), four I2Cs, two I3Cs, six SPIs (of which four I2S‑capable), two SAIs, with four DMIC support, five USARTs, five UARTs (ISO78916 interface, LIN, IrDA, up to 12.5 Mbit/s), one LPUART, two SDMMCs (MMC version 4.0, CE-ATA version 1.0, and SD version 1.0.1), three CAN FD -with TTCAN capability, JTAG and SWD debugging support, and Embedded Trace Macrocell™ (ETM). +with TTCAN capability, JTAG and SWD debugging support, and Embedded Trace Macrocell |trade| (ETM). The STM32N6570_DK Discovery kit integrates an STLINK-V3EC embedded in-circuit debugger and programmer for the STM32 MCU, with a USB Virtual COM port bridge and the comprehensive MCU Package. @@ -27,10 +27,10 @@ programmer for the STM32 MCU, with a USB Virtual COM port bridge and the compreh Hardware ******** -- STM32N657X0H3Q Arm® Cortex®‑M55‑based microcontroller featuring ST Neural-ART Accelerator™, +- STM32N657X0H3Q Arm |reg| Cortex |reg|‑M55‑based microcontroller featuring ST Neural-ART Accelerator |trade|, H264 encoder, NeoChrom 2.5D GPU, and 4.2 Mbytes of contiguous SRAM, in a VFBGA264 package - 5" LCD module with capacitive touch panel -- USB Type-C® with USB 2.0 HS interface, dual‑role‑power (DRP) +- USB Type-C |reg| with USB 2.0 HS interface, dual‑role‑power (DRP) - USB Type-A with USB 2.0 HS interface, host, 0.5 A max - 1‑Gbit Ethernet with TSN (time-sensitive networking) compliant with IEEE‑802.3‑2002 - SAI audio codec @@ -41,15 +41,15 @@ Hardware - User, tamper, and reset push-buttons - Board connectors: - - USB Type-C® + - USB Type-C |reg| - USB Type-A - Ethernet RJ45 - Camera module - - microSD™ card + - microSD |trade| card - LCD - Stereo headset jack including analog microphone input - Audio MEMS daughterboard expansion connector - - ARDUINO® Uno R3 expansion connector + - ARDUINO |reg| Uno R3 expansion connector - STMod+ expansion connector - On-board STLINK-V3EC debugger/programmer with USB re-enumeration capability: From 603e4df64d841a4f2ca17177caab48db6c877030 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Fri, 24 Oct 2025 09:12:18 +0100 Subject: [PATCH 0022/1450] scripts: ci: check_compliance: Fix not checking CMakeLists.txt files Fixes an oversight of only checking files that are exactly named CMakeLists.txt - this includes the directory name, so that it actually checks any file in the tree with this name Signed-off-by: Jamie McCrae --- scripts/ci/check_compliance.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index fa71a25d4ed42..ceb605a3ed398 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -1859,7 +1859,7 @@ class CMakeStyle(ComplianceTest): def run(self): # Loop through added/modified files for fname in get_files(filter="d"): - if fname.endswith(".cmake") or fname == "CMakeLists.txt": + if fname.endswith(".cmake") or fname.endswith("CMakeLists.txt"): self.check_style(fname) def check_style(self, fname): From 4dd6354a3be6b6b7624fe505562fc608d62226a4 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 24 Oct 2025 09:36:08 +0200 Subject: [PATCH 0023/1450] drivers: i2c: i2c-priv: drop logging i2c_map_dt_bitrate uses LOG_ERR, however, one must define (or declare) a log module where to sink the logs. Since this sits on a header file, it creates a hidden include order dependency: you must include i2c-priv.h after registering or declaring a log module on your driver. Even worse, you are force to use logging in your drivers even if you do not want to! Signed-off-by: Gerard Marull-Paretas --- drivers/i2c/i2c-priv.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/i2c/i2c-priv.h b/drivers/i2c/i2c-priv.h index 9b85c85f95731..0ac92bda79d94 100644 --- a/drivers/i2c/i2c-priv.h +++ b/drivers/i2c/i2c-priv.h @@ -9,7 +9,6 @@ #include #include -#include #ifdef __cplusplus extern "C" { @@ -30,8 +29,6 @@ static inline uint32_t i2c_map_dt_bitrate(uint32_t bitrate) return I2C_SPEED_ULTRA << I2C_SPEED_SHIFT; } - LOG_ERR("Invalid I2C bit rate value"); - return 0; } From 6807fa35a1dc738e45524a33d572f7ac6453de3e Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Fri, 24 Oct 2025 09:43:24 +0200 Subject: [PATCH 0024/1450] drivers: i2c: i2c-priv: document i2c_map_dt_bitrate Document the helper function. Signed-off-by: Gerard Marull-Paretas --- drivers/i2c/i2c-priv.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/i2c/i2c-priv.h b/drivers/i2c/i2c-priv.h index 0ac92bda79d94..83bbb420ca9a3 100644 --- a/drivers/i2c/i2c-priv.h +++ b/drivers/i2c/i2c-priv.h @@ -14,6 +14,14 @@ extern "C" { #endif +/** + * @brief Map I2C bitrate from DT (in bps) to I2C interface encoding. + * + * @param bitrate I2C bitrate from DT (in bps) + * + * @retval bitrate I2C interface encoded bitrate. + * @retval 0 If given @p bitrate is not valid. + */ static inline uint32_t i2c_map_dt_bitrate(uint32_t bitrate) { switch (bitrate) { From b6e7a754d85abdf615a149e78a8273ae3512ceb1 Mon Sep 17 00:00:00 2001 From: Yongxu Wang Date: Fri, 24 Oct 2025 14:45:55 +0800 Subject: [PATCH 0025/1450] drivers: timer: mcux_lptmr: Fix prescaler bypass from devicetree The previous implementation had a logical error where the prescaler could never be bypassed due to incorrect use of BIT() macro: This patch fixes the issue by: 1. Remove BIT() wrapper from LPTMR_PRESCALER macro to use raw devicetree property value 2. Update bypass logic to check for zero value explicitly 3. Map DTS values to hardware register values correctly: - prescale_glitch_filter = 0 -> bypass prescaler - prescale_glitch_filter = n -> divide by 2^n, using register value (n-1) The devicetree semantic is now: - prescale_glitch_filter = <0>: No prescaling (bypass) - prescale_glitch_filter = <1>: Divide by 2 - prescale_glitch_filter = <2>: Divide by 4 - prescale_glitch_filter = <3>: Divide by 8 - And so on... Signed-off-by: Yongxu Wang --- drivers/timer/mcux_lptmr_timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/timer/mcux_lptmr_timer.c b/drivers/timer/mcux_lptmr_timer.c index 9e95503b44f00..6b5e3b0f14593 100644 --- a/drivers/timer/mcux_lptmr_timer.c +++ b/drivers/timer/mcux_lptmr_timer.c @@ -24,7 +24,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, /* Devicetree properties */ #define LPTMR_BASE ((LPTMR_Type *)(DT_INST_REG_ADDR(0))) #define LPTMR_CLK_SOURCE TO_LPTMR_CLK_SEL(DT_INST_PROP_OR(0, clk_source, 0)) -#define LPTMR_PRESCALER BIT(DT_INST_PROP_OR(0, prescale_glitch_filter, 0)) +#define LPTMR_PRESCALER DT_INST_PROP_OR(0, prescale_glitch_filter, 0) #define LPTMR_IRQN DT_INST_IRQN(0) #define LPTMR_IRQ_PRIORITY DT_INST_IRQ(0, priority) @@ -85,8 +85,8 @@ static int sys_clock_driver_init(void) config.timerMode = kLPTMR_TimerModeTimeCounter; config.enableFreeRunning = false; config.prescalerClockSource = LPTMR_CLK_SOURCE; - config.bypassPrescaler = !LPTMR_PRESCALER; - config.value = LPTMR_PRESCALER; + config.bypassPrescaler = (LPTMR_PRESCALER == 0); + config.value = (LPTMR_PRESCALER == 0) ? 0 : (LPTMR_PRESCALER - 1); LPTMR_Init(LPTMR_BASE, &config); From 40256a919dd96492307deafa5e0c8f22a47a1698 Mon Sep 17 00:00:00 2001 From: Pan Gao Date: Fri, 24 Oct 2025 12:30:42 +0900 Subject: [PATCH 0026/1450] net: l2: wifi: Fix btwt_setup command parameter count command btwt_setup maximum support max 12 optional parameters. Signed-off-by: Pan Gao --- subsys/net/l2/wifi/wifi_shell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 5aaabebf697a5..46f64dcb4f03b 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -3844,7 +3844,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_twt_ops, " The total number of '0, 1, ..., x' is session_num\n" "[-i, --iface=] : Interface index.\n", cmd_wifi_btwt_setup, - 13, 2), + 13, 12), SHELL_CMD_ARG(teardown, NULL, " Teardown a TWT flow:\n" "\n" "\n" From d3bae1d442d52eaed66dfc7e5ffb7f6fdbdbceee Mon Sep 17 00:00:00 2001 From: Lyle Zhu Date: Fri, 24 Oct 2025 13:14:46 +0800 Subject: [PATCH 0027/1450] tests: Bluetooth: SDP: Wait for DUT connect event before send any cmd There is a corner case found that the ACL connected event may be printed when script is sending shell command by calling function `shell.exec_command()`. The echo of shell command will mix with the ACL connected event message. The received message cannot be recognized by the function `shell.exec_command()`. It caused the timeout exception reported by the function `shell.exec_command()`. Before sending any shell commands, check the DUT connected event after the connection is established on script side. Signed-off-by: Lyle Zhu --- .../classic/sdp_c/pytest/test_sdp.py | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py b/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py index 9d9184bb5db77..d728af75d2855 100644 --- a/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py +++ b/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py @@ -375,6 +375,8 @@ async def sdp_ssa_discover_no_record(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "No SDP Record") @@ -408,6 +410,8 @@ async def sdp_ssa_discover_one_record(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -465,6 +469,8 @@ async def sdp_ssa_discover_two_records(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -535,6 +541,8 @@ async def sdp_ssa_discover_multiple_records(hci_port, shell, dut, address) -> No logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -568,6 +576,8 @@ async def sdp_ssa_discover_multiple_records_with_range(hci_port, shell, dut, add logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record with range SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID ~ # SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID shell.exec_command( @@ -636,6 +646,8 @@ async def sdp_ss_discover_no_record(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "No SDP Record") @@ -669,6 +681,8 @@ async def sdp_ss_discover_one_record(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -712,6 +726,8 @@ async def sdp_ss_discover_two_records(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -755,6 +771,8 @@ async def sdp_ss_discover_multiple_records(hci_port, shell, dut, address) -> Non logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -799,6 +817,8 @@ async def sdp_sa_discover_no_record(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command("sdp_client sa_discovery 00010001") found, lines = await wait_for_shell_response(dut, "No SDP Record") @@ -832,6 +852,8 @@ async def sdp_sa_discover_one_record(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command("sdp_client sa_discovery 00010001") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -886,6 +908,8 @@ async def sdp_sa_discover_two_records(hci_port, shell, dut, address) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command("sdp_client sa_discovery 00010002") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -949,6 +973,8 @@ async def sdp_sa_discover_multiple_records(hci_port, shell, dut, address) -> Non logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command("sdp_client sa_discovery 00010003") found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") @@ -982,6 +1008,8 @@ async def sdp_sa_discover_multiple_records_with_range(hci_port, shell, dut, addr logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record with range SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID ~ # SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID shell.exec_command( @@ -1062,6 +1090,8 @@ def on_app_connection_request(self, request) -> None: logger.error(f'Fail to connect to {target_address}!') raise e + await wait_for_shell_response(dut, "Connected:") + # Discover SDP Record shell.exec_command("sdp_client ssa_discovery_fail") found, lines = await wait_for_shell_response(dut, "test pass") From c581297f2c38855d2c1c70ef5a2a7862afce9da2 Mon Sep 17 00:00:00 2001 From: Kyle Bonnici Date: Fri, 24 Oct 2025 02:31:23 +0200 Subject: [PATCH 0028/1450] Compliance check: no dts-linter installed This PR fixes incorrect error message when dts-linter is not installed and provide a proper message instead of: `Failed to parse dts-linter JSON output: ...` Signed-off-by: Kyle Bonnici --- scripts/ci/check_compliance.py | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index ceb605a3ed398..7aade2d1fcd13 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -497,6 +497,23 @@ class DevicetreeLintingCheck(ComplianceTest): name = "DevicetreeLinting" doc = "See https://docs.zephyrproject.org/latest/contribute/style/devicetree.html for more details." + def ensure_npx(self) -> bool: + try: + # --no prevents npx from fetching from registry + subprocess.run( + ["npx", "--no", 'dts-linter', "--", "--version"], + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL, + check=True, + text=True + ) + return True + except subprocess.CalledProcessError: + return False + except FileNotFoundError: + # npx itself not installed + return False + def _parse_json_output(self, cmd, cwd=None): """Run command and parse single JSON output with issues array""" result = subprocess.run( @@ -524,6 +541,11 @@ def run(self): if file.endswith((".dts", ".dtsi", ".overlay")) ] + if not self.ensure_npx(): + self.skip( + 'dts-linter not installed. To run this check, ' + 'install Node.js and then run [npm ci] command inside ZEPHYR_BASE' + ) if not dts_files: self.skip('No DTS') @@ -574,7 +596,7 @@ def run(self): self.failure(f"dts-linter found issues:\n{stderr_output}") else: self.failure("dts-linter failed with no output. " - "Make sure you install Node.JS and then run npm ci inside ZEPHYR_BASE") + "Make sure you install Node.js and then run npm ci inside ZEPHYR_BASE") except RuntimeError as ex: self.failure(f"{ex}") From 8ed51c0bdca62e1d696a420229b5dc63557aa22a Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Thu, 23 Oct 2025 23:52:17 +0100 Subject: [PATCH 0029/1450] boards: ESP32 related boards documentation fix Providing documentation update for ESP32 related boards that was missed during the first round. Signed-off-by: Marek Matej --- boards/pcbcupid/glyph_c6/doc/index.rst | 109 +---------------------- boards/rakwireless/rak3112/doc/index.rst | 30 +++---- boards/weact/esp32c3_mini/doc/index.rst | 48 ++-------- boards/weact/esp32c6_mini/doc/index.rst | 106 ++-------------------- boards/weact/esp32s3_mini/doc/index.rst | 76 ++-------------- 5 files changed, 39 insertions(+), 330 deletions(-) diff --git a/boards/pcbcupid/glyph_c6/doc/index.rst b/boards/pcbcupid/glyph_c6/doc/index.rst index 3fe1085f97a56..fc35f25182dce 100644 --- a/boards/pcbcupid/glyph_c6/doc/index.rst +++ b/boards/pcbcupid/glyph_c6/doc/index.rst @@ -12,78 +12,12 @@ For more information, check `Glyph-C6`_. Hardware ******** -ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the -802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security -features and multiple memory resources for IoT products. -It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, -and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. -It has a 320KB ROM, a 512KB SRAM, and works with external flash. - Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount glyph c6 on a breadboard. -ESP32-C6 includes the following features: - -- 32-bit core RISC-V microcontroller with a clock speed of up to 160 MHz -- 400 KB of internal RAM -- WiFi 802.11 ax 2.4GHz -- Fully compatible with IEEE 802.11b/g/n protocol -- Bluetooth LE: Bluetooth 5.3 certified -- Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna -- IEEE 802.15.4 (Zigbee and Thread) - -Digital interfaces: - -- 30x GPIOs (QFN40), or 22x GPIOs (QFN32) -- 2x UART -- 1x Low-power (LP) UART -- 1x General purpose SPI -- 1x I2C -- 1x Low-power (LP) I2C -- 1x I2S -- 1x Pulse counter -- 1x USB Serial/JTAG controller -- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) -- 1x SDIO 2.0 slave controller -- LED PWM controller, up to 6 channels -- 1x Motor control PWM (MCPWM) -- 1x Remote control peripehral -- 1x Parallel IO interface (PARLIO) -- General DMA controller (GDMA), with 3 transmit channels and 3 receive channels -- Event task matrix (ETM) - -Analog interfaces: - -- 1x 12-bit SAR ADCs, up to 7 channels -- 1x temperature sensor - -Timers: - -- 1x 52-bit system timer -- 1x 54-bit general-purpose timers -- 3x Watchdog timers -- 1x Analog watchdog timer - -Low Power: - -- Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash) -- Random number generator (RNG) - -Memory and Storage: - -- While the Glyph ESP32-C6 has 512KB onboard SRAM, it also relies on an external flash chip for program storage. - On this board, there is 4 MB of flash memory, which is shared between the code, file storage and OTA - -For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference -manual at `ESP32-C6 Technical Reference Manual`_. +.. include:: ../../../espressif/common/soc-esp32c6-features.rst + :start-after: espressif-soc-esp32c6-features Supported Features ================== @@ -93,16 +27,8 @@ Supported Features System Requirements ******************* -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements Programming and Debugging ************************* @@ -121,36 +47,9 @@ Debugging .. include:: ../../../espressif/common/openocd-debugging.rst :start-after: espressif-openocd-debugging -Low-Power CPU (LP CORE) -*********************** - -The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE). -The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus -interface for memory and peripheral access. - -The LP Core is in sleep mode by default. It has two application scenarios: - -- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations. -- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events. - -For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference -manual at `ESP32-C6 Technical Reference Manual`_. - -The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding -the following configuration to the project: - -.. code:: cfg - - CONFIG_ULP_COPROC_ENABLED=y - -See :zephyr:code-sample-category:`lp-core` folder as code reference. - References ********** .. target-notes:: .. _`Glyph-C6`: https://learn.pcbcupid.com/boards/glyph-c6/overview -.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf -.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/rakwireless/rak3112/doc/index.rst b/boards/rakwireless/rak3112/doc/index.rst index c7c4c592fb74b..eee0ebc1ff847 100644 --- a/boards/rakwireless/rak3112/doc/index.rst +++ b/boards/rakwireless/rak3112/doc/index.rst @@ -39,24 +39,19 @@ For more information about the RAK3112 stamp module: - `WisDuo RAK3112 Website`_ - `Espressif ESP32-S3 Website`_ +.. include:: ../../../espressif/common/soc-esp32s3-features.rst + :start-after: espressif-soc-esp32s3-features + Supported Features ================== .. zephyr:board-supported-hw:: -System requirements +System Requirements ******************* -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements Programming and Debugging ************************* @@ -69,13 +64,16 @@ Programming and Debugging .. include:: ../../../espressif/common/board-variants.rst :start-after: espressif-board-variants +Debugging +========= + +.. include:: ../../../espressif/common/openocd-debugging.rst + :start-after: espressif-openocd-debugging + References ********** .. target-notes:: -.. _WisDuo RAK3112 Website: - https://docs.rakwireless.com/Product-Categories/WisDuo/RAK3112-Module/Overview/ - -.. _Espressif ESP32-S3 Website: - https://www.espressif.com/en/products/socs/esp32-s3 +.. _`WisDuo RAK3112 Website`: https://docs.rakwireless.com/Product-Categories/WisDuo/RAK3112-Module/Overview/ +.. _`Espressif ESP32-S3 Website`: https://www.espressif.com/en/products/socs/esp32-s3 diff --git a/boards/weact/esp32c3_mini/doc/index.rst b/boards/weact/esp32c3_mini/doc/index.rst index bce8e2d05326d..d5a688c96304e 100644 --- a/boards/weact/esp32c3_mini/doc/index.rst +++ b/boards/weact/esp32c3_mini/doc/index.rst @@ -10,34 +10,8 @@ For more information, check `WeAct Studio ESP32-C3 Core Board`_. Hardware ******** -ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, -based on the open-source RISC-V architecture. - -The features include the following: - -- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz -- 400 KB of internal RAM -- 4 MB of internal flash (FH4 variant) -- 802.11b/g/n/e/i -- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh -- Various peripherals: - - - 12-bit ADC with up to 6 channels - - TWAI compatible with CAN bus 2.0 - - Temperature sensor - - 3x SPI - - 1x I2S - - 1x I2C - - 2x UART - - LED PWM with up to 6 channels - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- USB Serial/JTAG for flashing and debugging -- On-board blue LED (GPIO8) -- Boot button (GPIO9) - -For more information, check the datasheet at `ESP32-C3 Datasheet`_ or the technical reference -manual at `ESP32-C3 Technical Reference Manual`_. +.. include:: ../../../espressif/common/soc-esp32c3-features.rst + :start-after: espressif-soc-esp32c3-features Supported Features ================== @@ -47,16 +21,8 @@ Supported Features System Requirements ******************* -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements Programming and Debugging ************************* @@ -66,6 +32,9 @@ Programming and Debugging .. include:: ../../../espressif/common/building-flashing.rst :start-after: espressif-building-flashing +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ========= @@ -78,6 +47,3 @@ References .. target-notes:: .. _`WeAct Studio ESP32-C3 Core Board`: https://github.com/WeActStudio/WeActStudio.ESP32C3CoreBoard -.. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf -.. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/weact/esp32c6_mini/doc/index.rst b/boards/weact/esp32c6_mini/doc/index.rst index 1f3e3c8fee2d6..66dec982cbbb4 100644 --- a/boards/weact/esp32c6_mini/doc/index.rst +++ b/boards/weact/esp32c6_mini/doc/index.rst @@ -11,74 +11,11 @@ For more information, check `WeAct ESP32-C6 Mini`_. Hardware ******** -ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the -802.15.4 protocol. It consists of a high-performance (HP) 32-bit RISC-V processor, which can be -clocked up to 160 MHz, and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. -It has a 320KB ROM, a 512KB SRAM, and works with external flash. - The WeAct ESP32-C6 Mini is a compact board with the ESP32-C6FH4 chip directly mounted, featuring a 4 MB SPI flash. The board includes a USB Type-C connector, boot and reset buttons, and an RGB LED. -ESP32-C6FH4 is part of the ESP32-C6 series in a QFN32 (5x5 mm) package with in-package flash. - -Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. - -ESP32-C6 includes the following features: - -- 32-bit core RISC-V microcontroller with a clock speed of up to 160 MHz -- 400 KB of internal RAM -- WiFi 802.11 ax 2.4GHz -- Fully compatible with IEEE 802.11b/g/n protocol -- Bluetooth LE: Bluetooth 5.3 certified -- Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna -- IEEE 802.15.4 (Zigbee and Thread) - -Digital interfaces: - -- 22x GPIOs -- 2x UART -- 1x Low-power (LP) UART -- 1x SPI (SPI2) -- 1x I2C -- 1x Low-power (LP) I2C -- 1x I2S -- 1x Pulse counter -- 1x USB Serial/JTAG controller -- 1x TWAI® controllers, compatible with ISO 11898-1 (CAN Specification 2.0) -- 1x SDIO 2.0 slave controller -- LED PWM controller, up to 6 channels -- 1x Motor control PWM (MCPWM) -- 1x Remote control peripheral -- 1x Parallel IO interface (PARLIO) -- General DMA controller (GDMA), with 3 transmit channels and 3 receive channels -- Event task matrix (ETM) - -Analog interfaces: - -- 1x 12-bit SAR ADCs, up to 7 channels -- 1x temperature sensor - -Timers: - -- 1x 52-bit system timer -- 1x 54-bit general-purpose timers -- 3x Watchdog timers -- 1x Analog watchdog timer - -Low Power: - -- Four power modes: Active, Modem-sleep, Light-sleep, Deep-sleep - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash) -- Random number generator (RNG) - -For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference -manual at `ESP32-C6 Technical Reference Manual`_. +.. include:: ../../../espressif/common/soc-esp32c6-features.rst + :start-after: espressif-soc-esp32c6-features Supported Features ================== @@ -88,16 +25,8 @@ Supported Features System Requirements ******************* -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements Programming and Debugging ************************* @@ -107,39 +36,18 @@ Programming and Debugging .. include:: ../../../espressif/common/building-flashing.rst :start-after: espressif-building-flashing +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ========= .. include:: ../../../espressif/common/openocd-debugging.rst :start-after: espressif-openocd-debugging -Low-Power CPU (LP CORE) -*********************** - -The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE). -The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus -interface for memory and peripheral access. - -The LP Core is in sleep mode by default. It has two application scenarios: - -- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations. -- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events. - -The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding -the following configuration to the project: - -.. code:: cfg - - CONFIG_ULP_COPROC_ENABLED=y - -See :zephyr:code-sample-category:`lp-core` folder as code reference. - References ********** .. target-notes:: .. _`WeAct ESP32-C6 Mini`: https://github.com/WeActStudio/WeActStudio.ESP32C6-MINI -.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf -.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/weact/esp32s3_mini/doc/index.rst b/boards/weact/esp32s3_mini/doc/index.rst index 60ea100366588..8336f1c01529a 100644 --- a/boards/weact/esp32s3_mini/doc/index.rst +++ b/boards/weact/esp32s3_mini/doc/index.rst @@ -11,72 +11,17 @@ check `WeAct Studio ESP32-S3-MINI`_. Hardware ******** -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. WeAct Studio ESP32-S3-MINI includes the following features: -- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz - 4MB integrated Flash memory - 2MB integrated PSRAM -- 512KB of SRAM -- Wi-Fi 802.11b/g/n -- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate - Onboard RGB WS2812 LED (GPIO48) - BOOT button (GPIO0) - USB Type-C connector -Digital interfaces: - -- 36 programmable GPIOs -- 4x SPI -- 3x UART -- 2x I2C -- 2x I2S -- 1x RMT (TX/RX) -- LED PWM controller, up to 8 channels -- 1x full-speed USB OTG -- 1x USB Serial/JTAG controller -- 2x MCPWM -- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels -- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) -- Addressable RGB LED, driven by GPIO48. - -Analog interfaces: - -- 2x 12-bit SAR ADCs, up to 20 channels -- 1x temperature sensor -- 14x touch sensing IOs - -Timers: - -- 4x 54-bit general-purpose timers -- 1x 52-bit system timer -- 3x watchdog timers - -Low Power: - -- Power Management Unit with five power modes -- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) - -Asymmetric Multiprocessing (AMP) -******************************** - -WeAct Studio ESP32-S3-MINI supports dual-core execution allowing two different applications -to run on ESP32-S3 SoC. Each core can execute customized tasks in stand-alone mode -and/or exchange data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as reference. - -For more information, check the datasheet at `ESP32-S3 Datasheet`_ or the technical reference -manual at `ESP32-S3 Technical Reference Manual`_. +.. include:: ../../../espressif/common/soc-esp32s3-features.rst + :start-after: espressif-soc-esp32s3-features Supported Features ================== @@ -86,16 +31,8 @@ Supported Features System Requirements ******************* -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. +.. include:: ../../../espressif/common/system-requirements.rst + :start-after: espressif-system-requirements Programming and Debugging ************************* @@ -105,6 +42,9 @@ Programming and Debugging .. include:: ../../../espressif/common/building-flashing.rst :start-after: espressif-building-flashing +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ========= @@ -117,5 +57,3 @@ References .. target-notes:: .. _`WeAct Studio ESP32-S3-MINI`: https://github.com/WeActStudio/WeActStudio.ESP32S3-MINI/ -.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf From 4b4332ac1814ee675fdf25a32c313002d70918d4 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Tue, 21 Oct 2025 10:33:07 -0300 Subject: [PATCH 0030/1450] drivers: crypto: return -ENOTSUP when needed Make sure all crypto driver returns proper error when feature is not supported. Signed-off-by: Sylvio Alves --- drivers/crypto/crypto_ataes132a.c | 14 +++++++------- drivers/crypto/crypto_cc23x0.c | 14 +++++++------- drivers/crypto/crypto_it51xxx_sha.c | 4 ++-- drivers/crypto/crypto_it8xxx2_sha.c | 4 ++-- drivers/crypto/crypto_it8xxx2_sha_v2.c | 4 ++-- drivers/crypto/crypto_mchp_xec_symcr.c | 4 ++-- drivers/crypto/crypto_mtls_shim.c | 6 +++--- drivers/crypto/crypto_npcx_sha.c | 6 +++--- drivers/crypto/crypto_rts5912_sha.c | 2 +- drivers/crypto/crypto_smartbond.c | 2 +- drivers/crypto/crypto_stm32.c | 8 ++++---- drivers/crypto/crypto_stm32_hash.c | 4 ++-- 12 files changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/crypto/crypto_ataes132a.c b/drivers/crypto/crypto_ataes132a.c index 388c6dcfec6d2..1c78d3224cdb4 100644 --- a/drivers/crypto/crypto_ataes132a.c +++ b/drivers/crypto/crypto_ataes132a.c @@ -713,7 +713,7 @@ static int do_ccm_encrypt_mac(struct cipher_ctx *ctx, if (aead_op->ad != NULL || aead_op->ad_len != 0U) { LOG_ERR("Associated data is not supported."); - return -EINVAL; + return -ENOTSUP; } ataes132a_aes_ccm_encrypt(dev, key_id, &mac_mode, @@ -758,7 +758,7 @@ static int do_ccm_decrypt_auth(struct cipher_ctx *ctx, if (aead_op->ad != NULL || aead_op->ad_len != 0U) { LOG_ERR("Associated data is not supported."); - return -EINVAL; + return -ENOTSUP; } /* Normal Decryption Mode will only decrypt host generated packets */ @@ -835,18 +835,18 @@ static int ataes132a_session_setup(const struct device *dev, if (algo != CRYPTO_CIPHER_ALGO_AES) { LOG_ERR("ATAES132A unsupported algorithm"); - return -EINVAL; + return -ENOTSUP; } /*ATAES132A support I2C polling only*/ if (!(ctx->flags & CAP_SYNC_OPS)) { LOG_ERR("Async not supported by this driver"); - return -EINVAL; + return -ENOTSUP; } if (ctx->keylen != ATAES132A_AES_KEY_SIZE) { LOG_ERR("ATAES132A unsupported key size"); - return -EINVAL; + return -ENOTSUP; } if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) { @@ -859,7 +859,7 @@ static int ataes132a_session_setup(const struct device *dev, break; default: LOG_ERR("ATAES132A unsupported mode"); - return -EINVAL; + return -ENOTSUP; } } else { switch (mode) { @@ -871,7 +871,7 @@ static int ataes132a_session_setup(const struct device *dev, break; default: LOG_ERR("ATAES132A unsupported mode"); - return -EINVAL; + return -ENOTSUP; } } diff --git a/drivers/crypto/crypto_cc23x0.c b/drivers/crypto/crypto_cc23x0.c index f6f2d5efbac69..28caaf2eee6fa 100644 --- a/drivers/crypto/crypto_cc23x0.c +++ b/drivers/crypto/crypto_cc23x0.c @@ -985,24 +985,24 @@ static int crypto_cc23x0_session_setup(const struct device *dev, { if (ctx->flags & ~(CRYPTO_CC23_CAP)) { LOG_ERR("Unsupported feature"); - return -EINVAL; + return -ENOTSUP; } if (algo != CRYPTO_CIPHER_ALGO_AES) { LOG_ERR("Unsupported algo"); - return -EINVAL; + return -ENOTSUP; } if (mode != CRYPTO_CIPHER_MODE_ECB && mode != CRYPTO_CIPHER_MODE_CTR && mode != CRYPTO_CIPHER_MODE_CCM) { LOG_ERR("Unsupported mode"); - return -EINVAL; + return -ENOTSUP; } if (ctx->keylen != 16U) { LOG_ERR("%u key size is not supported", ctx->keylen); - return -EINVAL; + return -ENOTSUP; } if (!ctx->key.bit_stream) { @@ -1022,13 +1022,13 @@ static int crypto_cc23x0_session_setup(const struct device *dev, ctx->ops.ccm_crypt_hndlr = crypto_cc23x0_ccm_encrypt; break; default: - return -EINVAL; + return -ENOTSUP; } } else { switch (mode) { case CRYPTO_CIPHER_MODE_ECB: LOG_ERR("ECB decryption not supported by the hardware"); - return -EINVAL; + return -ENOTSUP; case CRYPTO_CIPHER_MODE_CTR: ctx->ops.ctr_crypt_hndlr = crypto_cc23x0_ctr; break; @@ -1036,7 +1036,7 @@ static int crypto_cc23x0_session_setup(const struct device *dev, ctx->ops.ccm_crypt_hndlr = crypto_cc23x0_ccm_decrypt; break; default: - return -EINVAL; + return -ENOTSUP; } } diff --git a/drivers/crypto/crypto_it51xxx_sha.c b/drivers/crypto/crypto_it51xxx_sha.c index bd20c29b25fac..855db84396e19 100644 --- a/drivers/crypto/crypto_it51xxx_sha.c +++ b/drivers/crypto/crypto_it51xxx_sha.c @@ -238,12 +238,12 @@ static int it51xxx_hash_begin_session(const struct device *dev, struct hash_ctx { if (algo != CRYPTO_HASH_ALGO_SHA256) { LOG_ERR("Unsupported algorithm"); - return -EINVAL; + return -ENOTSUP; } if (ctx->flags & ~(it51xxx_query_hw_caps(dev))) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } it51xxx_sha256_init(true); diff --git a/drivers/crypto/crypto_it8xxx2_sha.c b/drivers/crypto/crypto_it8xxx2_sha.c index 5ce174ab237ee..19e3514be00e6 100644 --- a/drivers/crypto/crypto_it8xxx2_sha.c +++ b/drivers/crypto/crypto_it8xxx2_sha.c @@ -188,12 +188,12 @@ static int it8xxx2_hash_begin_session(const struct device *dev, { if (algo != CRYPTO_HASH_ALGO_SHA256) { LOG_ERR("Unsupported algo"); - return -EINVAL; + return -ENOTSUP; } if (ctx->flags & ~(it8xxx2_query_hw_caps(dev))) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } it8xxx2_sha256_init(false); diff --git a/drivers/crypto/crypto_it8xxx2_sha_v2.c b/drivers/crypto/crypto_it8xxx2_sha_v2.c index 3098bf4b9b5e0..e2f334c96dc3c 100644 --- a/drivers/crypto/crypto_it8xxx2_sha_v2.c +++ b/drivers/crypto/crypto_it8xxx2_sha_v2.c @@ -308,12 +308,12 @@ static int it8xxx2_hash_begin_session(const struct device *dev, { if (algo != CRYPTO_HASH_ALGO_SHA256) { LOG_ERR("Unsupported algorithm"); - return -EINVAL; + return -ENOTSUP; } if (ctx->flags & ~(it8xxx2_query_hw_caps(dev))) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } it8xxx2_sha256_init(true); diff --git a/drivers/crypto/crypto_mchp_xec_symcr.c b/drivers/crypto/crypto_mchp_xec_symcr.c index 3d3ea836475f2..ac04126f6e2ec 100644 --- a/drivers/crypto/crypto_mchp_xec_symcr.c +++ b/drivers/crypto/crypto_mchp_xec_symcr.c @@ -405,13 +405,13 @@ static int xec_symcr_hash_session_begin(const struct device *dev, struct hash_ct if (ctx->flags & ~(MCHP_XEC_SYMCR_CAPS_SUPPORT)) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } rom_algo = lookup_hash_alg(algo); if (rom_algo == MCHP_ROM_HASH_ALG_NONE) { LOG_ERR("Unsupported algo %d", algo); - return -EINVAL; + return -ENOTSUP; } session_idx = mchp_xec_get_unused_session_index(data); diff --git a/drivers/crypto/crypto_mtls_shim.c b/drivers/crypto/crypto_mtls_shim.c index 2031e7d7c987b..eda094cdf72f4 100644 --- a/drivers/crypto/crypto_mtls_shim.c +++ b/drivers/crypto/crypto_mtls_shim.c @@ -341,7 +341,7 @@ static int mtls_session_setup(const struct device *dev, #endif mode != CRYPTO_CIPHER_MODE_ECB) { LOG_ERR("Unsupported mode"); - return -EINVAL; + return -ENOTSUP; } if (ctx->keylen != 16U) { @@ -541,7 +541,7 @@ static int mtls_hash_session_setup(const struct device *dev, if (ctx->flags & ~(MTLS_SUPPORT)) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } if ((algo != CRYPTO_HASH_ALGO_SHA224) && @@ -549,7 +549,7 @@ static int mtls_hash_session_setup(const struct device *dev, (algo != CRYPTO_HASH_ALGO_SHA384) && (algo != CRYPTO_HASH_ALGO_SHA512)) { LOG_ERR("Unsupported algo: %d", algo); - return -EINVAL; + return -ENOTSUP; } ctx_idx = mtls_get_unused_session_index(); diff --git a/drivers/crypto/crypto_npcx_sha.c b/drivers/crypto/crypto_npcx_sha.c index 65da0cb5dcf0f..b37d287467bd4 100644 --- a/drivers/crypto/crypto_npcx_sha.c +++ b/drivers/crypto/crypto_npcx_sha.c @@ -99,7 +99,7 @@ static int npcx_sha_compute(struct hash_ctx *ctx, struct hash_pkt *pkt, bool fin break; default: LOG_ERR("Unexpected algo: %d", npcx_session->algo); - return -EINVAL; + return -ENOTSUP; } if (!ctx->started) { @@ -140,13 +140,13 @@ static int npcx_hash_session_setup(const struct device *dev, struct hash_ctx *ct if (ctx->flags & ~(NPCX_HASH_CAPS_SUPPORT)) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } if ((algo != CRYPTO_HASH_ALGO_SHA256) && (algo != CRYPTO_HASH_ALGO_SHA384) && (algo != CRYPTO_HASH_ALGO_SHA512)) { LOG_ERR("Unsupported algo: %d", algo); - return -EINVAL; + return -ENOTSUP; } ctx_idx = npcx_get_unused_session_index(); diff --git a/drivers/crypto/crypto_rts5912_sha.c b/drivers/crypto/crypto_rts5912_sha.c index dc4ab4ec89e9e..7e9620aa33cb7 100644 --- a/drivers/crypto/crypto_rts5912_sha.c +++ b/drivers/crypto/crypto_rts5912_sha.c @@ -268,7 +268,7 @@ static int rts5912_hash_begin_session(const struct device *dev, struct hash_ctx rts5912_sha256_start(dev); break; default: - return -EINVAL; + return -ENOTSUP; } return 0; diff --git a/drivers/crypto/crypto_smartbond.c b/drivers/crypto/crypto_smartbond.c index 3861e74409aa4..f236472b9b9b0 100644 --- a/drivers/crypto/crypto_smartbond.c +++ b/drivers/crypto/crypto_smartbond.c @@ -384,7 +384,7 @@ static int crypto_smartbond_hash_set_algo(enum hash_algo algo) (0x1 << AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos)); break; default: - return -EINVAL; + return -ENOTSUP; } return 0; diff --git a/drivers/crypto/crypto_stm32.c b/drivers/crypto/crypto_stm32.c index b1c7cf59b03d5..d95499252d9c0 100644 --- a/drivers/crypto/crypto_stm32.c +++ b/drivers/crypto/crypto_stm32.c @@ -335,12 +335,12 @@ static int crypto_stm32_session_setup(const struct device *dev, if (ctx->flags & ~(CRYP_SUPPORT)) { LOG_ERR("Unsupported flag"); - return -EINVAL; + return -ENOTSUP; } if (algo != CRYPTO_CIPHER_ALGO_AES) { LOG_ERR("Unsupported algo"); - return -EINVAL; + return -ENOTSUP; } /* The CRYP peripheral supports the AES ECB, CBC, CTR, CCM and GCM @@ -356,7 +356,7 @@ static int crypto_stm32_session_setup(const struct device *dev, (mode != CRYPTO_CIPHER_MODE_CBC) && (mode != CRYPTO_CIPHER_MODE_CTR)) { LOG_ERR("Unsupported mode"); - return -EINVAL; + return -ENOTSUP; } /* The STM32F4 CRYP peripheral supports key sizes of 128, 192 and 256 @@ -368,7 +368,7 @@ static int crypto_stm32_session_setup(const struct device *dev, #endif (ctx->keylen != 32U)) { LOG_ERR("%u key size is not supported", ctx->keylen); - return -EINVAL; + return -ENOTSUP; } ctx_idx = crypto_stm32_get_unused_session_index(dev); diff --git a/drivers/crypto/crypto_stm32_hash.c b/drivers/crypto/crypto_stm32_hash.c index b563ed899cef8..dc0a761d7e6a4 100644 --- a/drivers/crypto/crypto_stm32_hash.c +++ b/drivers/crypto/crypto_stm32_hash.c @@ -72,7 +72,7 @@ static int stm32_hash_handler(struct hash_ctx *ctx, struct hash_pkt *pkt, bool f default: k_sem_give(&data->device_sem); LOG_ERR("Unsupported algorithm in handler: %d", session->algo); - return -EINVAL; + return -ENOTSUP; } k_sem_give(&data->device_sem); @@ -98,7 +98,7 @@ static int stm32_hash_begin_session(const struct device *dev, struct hash_ctx *c break; default: LOG_ERR("Unsupported hash algorithm: %d", algo); - return -EINVAL; + return -ENOTSUP; } ctx_idx = crypto_stm32_hash_get_unused_session_index(dev); From 998d9ab04f02a0d6ab57ee1b46fdf3f30a25df9e Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Tue, 21 Oct 2025 10:44:28 -0300 Subject: [PATCH 0031/1450] drivers: crypto: expand mbedTLS shim driver capabilities Select SHA24, SHA256 and SHA384 as part of the shim driver. Signed-off-by: Sylvio Alves --- drivers/crypto/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 4c5c268fcebba..8510762e5d880 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -25,6 +25,9 @@ config CRYPTO_MBEDTLS_SHIM bool "MbedTLS shim driver [EXPERIMENTAL]" select MBEDTLS select MBEDTLS_ENABLE_HEAP + select MBEDTLS_SHA224 + select MBEDTLS_SHA256 + select MBEDTLS_SHA384 select MBEDTLS_SHA512 select MBEDTLS_CIPHER_AES_ENABLED select EXPERIMENTAL From 654e4f51db8afa2f3e055fad070429371e2ba08b Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Tue, 21 Oct 2025 08:26:46 -0300 Subject: [PATCH 0032/1450] tests: crypto: hash: expand test coverage for multiple SHA algorithms Refactor hash tests to support SHA-224, SHA-256, SHA-384, and SHA-512 algorithms with a unified test vector framework. This improves test coverage and makes it easier to verify hardware crypto drivers that support multiple SHA variants. Signed-off-by: Sylvio Alves --- tests/crypto/crypto_hash/src/main.c | 197 ++++++++++++++++++++++------ 1 file changed, 159 insertions(+), 38 deletions(-) diff --git a/tests/crypto/crypto_hash/src/main.c b/tests/crypto/crypto_hash/src/main.c index a5863716654e5..fa04afc7df968 100644 --- a/tests/crypto/crypto_hash/src/main.c +++ b/tests/crypto/crypto_hash/src/main.c @@ -112,6 +112,23 @@ uint8_t test7[] = { 0x8b, 0x4f, 0x4a, 0xb0, 0xed, 0x99, 0x5e }; +static const uint8_t sha224_results[7][28] = { + {0xd1, 0x4a, 0x02, 0x8c, 0x2a, 0x3a, 0x2b, 0xc9, 0x47, 0x61, 0x02, 0xbb, 0x28, 0x82, + 0x34, 0xc4, 0x15, 0xa2, 0xb0, 0x1f, 0x82, 0x8e, 0xa6, 0x2a, 0xc5, 0xb3, 0xe4, 0x2f}, + {0xb1, 0xe4, 0x6b, 0xb9, 0xef, 0xe4, 0x5a, 0xf5, 0x54, 0x36, 0x34, 0x49, 0xc6, 0x94, + 0x5a, 0x0d, 0x61, 0x69, 0xfc, 0x3a, 0x5a, 0x39, 0x6a, 0x56, 0xcb, 0x97, 0xcb, 0x57}, + {0xd2, 0xb0, 0x86, 0xdb, 0xee, 0x60, 0x90, 0x7e, 0xd1, 0x09, 0x86, 0x77, 0xfe, 0x04, + 0x37, 0xb8, 0x14, 0x55, 0x66, 0x87, 0x17, 0x2d, 0x1f, 0x59, 0xcf, 0x38, 0x6c, 0x97}, + {0xbb, 0xac, 0x30, 0x15, 0x10, 0x7f, 0xe0, 0x2b, 0x0c, 0x0b, 0x2b, 0xdc, 0xb2, 0x6f, + 0x44, 0x19, 0x1b, 0xa8, 0xdb, 0xab, 0x43, 0xf5, 0xc6, 0xbb, 0xaa, 0x0a, 0x13, 0x41}, + {0xc2, 0x63, 0xf2, 0x74, 0x12, 0xc1, 0xfd, 0xfb, 0x29, 0x33, 0xb6, 0x2a, 0xec, 0x9f, + 0xa2, 0x60, 0x9c, 0x05, 0x7b, 0x91, 0x1e, 0x99, 0x2d, 0x8f, 0xb2, 0xe5, 0xe1, 0x5a}, + {0x95, 0x99, 0xbd, 0x2d, 0xe7, 0x5b, 0xdf, 0xef, 0xe4, 0xff, 0xf3, 0xc3, 0x78, 0x98, + 0x87, 0xf5, 0xa5, 0x26, 0xd0, 0xea, 0x63, 0xa8, 0xa5, 0xd2, 0x8f, 0xc5, 0x62, 0xd6}, + {0x1f, 0xf8, 0x37, 0xcf, 0xf3, 0x74, 0x77, 0x4d, 0x0c, 0x23, 0x2e, 0x77, 0xb9, 0x64, + 0xed, 0x29, 0xf5, 0xd1, 0xe7, 0x75, 0xad, 0x1a, 0x4e, 0x76, 0x6f, 0x18, 0x7a, 0x77}, +}; + uint8_t sha256_results[7][32] = { {0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c, @@ -136,54 +153,158 @@ uint8_t sha256_results[7][32] = { 0x86, 0x59, 0x98, 0x71, 0x4a, 0xad, 0x0b, 0x5e} }; -ZTEST_USER(crypto_hash, test_hash) -{ - int ret; - struct hash_ctx ctx; +static const uint8_t sha384_results[7][48] = { + {0x38, 0xb0, 0x60, 0xa7, 0x51, 0xac, 0x96, 0x38, 0x4c, 0xd9, 0x32, 0x7e, + 0xb1, 0xb1, 0xe3, 0x6a, 0x21, 0xfd, 0xb7, 0x11, 0x14, 0xbe, 0x07, 0x43, + 0x4c, 0x0c, 0xc7, 0xbf, 0x63, 0xf6, 0xe1, 0xda, 0x27, 0x4e, 0xde, 0xbf, + 0xe7, 0x6f, 0x65, 0xfb, 0xd5, 0x1a, 0xd2, 0xf1, 0x48, 0x98, 0xb9, 0x5b}, + {0x43, 0x72, 0xe3, 0x8a, 0x92, 0xa2, 0x8b, 0x5d, 0x2c, 0x39, 0x1e, 0x62, + 0x45, 0x2a, 0x86, 0xd5, 0x0e, 0x02, 0x67, 0x22, 0x8b, 0xe1, 0x76, 0xc7, + 0x7d, 0x24, 0x02, 0xef, 0xfe, 0x9f, 0xa5, 0x0d, 0xe4, 0x07, 0xbb, 0xb8, + 0x51, 0xb3, 0x7d, 0x59, 0x04, 0xab, 0xa2, 0xde, 0xde, 0x74, 0xda, 0x2a}, + {0xe9, 0x32, 0x48, 0x92, 0xec, 0x87, 0xf2, 0x29, 0x75, 0xc1, 0x4e, 0x42, + 0x0f, 0x3d, 0x77, 0x7d, 0xe5, 0xe9, 0x75, 0xbf, 0x01, 0x86, 0xeb, 0x99, + 0xdc, 0x44, 0x7c, 0xbe, 0x96, 0xcf, 0x8a, 0x7a, 0xcb, 0xbb, 0x78, 0x31, + 0xcf, 0xaf, 0xbb, 0xbf, 0x40, 0x4c, 0xdd, 0x5a, 0x45, 0x91, 0x64, 0x75}, + {0x81, 0x3d, 0x8e, 0x6f, 0x29, 0x18, 0x99, 0xb8, 0x49, 0xf1, 0xab, 0x87, + 0xcb, 0x04, 0x51, 0x48, 0x88, 0xb7, 0x0f, 0x5c, 0x66, 0xbe, 0xc7, 0x96, + 0x44, 0x59, 0x55, 0xae, 0x83, 0xc3, 0x9e, 0xee, 0xec, 0x62, 0xc2, 0x5c, + 0x25, 0xe9, 0x42, 0x94, 0x49, 0xd1, 0x33, 0x40, 0xc4, 0x7a, 0x96, 0x38}, + {0x2a, 0x6c, 0xca, 0xf7, 0xc7, 0xa7, 0xde, 0x23, 0x2e, 0xec, 0x95, 0x52, + 0x1a, 0x64, 0x4e, 0x6d, 0x27, 0x95, 0x6e, 0x32, 0x1c, 0x9f, 0x49, 0x21, + 0x87, 0x04, 0x14, 0x77, 0x76, 0xbc, 0x52, 0x39, 0xc5, 0x72, 0xaa, 0xe4, + 0xbf, 0xbb, 0x19, 0x72, 0x49, 0xd7, 0xd7, 0xbd, 0x09, 0xef, 0x12, 0x88}, + {0x7c, 0xab, 0x44, 0x4f, 0xc2, 0x63, 0xf1, 0x68, 0x83, 0x29, 0x6a, 0x84, + 0xc5, 0xb3, 0x00, 0xc0, 0x56, 0x0f, 0x4c, 0x4f, 0x08, 0x96, 0x95, 0x99, + 0xef, 0xe0, 0x81, 0x10, 0x81, 0x16, 0xd2, 0xea, 0xed, 0xb3, 0x30, 0xb8, + 0x06, 0x11, 0x61, 0x9c, 0x12, 0x97, 0x46, 0x05, 0xf5, 0xdf, 0x91, 0x18}, + {0xa1, 0x4c, 0x97, 0x00, 0x2f, 0x08, 0x3a, 0xf7, 0x17, 0x2d, 0x30, 0x99, + 0x28, 0x3f, 0x36, 0xcf, 0xd1, 0xf8, 0x56, 0xe3, 0x4b, 0x89, 0x63, 0x26, + 0x39, 0xe5, 0x36, 0xbe, 0xbe, 0xa5, 0x69, 0xa6, 0xac, 0x89, 0x19, 0x91, + 0x5a, 0xc7, 0x78, 0xfb, 0xaa, 0xa2, 0xe2, 0x0d, 0x6f, 0xfc, 0x28, 0x41}, +}; +static const uint8_t sha512_results[7][64] = { + {0xcf, 0x83, 0xe1, 0x35, 0x7e, 0xef, 0xb8, 0xbd, 0xf1, 0x54, 0x28, 0x50, 0xd6, + 0x6d, 0x80, 0x07, 0xd6, 0x20, 0xe4, 0x05, 0x0b, 0x57, 0x15, 0xdc, 0x83, 0xf4, + 0xa9, 0x21, 0xd3, 0x6c, 0xe9, 0xce, 0x47, 0xd0, 0xd1, 0x3c, 0x5d, 0x85, 0xf2, + 0xb0, 0xff, 0x83, 0x18, 0xd2, 0x87, 0x7e, 0xec, 0x2f, 0x63, 0xb9, 0x31, 0xbd, + 0x47, 0x41, 0x7a, 0x81, 0xa5, 0x38, 0x32, 0x7a, 0xf9, 0x27, 0xda, 0x3e}, + {0x29, 0x6e, 0x22, 0x67, 0xd7, 0x4c, 0x27, 0x8d, 0xaa, 0xaa, 0x94, 0x0d, 0x17, + 0xb0, 0xcf, 0xb7, 0x4a, 0x50, 0x83, 0xf8, 0xe0, 0x69, 0x72, 0x6d, 0x8c, 0x84, + 0x1c, 0xbe, 0x59, 0x6e, 0x04, 0x31, 0xcb, 0x77, 0x41, 0xa5, 0xb5, 0x0f, 0x71, + 0x66, 0x6c, 0xfd, 0x54, 0xba, 0xcb, 0x7b, 0x00, 0xae, 0xa8, 0x91, 0x49, 0x9c, + 0xf4, 0xef, 0x6a, 0x03, 0xc8, 0xa8, 0x3f, 0xe3, 0x7c, 0x3f, 0x7b, 0xaf}, + {0x1c, 0xac, 0x66, 0x62, 0x60, 0x2f, 0xcc, 0x5f, 0x6c, 0x69, 0xf4, 0x8a, 0xa1, + 0x7a, 0x92, 0x47, 0x50, 0x31, 0x36, 0x3d, 0xa5, 0xc7, 0xb7, 0x8e, 0x2c, 0xa3, + 0xb9, 0xd2, 0x1f, 0x27, 0xd6, 0x72, 0x6c, 0x2c, 0xc7, 0x6c, 0xa5, 0x51, 0x8a, + 0xda, 0x2c, 0x2f, 0xa7, 0x2e, 0xca, 0xf8, 0x34, 0x3f, 0x0c, 0xe1, 0xc1, 0xe8, + 0x2f, 0x69, 0x96, 0xad, 0x6e, 0x8b, 0xbc, 0x5c, 0x84, 0xc2, 0x7f, 0xb3}, + {0x74, 0x29, 0x16, 0x51, 0x71, 0x75, 0xab, 0x4c, 0xa7, 0x01, 0x89, 0xc9, 0xae, + 0x15, 0xca, 0xad, 0x39, 0x59, 0x9b, 0x67, 0x2d, 0xca, 0x75, 0x7b, 0x25, 0x62, + 0x75, 0x47, 0xfb, 0x84, 0x5b, 0xe0, 0x55, 0x25, 0x23, 0x21, 0x32, 0x67, 0x3f, + 0x09, 0x10, 0xcc, 0x24, 0x29, 0xf5, 0x0b, 0xe9, 0xc3, 0x86, 0xec, 0x14, 0xe8, + 0x52, 0xc5, 0xa9, 0x0a, 0x03, 0xc5, 0x63, 0xe1, 0xf6, 0xd7, 0x7b, 0x5c}, + {0x09, 0xa9, 0x85, 0xc1, 0x5f, 0xa5, 0xcc, 0x68, 0xa8, 0x96, 0x8f, 0xfa, 0xea, + 0xf3, 0xb5, 0xec, 0x23, 0x45, 0x69, 0xad, 0x56, 0x74, 0x50, 0x39, 0x4c, 0x07, + 0x5b, 0x90, 0x61, 0xc8, 0xf7, 0xdf, 0x58, 0xff, 0x11, 0x29, 0x95, 0x70, 0x18, + 0x82, 0x16, 0xc6, 0x31, 0xde, 0x60, 0x4d, 0xf0, 0xab, 0x08, 0xcd, 0xd1, 0x93, + 0x29, 0x1c, 0xe5, 0x76, 0x3a, 0xcd, 0xc4, 0x27, 0xdf, 0x06, 0x04, 0x89}, + {0xf8, 0xbc, 0x6c, 0x96, 0x37, 0x92, 0xe6, 0x3d, 0x84, 0x15, 0x32, 0xee, 0xa5, + 0x2f, 0x56, 0x70, 0xa4, 0x3e, 0xd0, 0xac, 0x72, 0xde, 0xa9, 0xb8, 0xd9, 0x2b, + 0x0d, 0xd9, 0x19, 0xc8, 0x1a, 0x28, 0xa0, 0xff, 0xc5, 0x6d, 0xb6, 0x9a, 0xc9, + 0x12, 0x30, 0x78, 0x2a, 0xe1, 0x2d, 0x35, 0x6e, 0x62, 0xd3, 0x94, 0x4b, 0xa0, + 0xdb, 0x29, 0x7f, 0xe9, 0xaf, 0x34, 0x85, 0xbc, 0xd6, 0x9e, 0xe4, 0x1c}, + {0xd2, 0x7d, 0xf8, 0xfb, 0x7e, 0xd5, 0xb9, 0x1c, 0xa8, 0x08, 0x33, 0x77, 0xf1, + 0x3c, 0x6f, 0x59, 0x63, 0xd7, 0x4e, 0x4a, 0xcc, 0x54, 0x24, 0x6b, 0x2e, 0x14, + 0x96, 0x25, 0xd2, 0x52, 0xeb, 0xf2, 0x66, 0x25, 0x3c, 0xae, 0x62, 0x83, 0x38, + 0xc1, 0x11, 0x94, 0x16, 0x8b, 0x73, 0x72, 0xf3, 0xf8, 0x61, 0x04, 0x1a, 0x46, + 0xaf, 0x54, 0x4b, 0x2f, 0xec, 0xdf, 0x76, 0x08, 0x57, 0x71, 0xef, 0x8c}, +}; + +static inline const struct device *get_crypto_dev(void) +{ #ifdef CRYPTO_DRV_NAME const struct device *dev = device_get_binding(CRYPTO_DRV_NAME); - - if (!dev) { - zassert(0, "Crypto device is not ready"); - } #else const struct device *dev = DEVICE_DT_GET_ONE(CRYPTO_DEV_COMPAT); +#endif + return dev; +} + +static void run_vector_set(enum hash_algo algo, size_t out_len, const uint8_t *const *inputs, + const size_t *in_lens, const uint8_t *const expected[], size_t nvec) +{ + const struct device *dev = get_crypto_dev(); - if (!device_is_ready(dev)) { - zassert(0, "Crypto device is not ready"); + zassert_true(dev && device_is_ready(dev), "Crypto device is not ready"); + + struct hash_ctx ctx = {.flags = CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS}; + int rc = hash_begin_session(dev, &ctx, algo); + + /* Skip test if algorithm is not supported */ + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; } -#endif - ctx.flags = CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS; - - ret = hash_begin_session(dev, &ctx, CRYPTO_HASH_ALGO_SHA256); - zassert_true(ret == 0, "Failed to init sha256 session"); - -#define TEST_HASH(_i) \ - do { \ - uint8_t out_buf[32] = {0}; \ - struct hash_pkt pkt = { \ - .in_buf = test ## _i, \ - .in_len = sizeof(test ## _i), \ - .out_buf = out_buf, \ - }; \ - ret = hash_compute(&ctx, &pkt); \ - zassert_true(ret == 0, "Failed to compute hash for test " #_i); \ - ret = memcmp(pkt.out_buf, sha256_results[_i - 1], 32); \ - zassert_true(ret == 0, "Failed to compute hash for test " #_i); \ - } while (0) - - - TEST_HASH(1); - TEST_HASH(2); - TEST_HASH(3); - TEST_HASH(4); - TEST_HASH(5); - TEST_HASH(6); - TEST_HASH(7); + zassert_equal(rc, 0, "begin_session failed"); + + for (size_t i = 0; i < nvec; i++) { + uint8_t out[64] = {0}; /* big enough for SHA-512 */ + + struct hash_pkt pkt = { + /* Safe: hash operations only read from in_buf, never modify it */ + .in_buf = inputs[i], + .in_len = in_lens[i], + .out_buf = out, + }; + rc = hash_compute(&ctx, &pkt); + zassert_equal(rc, 0, "hash_compute failed @vec %d", (int)i + 1); + rc = memcmp(out, expected[i], out_len); + zassert_equal(rc, 0, "digest mismatch @vec %d", (int)i + 1); + } hash_free_session(dev, &ctx); } +/* Convert our 2D byte arrays to array-of-pointers for helper */ +#define PTRS_FROM_2D(name) \ + static const uint8_t *name##_ptrs[] = {name[0], name[1], name[2], name[3], \ + name[4], name[5], name[6]} + +PTRS_FROM_2D(sha224_results); +PTRS_FROM_2D(sha256_results); +PTRS_FROM_2D(sha384_results); +PTRS_FROM_2D(sha512_results); + +/* Inputs & sizes */ +static const uint8_t *inputs[] = {test1, test2, test3, test4, test5, test6, test7}; +static const size_t in_lens[] = {sizeof(test1), sizeof(test2), sizeof(test3), sizeof(test4), + sizeof(test5), sizeof(test6), sizeof(test7)}; + +ZTEST(crypto_hash, test_sha224) +{ + run_vector_set(CRYPTO_HASH_ALGO_SHA224, 28, inputs, in_lens, + (const uint8_t *const *)sha224_results_ptrs, 7); +} + +ZTEST(crypto_hash, test_sha256) +{ + run_vector_set(CRYPTO_HASH_ALGO_SHA256, 32, inputs, in_lens, + (const uint8_t *const *)sha256_results_ptrs, 7); +} + +ZTEST(crypto_hash, test_sha384) +{ + run_vector_set(CRYPTO_HASH_ALGO_SHA384, 48, inputs, in_lens, + (const uint8_t *const *)sha384_results_ptrs, 7); +} + +ZTEST(crypto_hash, test_sha512) +{ + run_vector_set(CRYPTO_HASH_ALGO_SHA512, 64, inputs, in_lens, + (const uint8_t *const *)sha512_results_ptrs, 7); +} + ZTEST_SUITE(crypto_hash, NULL, NULL, NULL, NULL, NULL); From 8aa804040185c6bf7d9bb3515c0df46eeb5dd0bd Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 22 Oct 2025 12:49:55 -0300 Subject: [PATCH 0033/1450] tests: crypto: add AES cipher tests Add AES test cases for ECB, CBC, CCM, and GCM modes with standard test vectors from FIPS-197 and NIST specifications. Signed-off-by: Sylvio Alves --- tests/crypto/crypto_aes/CMakeLists.txt | 8 + tests/crypto/crypto_aes/prj.conf | 9 + tests/crypto/crypto_aes/prj_mtls_shim.conf | 8 + tests/crypto/crypto_aes/src/main.c | 583 +++++++++++++++++++++ tests/crypto/crypto_aes/testcase.yaml | 8 + 5 files changed, 616 insertions(+) create mode 100644 tests/crypto/crypto_aes/CMakeLists.txt create mode 100644 tests/crypto/crypto_aes/prj.conf create mode 100644 tests/crypto/crypto_aes/prj_mtls_shim.conf create mode 100644 tests/crypto/crypto_aes/src/main.c create mode 100644 tests/crypto/crypto_aes/testcase.yaml diff --git a/tests/crypto/crypto_aes/CMakeLists.txt b/tests/crypto/crypto_aes/CMakeLists.txt new file mode 100644 index 0000000000000..674c61c5c2c1c --- /dev/null +++ b/tests/crypto/crypto_aes/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(crypto_hash) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/crypto/crypto_aes/prj.conf b/tests/crypto/crypto_aes/prj.conf new file mode 100644 index 0000000000000..68f464029a22d --- /dev/null +++ b/tests/crypto/crypto_aes/prj.conf @@ -0,0 +1,9 @@ +CONFIG_ZTEST_STACK_SIZE=4096 +CONFIG_ZTEST=y +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_CRYPTO=y +CONFIG_CRYPTO_LOG_LEVEL_DBG=y diff --git a/tests/crypto/crypto_aes/prj_mtls_shim.conf b/tests/crypto/crypto_aes/prj_mtls_shim.conf new file mode 100644 index 0000000000000..71d350424a3be --- /dev/null +++ b/tests/crypto/crypto_aes/prj_mtls_shim.conf @@ -0,0 +1,8 @@ +CONFIG_MBEDTLS=y +CONFIG_MBEDTLS_BUILTIN=y +CONFIG_MBEDTLS_HEAP_SIZE=512 +CONFIG_MBEDTLS_CIPHER_AES_ENABLED=y +CONFIG_MBEDTLS_CIPHER_CCM_ENABLED=y +CONFIG_MBEDTLS_CIPHER_GCM_ENABLED=y + +CONFIG_CRYPTO_MBEDTLS_SHIM=y diff --git a/tests/crypto/crypto_aes/src/main.c b/tests/crypto/crypto_aes/src/main.c new file mode 100644 index 0000000000000..c3fe23f2312c1 --- /dev/null +++ b/tests/crypto/crypto_aes/src/main.c @@ -0,0 +1,583 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_CRYPTO_MBEDTLS_SHIM +#define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME +#else +#error "You need to enable one crypto device" +#endif + +/* Some crypto drivers require IO buffers to be aligned */ +#define IO_ALIGNMENT_BYTES 4 + +/* Test vectors from FIPS-197 and NIST SP 800-38A */ + +/* ECB Mode Test Vectors - FIPS-197 */ +static uint8_t ecb_key[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; + +static uint8_t ecb_plaintext[16] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF}; + +static uint8_t ecb_ciphertext[16] = {0x69, 0xC4, 0xE0, 0xD8, 0x6A, 0x7B, 0x04, 0x30, + 0xD8, 0xCD, 0xB7, 0x80, 0x70, 0xB4, 0xC5, 0x5A}; + +/* CBC Mode Test Vectors - Single block (16 bytes, no padding) */ +static uint8_t cbc_key[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + +static uint8_t cbc_iv[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; + +static uint8_t cbc_plaintext[16] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a}; + +static uint8_t cbc_ciphertext[16] = {0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, + 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d}; + +/* CTR Mode Test Vectors */ +static uint8_t ctr_key[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + +static uint8_t ctr_iv[12] = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, + 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb}; + +static uint8_t ctr_plaintext[64] = { + 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, + 0x93, 0x17, 0x2a, 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, + 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, + 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, 0xf6, 0x9f, 0x24, 0x45, + 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; + +static uint8_t ctr_ciphertext[64] = { + 0x22, 0xe5, 0x2f, 0xb1, 0x77, 0xd8, 0x65, 0xb2, 0xf7, 0xc6, 0xb5, 0x12, 0x69, + 0x2d, 0x11, 0x4d, 0xed, 0x6c, 0x1c, 0x72, 0x25, 0xda, 0xf6, 0xa2, 0xaa, 0xd9, + 0xd3, 0xda, 0x2d, 0xba, 0x21, 0x68, 0x35, 0xc0, 0xaf, 0x6b, 0x6f, 0x40, 0xc3, + 0xc6, 0xef, 0xc5, 0x85, 0xd0, 0x90, 0x2c, 0xc2, 0x63, 0x12, 0x2b, 0xc5, 0x8e, + 0x72, 0xde, 0x5c, 0xa2, 0xa3, 0x5c, 0x85, 0x3a, 0xb9, 0x2c, 0x06, 0xbb}; + +/* CCM Mode Test Vectors - RFC 3610 test vector #1 */ +static uint8_t ccm_key[16] = {0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf}; + +static uint8_t ccm_nonce[13] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5}; + +static uint8_t ccm_hdr[8] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + +static uint8_t ccm_plaintext[23] = {0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e}; + +static uint8_t ccm_ciphertext[31] = {0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x63, 0xd2, + 0xf0, 0x66, 0xd0, 0xc2, 0xc0, 0xf9, 0x89, 0x80, + 0x6d, 0x5f, 0x6b, 0x61, 0xda, 0xc3, 0x84, 0x17, + 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0}; + +/* GCM Mode Test Vectors - MACsec GCM-AES test vector 2.4.1 */ +static uint8_t gcm_key[16] = {0x07, 0x1b, 0x11, 0x3b, 0x0c, 0xa7, 0x43, 0xfe, + 0xcc, 0xcf, 0x3d, 0x05, 0x1f, 0x73, 0x73, 0x82}; + +static uint8_t gcm_nonce[12] = {0xf0, 0x76, 0x1e, 0x8d, 0xcd, 0x3d, + 0x00, 0x01, 0x76, 0xd4, 0x57, 0xed}; + +static uint8_t gcm_hdr[20] = {0xe2, 0x01, 0x06, 0xd7, 0xcd, 0x0d, 0xf0, 0x76, 0x1e, 0x8d, + 0xcd, 0x3d, 0x88, 0xe5, 0x4c, 0x2a, 0x76, 0xd4, 0x57, 0xed}; + +static uint8_t gcm_plaintext[42] = { + 0x08, 0x00, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, + 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, + 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x00, 0x04}; + +static uint8_t gcm_ciphertext[58] = { + 0x13, 0xb4, 0xc7, 0x2b, 0x38, 0x9d, 0xc5, 0x01, 0x8e, 0x72, 0xa1, 0x71, 0xdd, 0x85, 0xa5, + 0xd3, 0x75, 0x22, 0x74, 0xd3, 0xa0, 0x19, 0xfb, 0xca, 0xed, 0x09, 0xa4, 0x25, 0xcd, 0x9b, + 0x2e, 0x1c, 0x9b, 0x72, 0xee, 0xe7, 0xc9, 0xde, 0x7d, 0x52, 0xb3, 0xf3, 0xd6, 0xa5, 0x28, + 0x4f, 0x4a, 0x6d, 0x3f, 0xe2, 0x2a, 0x5d, 0x6c, 0x2b, 0x96, 0x04, 0x94, 0xc3}; + +static inline const struct device *get_crypto_dev(void) +{ +#ifdef CRYPTO_DRV_NAME + const struct device *dev = device_get_binding(CRYPTO_DRV_NAME); +#else + const struct device *dev = DEVICE_DT_GET_ONE(CRYPTO_DEV_COMPAT); +#endif + return dev; +} + +static const struct device *crypto_dev; + +static void *crypto_aes_setup(void) +{ + crypto_dev = get_crypto_dev(); + zassert_true(crypto_dev && device_is_ready(crypto_dev), "Crypto device is not ready"); + return NULL; +} + +static void crypto_aes_before(void *fixture) +{ + ARG_UNUSED(fixture); + + /* Add delay between tests to ensure cleanup */ + k_msleep(10); +} + +/* ECB Mode Tests */ +ZTEST(crypto_aes, test_ecb_encrypt) +{ + uint8_t encrypted[16] __aligned(IO_ALIGNMENT_BYTES) = {0}; + struct cipher_ctx ctx = { + .keylen = sizeof(ecb_key), + .key.bit_stream = ecb_key, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ecb_plaintext, + .in_len = sizeof(ecb_plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_ECB, CRYPTO_CIPHER_OP_ENCRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_block_op(&ctx, &pkt); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "ECB encrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(encrypted, ecb_ciphertext, sizeof(ecb_ciphertext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "ECB encrypt output mismatch"); +} + +ZTEST(crypto_aes, test_ecb_decrypt) +{ + uint8_t decrypted[16] __aligned(IO_ALIGNMENT_BYTES) = {0}; + struct cipher_ctx ctx = { + .keylen = sizeof(ecb_key), + .key.bit_stream = ecb_key, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ecb_ciphertext, + .in_len = sizeof(ecb_ciphertext), + .out_buf_max = sizeof(decrypted), + .out_buf = decrypted, + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_ECB, CRYPTO_CIPHER_OP_DECRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_block_op(&ctx, &pkt); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "ECB decrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(decrypted, ecb_plaintext, sizeof(ecb_plaintext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "ECB decrypt output mismatch"); +} + +/* CBC Mode Tests */ +ZTEST(crypto_aes, test_cbc_encrypt) +{ + uint8_t encrypted[32] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t iv_copy[16]; + + memcpy(iv_copy, cbc_iv, sizeof(cbc_iv)); + + struct cipher_ctx ctx = { + .keylen = sizeof(cbc_key), + .key.bit_stream = cbc_key, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)cbc_plaintext, + .in_len = sizeof(cbc_plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_CBC, CRYPTO_CIPHER_OP_ENCRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_cbc_op(&ctx, &pkt, iv_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CBC encrypt failed (rc=%d)", rc); + return; + } + + /* CBC prepends IV to output, so ciphertext starts at offset 16 */ + rc = memcmp(encrypted + 16, cbc_ciphertext, sizeof(cbc_ciphertext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CBC encrypt output mismatch"); +} + +ZTEST(crypto_aes, test_cbc_decrypt) +{ + /* For decrypt, need to prepend IV to ciphertext input */ + uint8_t input[32] __aligned(IO_ALIGNMENT_BYTES); + uint8_t decrypted[16] __aligned(IO_ALIGNMENT_BYTES) = {0}; + + /* Prepend IV to ciphertext */ + memcpy(input, cbc_iv, sizeof(cbc_iv)); + memcpy(input + 16, cbc_ciphertext, sizeof(cbc_ciphertext)); + + struct cipher_ctx ctx = { + .keylen = sizeof(cbc_key), + .key.bit_stream = cbc_key, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)input, + .in_len = sizeof(input), + .out_buf_max = sizeof(decrypted), + .out_buf = decrypted, + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_CBC, CRYPTO_CIPHER_OP_DECRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_cbc_op(&ctx, &pkt, input); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CBC decrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(decrypted, cbc_plaintext, sizeof(cbc_plaintext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CBC decrypt output mismatch"); +} + +/* CTR Mode Tests */ +ZTEST(crypto_aes, test_ctr_encrypt) +{ + uint8_t encrypted[64] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t iv_copy[12]; + + memcpy(iv_copy, ctr_iv, sizeof(ctr_iv)); + + struct cipher_ctx ctx = { + .keylen = sizeof(ctr_key), + .key.bit_stream = ctr_key, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + .mode_params.ctr_info.ctr_len = 32, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ctr_plaintext, + .in_len = sizeof(ctr_plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_CTR, CRYPTO_CIPHER_OP_ENCRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_ctr_op(&ctx, &pkt, iv_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CTR encrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(encrypted, ctr_ciphertext, sizeof(ctr_ciphertext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CTR encrypt output mismatch"); +} + +ZTEST(crypto_aes, test_ctr_decrypt) +{ + uint8_t decrypted[64] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t iv_copy[12]; + + memcpy(iv_copy, ctr_iv, sizeof(ctr_iv)); + + struct cipher_ctx ctx = { + .keylen = sizeof(ctr_key), + .key.bit_stream = ctr_key, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + .mode_params.ctr_info.ctr_len = 32, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ctr_ciphertext, + .in_len = sizeof(ctr_ciphertext), + .out_buf_max = sizeof(decrypted), + .out_buf = decrypted, + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_CTR, CRYPTO_CIPHER_OP_DECRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_ctr_op(&ctx, &pkt, iv_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CTR decrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(decrypted, ctr_plaintext, sizeof(ctr_plaintext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CTR decrypt output mismatch"); +} + +/* CCM Mode Tests */ +ZTEST(crypto_aes, test_ccm_encrypt) +{ + uint8_t encrypted[50] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t nonce_copy[13]; + + memcpy(nonce_copy, ccm_nonce, sizeof(ccm_nonce)); + + struct cipher_ctx ctx = { + .keylen = sizeof(ccm_key), + .key.bit_stream = ccm_key, + .mode_params.ccm_info = { + .nonce_len = sizeof(ccm_nonce), + .tag_len = 8, + }, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ccm_plaintext, + .in_len = sizeof(ccm_plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + + struct cipher_aead_pkt aead_pkt = { + .ad = (uint8_t *)ccm_hdr, + .ad_len = sizeof(ccm_hdr), + .pkt = &pkt, + .tag = encrypted + sizeof(ccm_plaintext), + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_CCM, CRYPTO_CIPHER_OP_ENCRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_ccm_op(&ctx, &aead_pkt, nonce_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CCM encrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(encrypted, ccm_ciphertext, sizeof(ccm_ciphertext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CCM encrypt output mismatch"); +} + +ZTEST(crypto_aes, test_ccm_decrypt) +{ + uint8_t decrypted[32] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t nonce_copy[13]; + uint8_t ciphertext_copy[31]; + + memcpy(nonce_copy, ccm_nonce, sizeof(ccm_nonce)); + memcpy(ciphertext_copy, ccm_ciphertext, sizeof(ccm_ciphertext)); + + struct cipher_ctx ctx = { + .keylen = sizeof(ccm_key), + .key.bit_stream = ccm_key, + .mode_params.ccm_info = { + .nonce_len = sizeof(ccm_nonce), + .tag_len = 8, + }, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ciphertext_copy, + .in_len = sizeof(ccm_plaintext), + .out_buf_max = sizeof(decrypted), + .out_buf = decrypted, + }; + + struct cipher_aead_pkt aead_pkt = { + .ad = (uint8_t *)ccm_hdr, + .ad_len = sizeof(ccm_hdr), + .pkt = &pkt, + .tag = ciphertext_copy + sizeof(ccm_plaintext), + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_CCM, CRYPTO_CIPHER_OP_DECRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_ccm_op(&ctx, &aead_pkt, nonce_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CCM decrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(decrypted, ccm_plaintext, sizeof(ccm_plaintext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "CCM decrypt output mismatch"); +} + +/* GCM Mode Tests */ +ZTEST(crypto_aes, test_gcm_encrypt) +{ + uint8_t encrypted[60] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t nonce_copy[12]; + + memcpy(nonce_copy, gcm_nonce, sizeof(gcm_nonce)); + + struct cipher_ctx ctx = { + .keylen = sizeof(gcm_key), + .key.bit_stream = gcm_key, + .mode_params.gcm_info = { + .nonce_len = sizeof(gcm_nonce), + .tag_len = 16, + }, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)gcm_plaintext, + .in_len = sizeof(gcm_plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + + struct cipher_aead_pkt aead_pkt = { + .ad = (uint8_t *)gcm_hdr, + .ad_len = sizeof(gcm_hdr), + .pkt = &pkt, + .tag = encrypted + sizeof(gcm_plaintext), + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_GCM, CRYPTO_CIPHER_OP_ENCRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_gcm_op(&ctx, &aead_pkt, nonce_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "GCM encrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(encrypted, gcm_ciphertext, sizeof(gcm_ciphertext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "GCM encrypt output mismatch"); +} + +ZTEST(crypto_aes, test_gcm_decrypt) +{ + uint8_t decrypted[44] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t nonce_copy[12]; + uint8_t ciphertext_copy[58]; + + memcpy(nonce_copy, gcm_nonce, sizeof(gcm_nonce)); + memcpy(ciphertext_copy, gcm_ciphertext, sizeof(gcm_ciphertext)); + + struct cipher_ctx ctx = { + .keylen = sizeof(gcm_key), + .key.bit_stream = gcm_key, + .mode_params.gcm_info = { + .nonce_len = sizeof(gcm_nonce), + .tag_len = 16, + }, + .flags = CAP_RAW_KEY | CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS, + }; + + struct cipher_pkt pkt = { + .in_buf = (uint8_t *)ciphertext_copy, + .in_len = sizeof(gcm_plaintext), + .out_buf_max = sizeof(decrypted), + .out_buf = decrypted, + }; + struct cipher_aead_pkt aead_pkt = { + .ad = (uint8_t *)gcm_hdr, + .ad_len = sizeof(gcm_hdr), + .pkt = &pkt, + .tag = ciphertext_copy + sizeof(gcm_plaintext), + }; + + int rc = cipher_begin_session(crypto_dev, &ctx, CRYPTO_CIPHER_ALGO_AES, + CRYPTO_CIPHER_MODE_GCM, CRYPTO_CIPHER_OP_DECRYPT); + + if (rc == -ENOTSUP) { + ztest_test_skip(); + return; + } + + rc = cipher_gcm_op(&ctx, &aead_pkt, nonce_copy); + if (rc != 0) { + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "GCM decrypt failed (rc=%d)", rc); + return; + } + + rc = memcmp(decrypted, gcm_plaintext, sizeof(gcm_plaintext)); + cipher_free_session(crypto_dev, &ctx); + zassert_equal(rc, 0, "GCM decrypt output mismatch"); +} + +ZTEST_SUITE(crypto_aes, NULL, crypto_aes_setup, crypto_aes_before, NULL, NULL); diff --git a/tests/crypto/crypto_aes/testcase.yaml b/tests/crypto/crypto_aes/testcase.yaml new file mode 100644 index 0000000000000..36d09836910fb --- /dev/null +++ b/tests/crypto/crypto_aes/testcase.yaml @@ -0,0 +1,8 @@ +tests: + crypto.aes: + platform_allow: + - native_sim + integration_platforms: + - native_sim + extra_args: EXTRA_CONF_FILE=prj_mtls_shim.conf + tags: crypto From a4588c0baeab85d0204a631b9f7aa386d9196921 Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Fri, 24 Oct 2025 15:12:42 -0300 Subject: [PATCH 0034/1450] tests: crypto_aes: add espressif support boards Add ESP32 devkits in testcases. Signed-off-by: Sylvio Alves --- tests/crypto/crypto_aes/src/main.c | 2 ++ tests/crypto/crypto_aes/testcase.yaml | 11 ++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/tests/crypto/crypto_aes/src/main.c b/tests/crypto/crypto_aes/src/main.c index c3fe23f2312c1..3da74aa964af7 100644 --- a/tests/crypto/crypto_aes/src/main.c +++ b/tests/crypto/crypto_aes/src/main.c @@ -12,6 +12,8 @@ #ifdef CONFIG_CRYPTO_MBEDTLS_SHIM #define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME +#elif CONFIG_CRYPTO_ESP32_AES +#define CRYPTO_DEV_COMPAT espressif_esp32_aes #else #error "You need to enable one crypto device" #endif diff --git a/tests/crypto/crypto_aes/testcase.yaml b/tests/crypto/crypto_aes/testcase.yaml index 36d09836910fb..64d4884532584 100644 --- a/tests/crypto/crypto_aes/testcase.yaml +++ b/tests/crypto/crypto_aes/testcase.yaml @@ -1,8 +1,17 @@ tests: - crypto.aes: + crypto.aes.mbedtls_shim: platform_allow: - native_sim integration_platforms: - native_sim extra_args: EXTRA_CONF_FILE=prj_mtls_shim.conf tags: crypto + crypto.aes: + platform_allow: + - esp32_devkitc/esp32/procpu + - esp32s2_devkitc + - esp32s3_devkitc/esp32s3/procpu + - esp32c3_devkitc + - esp32c6_devkitc/esp32c6/hpcore + - esp32h2_devkitm + tags: crypto From 3ae4dfe490d8def0899ba17204b2a5a2df7357dd Mon Sep 17 00:00:00 2001 From: Jakub Rzeszutko Date: Mon, 20 Oct 2025 12:24:31 +0200 Subject: [PATCH 0035/1450] shell: fix deadlock in the bypass function Previously, the bypass() function was called while the shell mutex was still held, preventing the use of shell APIs (e.g. shell_print()) inside the bypass context. This change unlocks the shell mutex before invoking bypass() and locks it again afterwards, restoring proper shell context handling and preventing potential deadlocks. Issue fixed by: roni1234321 Fixes #97722 Signed-off-by: Jakub Rzeszutko --- subsys/shell/shell.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/subsys/shell/shell.c b/subsys/shell/shell.c index da203ddc62c2f..8c3380d23ba6d 100644 --- a/subsys/shell/shell.c +++ b/subsys/shell/shell.c @@ -999,7 +999,18 @@ static void state_collect(const struct shell *sh) sizeof(buf), &count); if (count) { z_flag_cmd_ctx_set(sh, true); + /** Unlock the shell mutex before calling the bypass function, + * allowing shell APIs (e.g. shell_print()) to be used inside it. + * Since these APIs require the mutex to be unlocked, + * we temporarily leave the shell context and transfer control + * to the bypass function. + */ + z_shell_unlock(sh); bypass(sh, buf, count); + /* After returning, we're back in the shell context — re-acquire + * the shell mutex on the shell thread. + */ + z_shell_lock(sh); z_flag_cmd_ctx_set(sh, false); /* Check if bypass mode ended. */ if (!(volatile shell_bypass_cb_t *)sh->ctx->bypass) { From b0d4580422e29d33390841cbb84f93113e01ff09 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 8 Oct 2025 17:06:05 -0400 Subject: [PATCH 0036/1450] tests: lib: lockfree: Fix MPSC test consumer node return logic The MPSC test consumer was incorrectly handling node returns to producer free queues. It called spsc_acquire() without checking the return value, then unconditionally called spsc_produce(). When the SPSC free queue was full, spsc_acquire() would return NULL and not increment the acquire counter, causing spsc_produce() to silently do nothing (it only produces if acquire > 0). This resulted in lost nodes. At least on QEMU, a 4-CPU configuration is needed for this bug to manifest. Producers put all nodes in flight simultaneously with the single consumer unable to keep up, causing frequent SPSC queue full conditions. The Fix: Loop on spsc_acquire() until it succeeds before calling spsc_produce(). This ensures nodes are always successfully returned to producer queues. Added board overlay for qemu_cortex_a53/smp to enable 4-CPU testing, which reproduces the issue and validates the fix. Signed-off-by: Nicolas Pitre --- .../qemu_cortex_a53_qemu_cortex_a53_smp.conf | 2 ++ ...emu_cortex_a53_qemu_cortex_a53_smp.overlay | 22 +++++++++++++++++++ tests/lib/lockfree/src/test_mpsc.c | 5 ++++- 3 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf create mode 100644 tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay diff --git a/tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf b/tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf new file mode 100644 index 0000000000000..9eb7d2bea94db --- /dev/null +++ b/tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf @@ -0,0 +1,2 @@ +# Configuration overlay for 4-CPU testing on QEMU Cortex-A53 +CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay b/tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay new file mode 100644 index 0000000000000..aa91adf0a64bb --- /dev/null +++ b/tests/lib/lockfree/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay @@ -0,0 +1,22 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Device tree overlay to add 2 more CPUs to QEMU Cortex-A53 SMP + * for testing 4-CPU configurations + */ + +/ { + cpus { + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <3>; + }; + }; +}; diff --git a/tests/lib/lockfree/src/test_mpsc.c b/tests/lib/lockfree/src/test_mpsc.c index 2085d26b32d6f..35c278bc0f67e 100644 --- a/tests/lib/lockfree/src/test_mpsc.c +++ b/tests/lib/lockfree/src/test_mpsc.c @@ -127,7 +127,10 @@ static void mpsc_consumer(void *p1, void *p2, void *p3) nn = CONTAINER_OF(n, struct test_mpsc_node, n); - spsc_acquire(node_q[nn->id]); + /* Return node to producer's free queue - must retry if queue is full */ + while (spsc_acquire(node_q[nn->id]) == NULL) { + k_yield(); + } spsc_produce(node_q[nn->id]); } } From 751711accc2e54bc3db994933cd04f804172feab Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Tue, 14 Oct 2025 15:15:48 +0200 Subject: [PATCH 0037/1450] include: zephyr: sys: correct sys_test_bit() and friends description Correct the documentation of sys_test_bit() and its derivative helper functions (listed below) since these return a bit mask value instead of an essentially boolean value as previosuly described. In tree implementation do conform with that: the result of these functions are always implicitly tested against being 0 or a non-zero value. Helper functions which documentation is modified are sys_test_bit(), sys_test_and_set_bit(), sys_test_and_clear_bit(), sys_bitfield_test_bit(), sys_bitfield_test_and_set_bit() and sys_bitfield_test_and_clear_bit(). Signed-off-by: Etienne Carriere --- include/zephyr/sys/sys_io.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/include/zephyr/sys/sys_io.h b/include/zephyr/sys/sys_io.h index fc3c1205d6185..ae2692764c263 100644 --- a/include/zephyr/sys/sys_io.h +++ b/include/zephyr/sys/sys_io.h @@ -285,7 +285,8 @@ typedef uintptr_t mem_addr_t; * @param addr the memory address from where to look for the bit * @param bit the designated bit to test (from 0 to 31) * - * @return 1 if it is set, 0 otherwise + * @return the bitwise AND result of @p addr content and (1 << @p bit). + * Result is 0 only if the bit is cleared otherwise result is a non-0 value. */ /** @@ -298,7 +299,8 @@ typedef uintptr_t mem_addr_t; * @param addr the memory address from where to look for the bit * @param bit the designated bit to test and set (from 0 to 31) * - * @return 1 if it was set, 0 otherwise + * @return the bitwise AND result of @p addr content and (1 << @p bit) before target bit + * is set. Result is 0 only if the bit was cleared otherwise result is a non-0 value. */ /** @@ -311,7 +313,8 @@ typedef uintptr_t mem_addr_t; * @param addr the memory address from where to look for the bit * @param bit the designated bit to test and clear (from 0 to 31) * - * @return 0 if it was clear, 1 otherwise + * @return the bitwise AND result of @p addr content and (1 << @p bit) before target bit + * is cleared. Result is 0 only if the bit was cleared otherwise result is a non-0 value. */ /** @@ -344,7 +347,8 @@ typedef uintptr_t mem_addr_t; * @param addr the memory address from where to look for the bit * @param bit the designated bit to test (arbitrary * - * @return 1 if it is set, 0 otherwise + * @return the bitwise AND result of @p addr content and (1 << @p bit). Result is 0 + * only if the bit is cleared otherwise result is a non-0 value. */ /** @@ -357,7 +361,8 @@ typedef uintptr_t mem_addr_t; * @param addr the memory address from where to look for the bit * @param bit the designated bit to test and set (arbitrary) * - * @return 1 if it was set, 0 otherwise + * @return the bitwise AND result of @p addr content and (1 << @p bit) before target bit + * is set. Result is 0 only if the bit was cleared otherwise result is a non-0 value. */ /** @@ -370,7 +375,8 @@ typedef uintptr_t mem_addr_t; * @param addr the memory address from where to look for the bit * @param bit the designated bit to test and clear (arbitrary) * - * @return 0 if it was clear, 1 otherwise + * @return the bitwise AND result of @p addr content and (1 << @p bit) before target bit + * is cleared. Result is 0 only if the bit was cleared otherwise result is a non-0 value. */ From 2e9f29a67cec3c5e16ef6513f01367819b77f260 Mon Sep 17 00:00:00 2001 From: Elmo Lan Date: Mon, 13 Oct 2025 20:12:53 +0800 Subject: [PATCH 0038/1450] MAINTAINERS: add maintainer for Realtek EC api and driver This commit adds maintainers of Realtek EC to maintainers.yml Signed-off-by: Elmo Lan --- MAINTAINERS.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 9ef14d9351fc9..033f36a407a48 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -4306,6 +4306,11 @@ Realtek EC Platforms: status: maintained maintainers: - JasonLin-RealTek + collaborators: + - elmo9999 + - benson0715 + - JhanBoChao-Realtek + - Titan-Realtek files: - boards/realtek/ - drivers/*/*rts5912* From 2487fe9a4d38f320c5f6f4c0f4a2831b9dc25535 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Mon, 6 Oct 2025 16:26:03 -0700 Subject: [PATCH 0039/1450] include: linker: Set eh_frame size to 0 when C++ exceptions are disabled When building Zephyr with CONFIG_CPP_EXCEPTIONS=n and linking against a libc++ built with support for exceptions, lld complains that the eh_frame-related symbols are missing: ld.lld: error: undefined symbol: __eh_frame_start ld.lld: error: undefined symbol: __eh_frame_end ld.lld: error: undefined symbol: __eh_frame_hdr_start ld.lld: error: undefined symbol: __eh_frame_hdr_end libunwind handles the zero size: https://github.com/llvm/llvm-project/blob/76e71e05d2687f602695931b2fbf25e4e262dcc4/libunwind/src/AddressSpace.hpp#L520-L526 https://github.com/llvm/llvm-project/blob/76e71e05d2687f602695931b2fbf25e4e262dcc4/libunwind/src/EHHeaderParser.hpp#L61-L64 Signed-off-by: Tom Hughes --- include/zephyr/linker/cplusplus-rom.ld | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/zephyr/linker/cplusplus-rom.ld b/include/zephyr/linker/cplusplus-rom.ld index 89f35c309a522..a93bad13a8ea0 100644 --- a/include/zephyr/linker/cplusplus-rom.ld +++ b/include/zephyr/linker/cplusplus-rom.ld @@ -30,5 +30,9 @@ #endif /* CONFIG_CPP */ #if !defined(CONFIG_CPP_EXCEPTIONS) + PROVIDE(__eh_frame_start = 0); + PROVIDE(__eh_frame_end = 0); + PROVIDE(__eh_frame_hdr_start = 0); + PROVIDE(__eh_frame_hdr_end = 0); /DISCARD/ : { *(.eh_frame) } #endif From ef844cee5551d3adaa021d5bdc6d8e5a3906571a Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 14 Oct 2025 16:57:33 +0000 Subject: [PATCH 0040/1450] kernel: make k_is_pre_kernel safe to call from user mode Make k_is_pre_kernel safe to call from user mode. Since z_sys_post_kernel memory is not accessible to user threads, calling k_is_pre_kernel would result in a memory access fault. This change adds k_is_user_context guard. It can be assumed the system is post-kernel if k_is_user_context is true. Signed-off-by: Rob Barnes --- include/zephyr/kernel.h | 9 +++++++++ tests/kernel/mem_protect/userspace/src/main.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h index 3dd4b7c589ea8..e3583630b9153 100644 --- a/include/zephyr/kernel.h +++ b/include/zephyr/kernel.h @@ -1289,6 +1289,15 @@ static inline bool k_is_pre_kernel(void) { extern bool z_sys_post_kernel; /* in init.c */ + /* + * If called from user mode, it must already be post kernel. + * This guard is necessary because z_sys_post_kernel memory + * is not accessible to user threads. + */ + if (k_is_user_context()) { + return false; + } + return !z_sys_post_kernel; } diff --git a/tests/kernel/mem_protect/userspace/src/main.c b/tests/kernel/mem_protect/userspace/src/main.c index 64164695e10e9..4f1249c612719 100644 --- a/tests/kernel/mem_protect/userspace/src/main.c +++ b/tests/kernel/mem_protect/userspace/src/main.c @@ -110,6 +110,18 @@ ZTEST_USER(userspace, test_is_usermode) zassert_true(k_is_user_context(), "thread left in kernel mode"); } +/** + * @brief Test to check if k_is_pre_kernel works from user mode + * + * @ingroup kernel_memprotect_tests + */ +ZTEST_USER(userspace, test_is_post_kernel) +{ + clear_fault(); + + zassert_false(k_is_pre_kernel(), "still pre-kernel in user mode"); +} + /** * @brief Test to write to a control register * From 5ce408b6472d6fafb5451e91b1bc1e31d008e54d Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Wed, 1 Oct 2025 19:55:26 +0000 Subject: [PATCH 0041/1450] kernel: assert if k_current_get is called pre-kernel k_current_get is not valid pre-kernel. It will return an invalid dummy thread or invalid memory. The invalid memory case can occur when CURRENT_THREAD_USE_TLS is enabled. Assert in k_current_get when called pre-kernel so offending code may be identified. k_is_pre_kernel is moved up in kernel.h to avoid needing a prototype for k_is_pre_kernel. Signed-off-by: Rob Barnes --- include/zephyr/kernel.h | 56 ++++++++++--------- .../tracing/test/tracing_string_format_test.c | 4 +- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h index e3583630b9153..620fc7aefd33a 100644 --- a/include/zephyr/kernel.h +++ b/include/zephyr/kernel.h @@ -687,6 +687,33 @@ __syscall void k_wakeup(k_tid_t thread); __attribute_const__ __syscall k_tid_t k_sched_current_thread_query(void); +/** + * @brief Test whether startup is in the before-main-task phase. + * + * This routine allows the caller to customize its actions, depending on + * whether it being invoked before the kernel is fully active. + * + * @funcprops \isr_ok + * + * @return true if invoked before post-kernel initialization + * @return false if invoked during/after post-kernel initialization + */ +static inline bool k_is_pre_kernel(void) +{ + extern bool z_sys_post_kernel; /* in init.c */ + + /* + * If called from userspace, it must be post kernel. + * This guard is necessary because z_sys_post_kernel memory + * is not accessible to user threads. + */ + if (k_is_user_context()) { + return false; + } + + return !z_sys_post_kernel; +} + /** * @brief Get thread ID of the current thread. * @@ -696,6 +723,8 @@ __syscall k_tid_t k_sched_current_thread_query(void); __attribute_const__ static inline k_tid_t k_current_get(void) { + __ASSERT(!k_is_pre_kernel(), "k_current_get called pre-kernel"); + #ifdef CONFIG_CURRENT_THREAD_USE_TLS /* Thread-local cache of current thread ID, set in z_thread_entry() */ @@ -1274,33 +1303,6 @@ bool k_is_in_isr(void); */ __syscall int k_is_preempt_thread(void); -/** - * @brief Test whether startup is in the before-main-task phase. - * - * This routine allows the caller to customize its actions, depending on - * whether it being invoked before the kernel is fully active. - * - * @funcprops \isr_ok - * - * @return true if invoked before post-kernel initialization - * @return false if invoked during/after post-kernel initialization - */ -static inline bool k_is_pre_kernel(void) -{ - extern bool z_sys_post_kernel; /* in init.c */ - - /* - * If called from user mode, it must already be post kernel. - * This guard is necessary because z_sys_post_kernel memory - * is not accessible to user threads. - */ - if (k_is_user_context()) { - return false; - } - - return !z_sys_post_kernel; -} - /** * @} */ diff --git a/subsys/tracing/test/tracing_string_format_test.c b/subsys/tracing/test/tracing_string_format_test.c index 65250b9f08523..1dec7339fcbb9 100644 --- a/subsys/tracing/test/tracing_string_format_test.c +++ b/subsys/tracing/test/tracing_string_format_test.c @@ -15,7 +15,7 @@ void sys_trace_k_thread_switched_out(void) { struct k_thread *thread; - thread = k_current_get(); + thread = k_sched_current_thread_query(); TRACING_STRING("%s: %p\n", __func__, thread); } @@ -23,7 +23,7 @@ void sys_trace_k_thread_switched_in(void) { struct k_thread *thread; - thread = k_current_get(); + thread = k_sched_current_thread_query(); TRACING_STRING("%s: %p\n", __func__, thread); } From a7f3c1b5e378666fd6a820d71b8b8c49a31cfa47 Mon Sep 17 00:00:00 2001 From: Nulliu Z Date: Sat, 4 Oct 2025 21:39:56 +0800 Subject: [PATCH 0042/1450] ib: multi_heap: fix out-of-bounds array access Add bounds check to prevent accessing heaps array with index=-1 when the address parameter is NULL or too small. Return NULL in such cases to match the API specification. Signed-off-by: Nulliu Z --- lib/heap/multi_heap.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/heap/multi_heap.c b/lib/heap/multi_heap.c index e7579bbff7c13..c782cf0896d46 100644 --- a/lib/heap/multi_heap.c +++ b/lib/heap/multi_heap.c @@ -75,8 +75,11 @@ const struct sys_multi_heap_rec *sys_multi_heap_get_heap(const struct sys_multi_ /* Now i stores the index of the heap after our target (even * if it's invalid and our target is the last!) - * FIXME: return -ENOENT when a proper heap is not found */ + if (i == 0) { + return NULL; + } + return &mheap->heaps[i-1]; } From c0d973d1709981848ba3f54e933cf704e5a61e50 Mon Sep 17 00:00:00 2001 From: jhan bo chao Date: Mon, 25 Aug 2025 22:04:00 +0800 Subject: [PATCH 0043/1450] drivers/espi: rts5912: handler all port 80 data until fifo is empty The rts5912's port 80 has a FIFO. In the ISR (Interrupt Service Routine), extract the FIFO data until the FIFO is empty, otherwise port 80 data will be lost. Signed-off-by: jhan bo chao --- drivers/espi/espi_realtek_rts5912.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/espi/espi_realtek_rts5912.c b/drivers/espi/espi_realtek_rts5912.c index c0c83dcb964df..c87f4cf819f0b 100644 --- a/drivers/espi/espi_realtek_rts5912.c +++ b/drivers/espi/espi_realtek_rts5912.c @@ -684,6 +684,8 @@ static void espi_periph_ch_setup(const struct device *dev) #ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80 +#define P80_MAX_ITEM 16 + static void espi_port80_isr(const struct device *dev) { const struct espi_rts5912_config *const espi_config = dev->config; @@ -693,8 +695,13 @@ static void espi_port80_isr(const struct device *dev) ESPI_PERIPHERAL_NODATA}; volatile struct port80_reg *const port80_reg = espi_config->port80_reg; - evt.evt_data = port80_reg->DATA; - espi_send_callbacks(&espi_data->callbacks, dev, evt); + int i = 0; + + while (!(port80_reg->STS & PORT80_STS_FIFOEM) && i < P80_MAX_ITEM) { + evt.evt_data = port80_reg->DATA; + espi_send_callbacks(&espi_data->callbacks, dev, evt); + i++; + } } static int espi_peri_ch_port80_setup(const struct device *dev) From 6dfad60de79877c263368bcf7bc98bea2b49b97b Mon Sep 17 00:00:00 2001 From: Szymon Janc Date: Tue, 28 Oct 2025 15:51:31 +0100 Subject: [PATCH 0044/1450] tests: bt: host: mock z_sys_post_kernel unit tests needs mocking for z_sys_post_kernel. Signed-off-by: Szymon Janc --- tests/bluetooth/host/conn/mocks/kernel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/bluetooth/host/conn/mocks/kernel.c b/tests/bluetooth/host/conn/mocks/kernel.c index af7a319b8a2a6..47b677025d680 100644 --- a/tests/bluetooth/host/conn/mocks/kernel.c +++ b/tests/bluetooth/host/conn/mocks/kernel.c @@ -39,3 +39,4 @@ DEFINE_FAKE_VALUE_FUNC(void *, k_heap_aligned_alloc, struct k_heap *, size_t, size_t, k_timeout_t); struct k_work_q k_sys_work_q; +bool z_sys_post_kernel = true; From 052855472073ae88a170d242e13fa27325a49d7f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 28 Oct 2025 11:43:20 +0100 Subject: [PATCH 0045/1450] drivers/ethernet/eth_native_tap: Fix use of deprecated kconfig In 200b886d3c579ecbac1083c3ed35bd53f5412444 a deprecated kconfig option was brought back into the driver. Let's fix it. Signed-off-by: Alberto Escolar Piedras --- drivers/ethernet/eth_native_tap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ethernet/eth_native_tap.c b/drivers/ethernet/eth_native_tap.c index 8507e58c14a41..32b7f1aa32b2c 100644 --- a/drivers/ethernet/eth_native_tap.c +++ b/drivers/ethernet/eth_native_tap.c @@ -400,7 +400,7 @@ static void eth_iface_init(struct net_if *iface) } #endif - ctx->dev_fd = eth_iface_create(CONFIG_ETH_NATIVE_POSIX_DEV_NAME, ctx->if_name, false); + ctx->dev_fd = eth_iface_create(CONFIG_ETH_NATIVE_TAP_DEV_NAME, ctx->if_name, false); if (ctx->dev_fd < 0) { LOG_ERR("Cannot create %s (%d/%s)", ctx->if_name, ctx->dev_fd, strerror(-ctx->dev_fd)); From 8b0f33af0446f40462c96da90265c1bdb10519c7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 27 Oct 2025 18:52:57 -0400 Subject: [PATCH 0046/1450] MAINTAINERS file: make doc/build/dts unique to devicetree area Exclude doc/build/dts from build system area. Signed-off-by: Anas Nashif --- MAINTAINERS.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 033f36a407a48..3570ef8738d4c 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -762,6 +762,8 @@ Build system: - scripts/schemas/soc-schema.yaml - scripts/list_shields.py - scripts/snippets.py + files-exclude: + - doc/build/dts/ labels: - "area: Build System" tests: From 8db71e3064c782699ebdce6e9e370fee362fb637 Mon Sep 17 00:00:00 2001 From: Johann Fischer Date: Fri, 24 Oct 2025 16:31:29 +0200 Subject: [PATCH 0047/1450] doc: remove "zephyr,usb-device" from chosen properties documentation Chosen property "zephyr,usb-device" can be used with the deprecated legacy USB device stack, but actually was never used in the tree. There are no plans to use it in the future. Remove it from the documentation, as there seems to be some misunderstanding and the property appears in the board's DTS without any use or benefit. Signed-off-by: Johann Fischer --- doc/build/dts/api/api.rst | 3 --- 1 file changed, 3 deletions(-) diff --git a/doc/build/dts/api/api.rst b/doc/build/dts/api/api.rst index 7352317e9dfa5..aeeea90884f05 100644 --- a/doc/build/dts/api/api.rst +++ b/doc/build/dts/api/api.rst @@ -458,9 +458,6 @@ device. - UART used for :ref:`device_mgmt` * - zephyr,uart-pipe - Sets UART device used by serial pipe driver - * - zephyr,usb-device - - USB device node. If defined and has a ``vbus-gpios`` property, these - will be used by the USB subsystem to enable/disable VBUS * - zephyr,led-strip - A LED-strip node which is used to determine the timings of the WS2812 GPIO driver From f547fb1af544ebe89fe3fe9c6eaa26b29fa9ec33 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 24 Oct 2025 14:02:58 +0200 Subject: [PATCH 0048/1450] video: dcmipp: put Pipe1 / pipe2 caps within preproc if statement Correct compilation error due to usage of DCMIPP_PIPE1 / DCMIPP_PIPE2 on platform which do not have pixel pipes by putting those caps under #if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) Put also DCMIPP_VIDEO_FORMAT_CAP macro inside since this is only used for AUX / MAIN pipes. Fixes: 126aaf6b727 ("video: dcmipp: expose dcmipp caps for all 3 pipes.") Signed-off-by: Alain Volmat --- drivers/video/video_stm32_dcmipp.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/video/video_stm32_dcmipp.c b/drivers/video/video_stm32_dcmipp.c index ab12ab1b1c306..57b51fba24799 100644 --- a/drivers/video/video_stm32_dcmipp.c +++ b/drivers/video/video_stm32_dcmipp.c @@ -1344,18 +1344,6 @@ static int stm32_dcmipp_dequeue(const struct device *dev, struct video_buffer ** #define DCMIPP_CEIL_DIV(val, div) \ (((val) + (div) - 1) / (div)) -#define DCMIPP_VIDEO_FORMAT_CAP(format, pixmul) { \ - .pixelformat = VIDEO_PIX_FMT_##format, \ - .width_min = DCMIPP_CEIL_DIV_ROUND_UP_MUL(CONFIG_VIDEO_STM32_DCMIPP_SENSOR_WIDTH, \ - STM32_DCMIPP_MAX_PIPE_SCALE_FACTOR, \ - pixmul), \ - .width_max = CONFIG_VIDEO_STM32_DCMIPP_SENSOR_WIDTH / (pixmul) * (pixmul), \ - .height_min = DCMIPP_CEIL_DIV(CONFIG_VIDEO_STM32_DCMIPP_SENSOR_HEIGHT, \ - STM32_DCMIPP_MAX_PIPE_SCALE_FACTOR), \ - .height_max = CONFIG_VIDEO_STM32_DCMIPP_SENSOR_HEIGHT, \ - .width_step = pixmul, .height_step = 1, \ -} - static const struct video_format_cap stm32_dcmipp_dump_fmt[] = { { .pixelformat = VIDEO_FOURCC_FROM_STR(CONFIG_VIDEO_STM32_DCMIPP_SENSOR_PIXEL_FORMAT), @@ -1368,6 +1356,19 @@ static const struct video_format_cap stm32_dcmipp_dump_fmt[] = { {0}, }; +#if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) +#define DCMIPP_VIDEO_FORMAT_CAP(format, pixmul) { \ + .pixelformat = VIDEO_PIX_FMT_##format, \ + .width_min = DCMIPP_CEIL_DIV_ROUND_UP_MUL(CONFIG_VIDEO_STM32_DCMIPP_SENSOR_WIDTH, \ + STM32_DCMIPP_MAX_PIPE_SCALE_FACTOR, \ + pixmul), \ + .width_max = CONFIG_VIDEO_STM32_DCMIPP_SENSOR_WIDTH / (pixmul) * (pixmul), \ + .height_min = DCMIPP_CEIL_DIV(CONFIG_VIDEO_STM32_DCMIPP_SENSOR_HEIGHT, \ + STM32_DCMIPP_MAX_PIPE_SCALE_FACTOR), \ + .height_max = CONFIG_VIDEO_STM32_DCMIPP_SENSOR_HEIGHT, \ + .width_step = pixmul, .height_step = 1, \ +} + static const struct video_format_cap stm32_dcmipp_main_fmts[] = { DCMIPP_VIDEO_FORMAT_CAP(RGB565, 8), DCMIPP_VIDEO_FORMAT_CAP(YUYV, 8), @@ -1401,6 +1402,7 @@ static const struct video_format_cap stm32_dcmipp_aux_fmts[] = { DCMIPP_VIDEO_FORMAT_CAP(BGRA32, 4), {0}, }; +#endif static int stm32_dcmipp_get_caps(const struct device *dev, struct video_caps *caps) { @@ -1410,12 +1412,14 @@ static int stm32_dcmipp_get_caps(const struct device *dev, struct video_caps *ca case DCMIPP_PIPE0: caps->format_caps = stm32_dcmipp_dump_fmt; break; +#if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) case DCMIPP_PIPE1: caps->format_caps = stm32_dcmipp_main_fmts; break; case DCMIPP_PIPE2: caps->format_caps = stm32_dcmipp_aux_fmts; break; +#endif default: CODE_UNREACHABLE; } From 47d521fb384796070c07f3673e5f73026ab90751 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 24 Oct 2025 14:17:16 +0200 Subject: [PATCH 0049/1450] tests: drivers: build_all: video: add STM32MP13 dcmipp Add test compilation for the STM32MP13 platform as part of drivers.video.stm32_dcmipp.build since this allow to test build the driver when STM32_DCMIPP_HAS_PIXEL_PIPES is not defined. Signed-off-by: Alain Volmat --- tests/drivers/build_all/video/testcase.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/drivers/build_all/video/testcase.yaml b/tests/drivers/build_all/video/testcase.yaml index cb3e09527d351..d4ff481d36088 100644 --- a/tests/drivers/build_all/video/testcase.yaml +++ b/tests/drivers/build_all/video/testcase.yaml @@ -34,8 +34,10 @@ tests: drivers.video.stm32_dcmipp.build: platform_allow: - stm32n6570_dk/stm32n657xx/sb + - stm32mp135f_dk/stm32mp135fxx extra_args: - platform:stm32n6570_dk/stm32n657xx/sb:SHIELD=st_b_cams_imx_mb1854 + - platform:stm32mp135f_dk/stm32mp135fxx:SHIELD=st_mb1897_cam drivers.video.renesas_ra_ceu.build: platform_allow: - ek_ra8d1/r7fa8d1bhecbd From c5e1b72b54ec6b5164da5f1553e7518f780b5654 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 24 Oct 2025 14:20:09 +0200 Subject: [PATCH 0050/1450] doc: _extensions: apply `ruff format` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Documentation extensions are often edited so bite the bullet and apply `ruff format` on them and stop excluding them in ruff-excludes Signed-off-by: Benjamin Cabé --- .ruff-excludes.toml | 13 ------ doc/_extensions/zephyr/api_overview.py | 10 ++-- doc/_extensions/zephyr/application.py | 46 +++++++++---------- doc/_extensions/zephyr/domain/__init__.py | 20 ++++---- doc/_extensions/zephyr/doxybridge.py | 3 +- doc/_extensions/zephyr/doxyrunner.py | 1 + .../zephyr/doxytooltip/__init__.py | 1 + doc/_extensions/zephyr/dtcompatible-role.py | 1 + doc/_extensions/zephyr/external_content.py | 12 ++--- doc/_extensions/zephyr/gh_utils.py | 18 +++----- doc/_extensions/zephyr/html_redirects.py | 2 +- doc/_extensions/zephyr/kconfig/__init__.py | 45 +++++++++--------- doc/_extensions/zephyr/link-roles.py | 17 ++++--- 13 files changed, 86 insertions(+), 103 deletions(-) diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index 384e588276bfe..a92407467dcb9 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -1225,19 +1225,6 @@ exclude = [ "./arch/xtensa/core/gen_zsr.py", "./arch/xtensa/core/xtensa_intgen.py", "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py", - "./doc/_extensions/zephyr/api_overview.py", - "./doc/_extensions/zephyr/application.py", - "./doc/_extensions/zephyr/domain/__init__.py", - "./doc/_extensions/zephyr/doxybridge.py", - "./doc/_extensions/zephyr/doxyrunner.py", - "./doc/_extensions/zephyr/doxytooltip/__init__.py", - "./doc/_extensions/zephyr/dtcompatible-role.py", - "./doc/_extensions/zephyr/external_content.py", - "./doc/_extensions/zephyr/gh_utils.py", - "./doc/_extensions/zephyr/html_redirects.py", - "./doc/_extensions/zephyr/kconfig/__init__.py", - "./doc/_extensions/zephyr/link-roles.py", - "./doc/_scripts/gen_boards_catalog.py", "./doc/_scripts/gen_devicetree_rest.py", "./doc/_scripts/redirects.py", "./doc/conf.py", diff --git a/doc/_extensions/zephyr/api_overview.py b/doc/_extensions/zephyr/api_overview.py index 028a4ce9df048..52a3561da0319 100644 --- a/doc/_extensions/zephyr/api_overview.py +++ b/doc/_extensions/zephyr/api_overview.py @@ -89,9 +89,7 @@ def visit_group(self, group, all_groups, rows, indent=0): github_uri = self.config.api_overview_base_url + "/releases/tag/" cdef = group.get_compounddef()[0] - ssects = [ - s for p in cdef.get_detaileddescription().get_para() for s in p.get_simplesect() - ] + ssects = [s for p in cdef.get_detaileddescription().get_para() for s in p.get_simplesect()] for sect in ssects: if sect.get_kind() == "since": since = sect.get_para()[0].get_valueOf_() @@ -123,7 +121,7 @@ def visit_group(self, group, all_groups, rows, indent=0): # Next entry will contain the spacer and the link with API name entry = nodes.entry() - span = nodes.Text("".join(["\U000000A0"] * indent)) + span = nodes.Text("".join(["\U000000a0"] * indent)) entry += span # API name with link @@ -143,9 +141,7 @@ def visit_group(self, group, all_groups, rows, indent=0): rows.append(row_node) for innergroup in cdef.get_innergroup(): - self.visit_group( - get_group(innergroup, all_groups), all_groups, rows, indent + 6 - ) + self.visit_group(get_group(innergroup, all_groups), all_groups, rows, indent + 6) def setup(app) -> dict[str, Any]: diff --git a/doc/_extensions/zephyr/application.py b/doc/_extensions/zephyr/application.py index 41e34bac18259..11f150fd30310 100644 --- a/doc/_extensions/zephyr/application.py +++ b/doc/_extensions/zephyr/application.py @@ -11,6 +11,7 @@ ZEPHYR_BASE = Path(__file__).parents[3] + # TODO: extend and modify this for Windows. # # This could be as simple as generating a couple of sets of instructions, one @@ -20,6 +21,7 @@ class ZephyrAppCommandsDirective(Directive): This is a Zephyr directive for generating consistent documentation of the shell commands needed to manage (build, flash, etc.) an application. ''' + has_content = False required_arguments = 0 optional_arguments = 0 @@ -119,10 +121,8 @@ def run(self): build_dir = ('build' + '/' + build_dir_append).rstrip('/') # Prepare repeatable arguments - host_os = [host_os] if host_os != "all" else [v for v in self.HOST_OS - if v != 'all'] - tools = [tool] if tool != "all" else [v for v in self.TOOLS - if v != 'all'] + host_os = [host_os] if host_os != "all" else [v for v in self.HOST_OS if v != 'all'] + tools = [tool] if tool != "all" else [v for v in self.TOOLS if v != 'all'] build_args_list = build_args.split(' ') if build_args is not None else None snippet_list = snippets.split(',') if snippets is not None else None shield_list = shield.split(',') if shield is not None else None @@ -155,7 +155,7 @@ def run(self): 'debug_args': debug_args, 'debugserver_args': debugserver_args, 'attach_args': attach_args, - } + } if 'west' in tools: w = self._generate_west(**run_config) @@ -171,8 +171,7 @@ def run(self): c = self._generate_cmake(**run_config) if tool_comment: paragraph = nodes.paragraph() - paragraph += nodes.Text(tool_comment.format( - f'CMake and {generator}')) + paragraph += nodes.Text(tool_comment.format(f'CMake and {generator}')) content.append(paragraph) content.append(self._lit_block(c)) else: @@ -284,8 +283,10 @@ def _generate_west(self, **kwargs): def _mkdir(mkdir, build_dir, host_os, skip_config): content = [] if skip_config: - content.append(f"# If you already made a build directory ({build_dir}) and ran cmake, " - f"just 'cd {build_dir}' instead.") + content.append( + f"# If you already made a build directory ({build_dir}) and ran cmake, " + f"just 'cd {build_dir}' instead." + ) if host_os == 'all': content.append(f'mkdir {build_dir} && cd {build_dir}') if host_os == "unix": @@ -320,8 +321,7 @@ def _cd_into(self, mkdir, **kwargs): if not app and mkdir and num_slashes == 0: # When there's no app and a single level deep build dir, # simplify output - content.extend(self._mkdir(mkdir, build_dir, 'all', - skip_config)) + content.extend(self._mkdir(mkdir, build_dir, 'all', skip_config)) if not compact: content.append('') return content @@ -383,16 +383,20 @@ def _generate_cmake(self, **kwargs): if not compact: if not cd_into and skip_config: - content.append(f'# If you already ran cmake with -B{build_dir}, you ' - f'can skip this step and run {generator} directly.') + content.append( + f'# If you already ran cmake with -B{build_dir}, you ' + f'can skip this step and run {generator} directly.' + ) else: - content.append(f'# Use cmake to configure a {generator.capitalize()}-based build' - 'system:') + content.append( + f'# Use cmake to configure a {generator.capitalize()}-based buildsystem:' + ) - content.append(f'cmake{cmake_build_dir}{gen_arg}{cmake_args}{snippet_args}{shield_args}{source_dir}') + content.append( + f'cmake{cmake_build_dir}{gen_arg}{cmake_args}{snippet_args}{shield_args}{source_dir}' + ) if not compact: - content.extend(['', - '# Now run the build tool on the generated build system:']) + content.extend(['', '# Now run the build tool on the generated build system:']) if 'build' in goals: content.append(f'{generator}{tool_build_dir}{build_args}') @@ -407,8 +411,4 @@ def _generate_cmake(self, **kwargs): def setup(app): app.add_directive('zephyr-app-commands', ZephyrAppCommandsDirective) - return { - 'version': '1.0', - 'parallel_read_safe': True, - 'parallel_write_safe': True - } + return {'version': '1.0', 'parallel_read_safe': True, 'parallel_write_safe': True} diff --git a/doc/_extensions/zephyr/domain/__init__.py b/doc/_extensions/zephyr/domain/__init__.py index 6b5d8bd45c32c..38cde05f5dcb1 100644 --- a/doc/_extensions/zephyr/domain/__init__.py +++ b/doc/_extensions/zephyr/domain/__init__.py @@ -221,14 +221,18 @@ def convert_node(self, node): json_ld = nodes.raw( "", f"""""", format="html", ) diff --git a/doc/_extensions/zephyr/doxybridge.py b/doc/_extensions/zephyr/doxybridge.py index 6b640fa8822e6..f69984b2715fe 100644 --- a/doc/_extensions/zephyr/doxybridge.py +++ b/doc/_extensions/zephyr/doxybridge.py @@ -40,7 +40,6 @@ class DoxygenGroupDirective(SphinxDirective): } def run(self): - desc_node = addnodes.desc() desc_node["domain"] = "c" desc_node["objtype"] = "group" @@ -52,7 +51,7 @@ def run(self): reftype="group", reftarget=self.arguments[0], refwarn=True, - project=self.options.get("project") + project=self.options.get("project"), ) group_xref += nodes.Text(self.arguments[0]) title_signode += group_xref diff --git a/doc/_extensions/zephyr/doxyrunner.py b/doc/_extensions/zephyr/doxyrunner.py index 45621175ad3b7..f38eec4752b22 100644 --- a/doc/_extensions/zephyr/doxyrunner.py +++ b/doc/_extensions/zephyr/doxyrunner.py @@ -78,6 +78,7 @@ def hash_file(file: Path) -> str: return sha256.hexdigest() + def get_doxygen_option(doxyfile: str, option: str) -> list[str]: """Obtain the value of a Doxygen option. diff --git a/doc/_extensions/zephyr/doxytooltip/__init__.py b/doc/_extensions/zephyr/doxytooltip/__init__.py index 574e65be2c3ba..759236599a59b 100644 --- a/doc/_extensions/zephyr/doxytooltip/__init__.py +++ b/doc/_extensions/zephyr/doxytooltip/__init__.py @@ -19,6 +19,7 @@ RESOURCES_DIR = Path(__file__).parent / "static" + def setup(app: Sphinx) -> dict[str, Any]: app.config.html_static_path.append(RESOURCES_DIR.as_posix()) diff --git a/doc/_extensions/zephyr/dtcompatible-role.py b/doc/_extensions/zephyr/dtcompatible-role.py index 5cda7d348924d..c2272a00a9fe6 100644 --- a/doc/_extensions/zephyr/dtcompatible-role.py +++ b/doc/_extensions/zephyr/dtcompatible-role.py @@ -11,6 +11,7 @@ in the right places. """ + def setup(app): app.add_crossref_type('dtcompatible', 'dtcompatible') diff --git a/doc/_extensions/zephyr/external_content.py b/doc/_extensions/zephyr/external_content.py index a2ab020d4c9dd..0321a81797d0f 100644 --- a/doc/_extensions/zephyr/external_content.py +++ b/doc/_extensions/zephyr/external_content.py @@ -102,10 +102,7 @@ def sync_contents(app: Sphinx) -> None: to_copy = [] to_delete = set(f for f in srcdir.glob("**/*") if not f.is_dir()) to_keep = set( - f - for k in app.config.external_content_keep - for f in srcdir.glob(k) - if not f.is_dir() + f for k in app.config.external_content_keep for f in srcdir.glob(k) if not f.is_dir() ) def _pattern_excludes(f): @@ -117,8 +114,11 @@ def _pattern_excludes(f): for src in prefix_src.glob(glob): if src.is_dir(): to_copy.extend( - [(f, prefix_src) for f in src.glob("**/*") if - (not f.is_dir() and not _pattern_excludes(f))] + [ + (f, prefix_src) + for f in src.glob("**/*") + if (not f.is_dir() and not _pattern_excludes(f)) + ] ) elif not _pattern_excludes(src): to_copy.append((src, prefix_src)) diff --git a/doc/_extensions/zephyr/gh_utils.py b/doc/_extensions/zephyr/gh_utils.py index db89dc3a988cc..908c3cfd8d995 100644 --- a/doc/_extensions/zephyr/gh_utils.py +++ b/doc/_extensions/zephyr/gh_utils.py @@ -50,8 +50,8 @@ from get_maintainer import Maintainers -ZEPHYR_BASE : Final[str] = Path(__file__).parents[3] -MAINTAINERS : Final[Maintainers] = Maintainers(filename=f"{ZEPHYR_BASE}/MAINTAINERS.yml") +ZEPHYR_BASE: Final[str] = Path(__file__).parents[3] +MAINTAINERS: Final[Maintainers] = Maintainers(filename=f"{ZEPHYR_BASE}/MAINTAINERS.yml") __version__ = "0.1.0" @@ -140,15 +140,8 @@ def gh_link_get_open_issue_url(app: Sphinx, pagename: str, sha1: str) -> str | N form_data = { "template": "001_bug_report.yml", "title": f"doc: Documentation issue in '{pagename}'", - "labels": [ - "bug", - "area: Documentation" - ], - "env": ( - f"- Page: {pagename}\n" - f"- Version: {app.config.gh_link_version}\n" - f"- SHA-1: {sha1}" - ), + "labels": ["bug", "area: Documentation"], + "env": (f"- Page: {pagename}\n- Version: {app.config.gh_link_version}\n- SHA-1: {sha1}"), "context": ( "This issue was reported from the online documentation page using the " "'Report an issue' button." @@ -213,7 +206,7 @@ def git_info_filter(app: Sphinx, pagename) -> tuple[str, str] | None: .decode("utf-8") .strip() ) - if not date_and_sha1: # added but not committed + if not date_and_sha1: # added but not committed return None date, sha1 = date_and_sha1.split(" ", 1) date_object = datetime.fromtimestamp(int(date)) @@ -225,6 +218,7 @@ def git_info_filter(app: Sphinx, pagename) -> tuple[str, str] | None: except subprocess.CalledProcessError: return None + def add_jinja_filter(app: Sphinx): if app.builder.format != "html": return diff --git a/doc/_extensions/zephyr/html_redirects.py b/doc/_extensions/zephyr/html_redirects.py index f3280c27d3718..25b804f59837f 100644 --- a/doc/_extensions/zephyr/html_redirects.py +++ b/doc/_extensions/zephyr/html_redirects.py @@ -67,7 +67,7 @@ def create_redirect_pages(app, exception): if not isinstance(app.builder, StandaloneHTMLBuilder): return # only relevant for standalone HTML output - for (old_url, new_url) in app.config.html_redirect_pages: + for old_url, new_url in app.config.html_redirect_pages: if old_url.startswith('/'): old_url = old_url[1:] diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py index 704415eac101f..e977a3b734a8f 100644 --- a/doc/_extensions/zephyr/kconfig/__init__.py +++ b/doc/_extensions/zephyr/kconfig/__init__.py @@ -81,9 +81,9 @@ def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, kconfiglib.Kconfig, d kconfig = "" sysbuild_kconfig = "" for module in modules: - kconfig_module_dirs += zephyr_module.process_kconfig_module_dir(module.project, - module.meta, - False) + kconfig_module_dirs += zephyr_module.process_kconfig_module_dir( + module.project, module.meta, False + ) kconfig += zephyr_module.process_kconfig(module.project, module.meta) sysbuild_kconfig += zephyr_module.process_sysbuildkconfig(module.project, module.meta) @@ -128,9 +128,14 @@ def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, kconfiglib.Kconfig, d f.write(kconfig) (Path(td) / 'boards').mkdir(exist_ok=True) - root_args = argparse.Namespace(**{'board_roots': [Path(ZEPHYR_BASE)], - 'soc_roots': [Path(ZEPHYR_BASE)], 'board': None, - 'board_dir': []}) + root_args = argparse.Namespace( + **{ + 'board_roots': [Path(ZEPHYR_BASE)], + 'soc_roots': [Path(ZEPHYR_BASE)], + 'board': None, + 'board_dir': [], + } + ) v2_boards = list_boards.find_v2_boards(root_args).values() with open(Path(td) / "boards" / "Kconfig.boards", "w") as f: @@ -219,9 +224,7 @@ class KconfigSearch(SphinxDirective): def run(self): if not self.config.kconfig_generate_db: - raise ExtensionError( - "Kconfig search directive can not be used without database" - ) + raise ExtensionError("Kconfig search directive can not be used without database") if "kconfig_search_inserted" in self.env.temp_data: raise ExtensionError("Kconfig search directive can only be used once") @@ -257,8 +260,14 @@ def found_kconfig_search_directive(self) -> bool: class KconfigRegexRole(XRefRole): """Role for creating links to Kconfig regex searches.""" - def process_link(self, env: BuildEnvironment, refnode: nodes.Element, has_explicit_title: bool, - title: str, target: str) -> tuple[str, str]: + def process_link( + self, + env: BuildEnvironment, + refnode: nodes.Element, + has_explicit_title: bool, + title: str, + target: str, + ) -> tuple[str, str]: # render as "normal" text when explicit title is provided, literal otherwise if has_explicit_title: self.innernodeclass = nodes.inline @@ -316,9 +325,7 @@ def resolve_xref( if match: todocname, anchor = match[0] - return make_refnode( - builder, fromdocname, todocname, anchor, contnode, anchor - ) + return make_refnode(builder, fromdocname, todocname, anchor, contnode, anchor) else: return None @@ -347,9 +354,7 @@ def _find_search_docname(self, env: BuildEnvironment) -> str | None: def add_option(self, option): """Register a new Kconfig option to the domain.""" - self.data["options"].add( - (option, option, "option", self.env.docname, option, 1) - ) + self.data["options"].add((option, option, "option", self.env.docname, option, 1)) def sc_fmt(sc): @@ -535,11 +540,7 @@ def kconfig_install( doctree: nodes.Node | None, ) -> None: """Install the Kconfig library files on pages that require it.""" - if ( - not app.config.kconfig_generate_db - or app.builder.format != "html" - or not doctree - ): + if not app.config.kconfig_generate_db or app.builder.format != "html" or not doctree: return visitor = _FindKconfigSearchDirectiveVisitor(doctree) diff --git a/doc/_extensions/zephyr/link-roles.py b/doc/_extensions/zephyr/link-roles.py index b66289acb932b..5de60fd934ca5 100644 --- a/doc/_extensions/zephyr/link-roles.py +++ b/doc/_extensions/zephyr/link-roles.py @@ -108,9 +108,7 @@ def role( rev = project.revision # No module provided elif module is None: - raise ValueError( - f"Role 'module_file' must take a module as an argument\n\t{trace}" - ) + raise ValueError(f"Role 'module_file' must take a module as an argument\n\t{trace}") # Invalid module provided elif module != config.link_roles_manifest_project: logger.debug(f"Module {module} not found in the west manifest") @@ -122,13 +120,14 @@ def role( if module == config.link_roles_manifest_project: p = Path(source).relative_to(inliner.document.settings.env.srcdir) - if not any( - p.match(glob) - for glob in config.link_roles_manifest_project_broken_links_ignore_globs - ) and not Path(ZEPHYR_BASE, link).exists(): - logger.warning( - f"{link} not found in {config.link_roles_manifest_project} {trace}" + if ( + not any( + p.match(glob) + for glob in config.link_roles_manifest_project_broken_links_ignore_globs ) + and not Path(ZEPHYR_BASE, link).exists() + ): + logger.warning(f"{link} not found in {config.link_roles_manifest_project} {trace}") url = f"{baseurl}/{format}/{rev}/{link}{line_ref}" node = nodes.reference(rawtext, link_text, refuri=url, **options) From afa7b8c9e69088e457f58597249411c9e9a829c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 24 Oct 2025 14:30:29 +0200 Subject: [PATCH 0051/1450] doc: _scripts: fix SIM905 linter rule in gen_devicetree_rest.py MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit replace str.split() with an actual set of strings Signed-off-by: Benjamin Cabé --- .ruff-excludes.toml | 3 --- doc/_scripts/gen_devicetree_rest.py | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index a92407467dcb9..af5c24fd36bf9 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -44,9 +44,6 @@ "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] -"./doc/_scripts/gen_devicetree_rest.py" = [ - "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string -] "./doc/_scripts/redirects.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long ] diff --git a/doc/_scripts/gen_devicetree_rest.py b/doc/_scripts/gen_devicetree_rest.py index 2d12a79587184..82c18b085ee06 100644 --- a/doc/_scripts/gen_devicetree_rest.py +++ b/doc/_scripts/gen_devicetree_rest.py @@ -29,7 +29,7 @@ ZEPHYR_BASE = Path(__file__).parents[2] # Base properties that have documentation in 'dt-important-props'. -DETAILS_IN_IMPORTANT_PROPS = set('compatible label reg status interrupts'.split()) +DETAILS_IN_IMPORTANT_PROPS = {'compatible', 'label', 'reg', 'status', 'interrupts'} logger = logging.getLogger('gen_devicetree_rest') From a825e014d858eb2badd600da6f3163e413b6bf3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20St=C4=99pnicki?= Date: Fri, 24 Oct 2025 13:33:13 +0200 Subject: [PATCH 0052/1450] arch: riscv: core: vector_table alignement fix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For RISCV vector table needs to be aligned depending on CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN. This was missing when using LTO making issues when direct ISR were in use. Signed-off-by: Łukasz Stępnicki --- arch/riscv/core/vector_table.ld | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/core/vector_table.ld b/arch/riscv/core/vector_table.ld index 6a93082ed894e..5667b8935b8ed 100644 --- a/arch/riscv/core/vector_table.ld +++ b/arch/riscv/core/vector_table.ld @@ -6,6 +6,7 @@ #if LINKER_ZEPHYR_FINAL && defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) KEEP(*(.vectors.__start)) +. = ALIGN(CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN); INCLUDE isr_tables_vt.ld #else KEEP(*(.vectors.*)) From 3e4e1c52fbed3bd22fd1c978b1b9422bef885ba4 Mon Sep 17 00:00:00 2001 From: Yasushi SHOJI Date: Fri, 24 Oct 2025 20:15:38 +0900 Subject: [PATCH 0053/1450] drivers: timer: Improve wording for AMD Xilinx PS TTC support Clarify that the AMD Xilinx PS Triple Timer Counter (TTC) is used in both Zynq UltraScale+ MPSoC (ZynqMP) and Versal platforms. Update the device tree binding description and Kconfig accordingly. Also, rephrase the Kconfig help text to fix grammar issues and improve clarity. Signed-off-by: Yasushi SHOJI --- drivers/timer/Kconfig.xlnx_psttc | 11 ++++++----- dts/bindings/timer/xlnx,ttcps.yaml | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/timer/Kconfig.xlnx_psttc b/drivers/timer/Kconfig.xlnx_psttc index 8cd0a2619a8a7..3004086c834e3 100644 --- a/drivers/timer/Kconfig.xlnx_psttc +++ b/drivers/timer/Kconfig.xlnx_psttc @@ -4,17 +4,18 @@ # SPDX-License-Identifier: Apache-2.0 config XLNX_PSTTC_TIMER - bool "Xilinx PS ttc timer support" + bool "Xilinx PS Triple-Timer Counter support" default y depends on DT_HAS_XLNX_TTCPS_ENABLED select TICKLESS_CAPABLE help - This module implements a kernel device driver for the Xilinx ZynqMP - platform provides the standard "system clock driver" interfaces. - If unchecked, no timer will be used. + Enable the AMD Xilinx PS Triple Timer Counter (TTC) timer driver for + Zynq UltraScale+ MPSoC (ZynqMP) and Versal platforms. This TTC-based + timer driver provides the "standard system clock driver" interface. + If disabled, the TTC will not be used as the system timer. config XLNX_PSTTC_TIMER_INDEX - int "Xilinx PS ttc timer index" + int "Xilinx PS Triple-Timer Counter index" range 0 3 default 0 depends on XLNX_PSTTC_TIMER diff --git a/dts/bindings/timer/xlnx,ttcps.yaml b/dts/bindings/timer/xlnx,ttcps.yaml index 44450fe144780..7e64bffe7aa69 100644 --- a/dts/bindings/timer/xlnx,ttcps.yaml +++ b/dts/bindings/timer/xlnx,ttcps.yaml @@ -1,4 +1,4 @@ -description: Xilinx ZynqMP PS TTC timer +description: Xilinx PS Triple-Timer Counter compatible: "xlnx,ttcps" From 6ec763474f6593ceafe70f79731247ede3721984 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Fri, 24 Oct 2025 13:03:03 +0200 Subject: [PATCH 0054/1450] soc: nordic: nrf54h: Disable S2RAM on cpurad MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On nrf54h20 only cpuapp supports s2ram low power cpu state. Signed-off-by: Sebastian Głąb --- soc/nordic/nrf54h/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index d5632943e19f7..ac25cff79150b 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -65,7 +65,6 @@ config SOC_NRF54H20_CPURAD_COMMON select HAS_NORDIC_DMM select HAS_NORDIC_RAM_CTRL select HAS_PM - select HAS_PM_S2RAM_CUSTOM_MARKING select HAS_POWEROFF config SOC_NRF54H20_CPURAD_ENABLE From 182a6c62b140873c4ff284d13d6837fcf9029036 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Krzysztof=20Chru=C5=9Bci=C5=84ski?= Date: Mon, 13 Oct 2025 10:34:32 +0200 Subject: [PATCH 0055/1450] drivers: timer: nrf_rtc: Kconfig clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove redundant enabling of NRF_RTC_TIMER in SoC specific files and replace it with default y in the NRF_RTC_TIMER definition. Signed-off-by: Krzysztof Chruściński --- boards/native/nrf_bsim/Kconfig | 3 --- drivers/timer/Kconfig.nrf_rtc | 1 + soc/nordic/nrf51/Kconfig.defconfig | 4 ---- soc/nordic/nrf52/Kconfig.defconfig | 4 ---- soc/nordic/nrf53/Kconfig.defconfig | 4 ---- soc/nordic/nrf91/Kconfig.defconfig | 4 ---- 6 files changed, 1 insertion(+), 19 deletions(-) diff --git a/boards/native/nrf_bsim/Kconfig b/boards/native/nrf_bsim/Kconfig index 3596ccec0240a..9df6cfd2243fb 100644 --- a/boards/native/nrf_bsim/Kconfig +++ b/boards/native/nrf_bsim/Kconfig @@ -5,7 +5,6 @@ config BOARD_NRF52_BSIM bool select SOC_SERIES_BSIM_NRF52X select SOC_COMPATIBLE_NRF52833 - select NRF_RTC_TIMER select CLOCK_CONTROL help NRF52 simulation model @@ -16,7 +15,6 @@ config BOARD_NRF5340BSIM_NRF5340_CPUNET bool select SOC_SERIES_BSIM_NRF53X select SOC_COMPATIBLE_NRF5340_CPUNET - select NRF_RTC_TIMER select CLOCK_CONTROL help Simulated NRF53 Network core @@ -27,7 +25,6 @@ config BOARD_NRF5340BSIM_NRF5340_CPUAPP bool select SOC_SERIES_BSIM_NRF53X select SOC_COMPATIBLE_NRF5340_CPUAPP - select NRF_RTC_TIMER select CLOCK_CONTROL help Simulated NRF53 Application core diff --git a/drivers/timer/Kconfig.nrf_rtc b/drivers/timer/Kconfig.nrf_rtc index 1ddd473c01a09..c045f85f240cb 100644 --- a/drivers/timer/Kconfig.nrf_rtc +++ b/drivers/timer/Kconfig.nrf_rtc @@ -11,6 +11,7 @@ config NRF_RTC_TIMER select TICKLESS_CAPABLE select SYSTEM_TIMER_HAS_DISABLE_SUPPORT select NRFX_PPI if SOC_NRF52832 + default y if SYS_CLOCK_EXISTS help This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard "system clock driver" diff --git a/soc/nordic/nrf51/Kconfig.defconfig b/soc/nordic/nrf51/Kconfig.defconfig index 67f1eb86e39fb..dad7aedf09c8b 100644 --- a/soc/nordic/nrf51/Kconfig.defconfig +++ b/soc/nordic/nrf51/Kconfig.defconfig @@ -9,10 +9,6 @@ if SOC_SERIES_NRF51X config NUM_IRQS default 26 -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_nodelabel_int_prop,rtc1,clock-frequency) diff --git a/soc/nordic/nrf52/Kconfig.defconfig b/soc/nordic/nrf52/Kconfig.defconfig index 7908f14561ef5..a8220ea2f4891 100644 --- a/soc/nordic/nrf52/Kconfig.defconfig +++ b/soc/nordic/nrf52/Kconfig.defconfig @@ -7,10 +7,6 @@ if SOC_SERIES_NRF52X rsource "Kconfig.defconfig.nrf52*" -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_nodelabel_int_prop,rtc1,clock-frequency) diff --git a/soc/nordic/nrf53/Kconfig.defconfig b/soc/nordic/nrf53/Kconfig.defconfig index bd0b9cb6d27df..82974c027426c 100644 --- a/soc/nordic/nrf53/Kconfig.defconfig +++ b/soc/nordic/nrf53/Kconfig.defconfig @@ -7,10 +7,6 @@ if SOC_SERIES_NRF53X rsource "Kconfig.defconfig.nrf53*" -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_nodelabel_int_prop,rtc1,clock-frequency) diff --git a/soc/nordic/nrf91/Kconfig.defconfig b/soc/nordic/nrf91/Kconfig.defconfig index 81fce08e5dd49..bad2765c1b0c9 100644 --- a/soc/nordic/nrf91/Kconfig.defconfig +++ b/soc/nordic/nrf91/Kconfig.defconfig @@ -7,10 +7,6 @@ if SOC_SERIES_NRF91X rsource "Kconfig.defconfig.nrf91*" -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_nodelabel_int_prop,rtc1,clock-frequency) From 396466ed1789f06a2c2a329f58711a72aab34ea1 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Mon, 20 Oct 2025 10:32:01 +0100 Subject: [PATCH 0056/1450] scripts: snippets: Update to use jsonschema instead of pykwalify Updates the schema and script to use jsonschema Signed-off-by: Jamie McCrae --- scripts/schemas/snippet-schema.yaml | 57 +++++++++++++++++++++++++++++ scripts/schemas/snippet-schema.yml | 49 ------------------------- scripts/snippets.py | 33 +++++++---------- 3 files changed, 70 insertions(+), 69 deletions(-) create mode 100644 scripts/schemas/snippet-schema.yaml delete mode 100644 scripts/schemas/snippet-schema.yml diff --git a/scripts/schemas/snippet-schema.yaml b/scripts/schemas/snippet-schema.yaml new file mode 100644 index 0000000000000..360ff2caf0f1d --- /dev/null +++ b/scripts/schemas/snippet-schema.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2022-2025, Nordic Semiconductor ASA + +# JSON Schema for snippet YAML files +# When possible, constraints and validation rules should be modeled directly in this file. + +# Example usage of applying a snippet to all boards: +# name: foo +# append: +# EXTRA_DTC_OVERLAY_FILE: m3.overlay + +# Example usage of applying a snippet to one specific board: +# name: foo +# boards: +# qemu_cortex_m3: +# append: +# EXTRA_DTC_OVERLAY_FILE: m3.overlay + +$schema: "https://json-schema.org/draft/2020-12/schema" +$id: "https://zephyrproject.org/schemas/zephyr/snippet" +title: Zephyr snippet Schema +description: Schema for validating Zephyr snippet files +type: object +$defs: + append-schema: + # Sub-schema for appending onto CMake list variables. + # See uses under '$ref: "#/$defs/append-schema"' keys below. + type: object + properties: + EXTRA_DTC_OVERLAY_FILE: + type: string + EXTRA_CONF_FILE: + type: string + SB_EXTRA_CONF_FILE: + type: string + DTS_EXTRA_CPPFLAGS: + type: string + additionalProperties: false + +properties: + name: + type: string + append: + $ref: "#/$defs/append-schema" + boards: + type: object + patternProperties: + "(.*)": + type: object + properties: + append: + $ref: "#/$defs/append-schema" + additionalProperties: false +required: + - name +additionalProperties: false diff --git a/scripts/schemas/snippet-schema.yml b/scripts/schemas/snippet-schema.yml deleted file mode 100644 index 319097c58f8d7..0000000000000 --- a/scripts/schemas/snippet-schema.yml +++ /dev/null @@ -1,49 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2022, Nordic Semiconductor ASA - -# A pykwalify schema for basic validation of the snippet.yml format. - -schema;append-schema: - # Sub-schema for appending onto CMake list variables. - # See uses under 'append:' keys below. - type: map - mapping: - EXTRA_DTC_OVERLAY_FILE: - type: str - EXTRA_CONF_FILE: - type: str - SB_EXTRA_CONF_FILE: - type: str - DTS_EXTRA_CPPFLAGS: - type: str - -type: map -mapping: - name: - required: true - type: str - append: - example: | - Snippet-wide appending can be done here: - - name: foo - append: - EXTRA_DTC_OVERLAY_FILE: m3.overlay - include: append-schema - boards: - example: | - Board-specific appending can be done here: - - name: foo - boards: - qemu_cortex_m3: - append: - EXTRA_DTC_OVERLAY_FILE: m3.overlay - type: map - mapping: - regex;(.*): - type: map - mapping: - append: - include: append-schema diff --git a/scripts/snippets.py b/scripts/snippets.py index d725f08891e0a..2b5f6a5e428be 100644 --- a/scripts/snippets.py +++ b/scripts/snippets.py @@ -18,16 +18,15 @@ from dataclasses import dataclass, field from pathlib import Path, PurePosixPath from typing import Dict, Iterable, List, Set +from jsonschema.exceptions import best_match import argparse import logging import os -import pykwalify.core -import pykwalify.errors import re import sys -import textwrap import yaml import platform +import jsonschema # Marker type for an 'append:' configuration. Maps variables # to the list of values to append to them. @@ -50,7 +49,7 @@ class Snippet: def process_data(self, pathobj: Path, snippet_data: dict, sysbuild: bool): '''Process the data in a snippet.yml file, after it is loaded into a - python object and validated by pykwalify.''' + python object and validated by jsonschema.''' def append_value(variable, value): if variable in ('SB_EXTRA_CONF_FILE', 'EXTRA_DTC_OVERLAY_FILE', 'EXTRA_CONF_FILE'): path = pathobj.parent / value @@ -181,9 +180,9 @@ def print(self, *args, **kwargs): kwargs['file'] = self.out_file print(*args, **kwargs) -# Name of the file containing the pykwalify schema for snippet.yml +# Name of the file containing the jsonschema schema for snippet.yml # files. -SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'snippet-schema.yml') +SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'snippet-schema.yaml') with open(SCHEMA_PATH, 'r') as f: SNIPPET_SCHEMA = yaml.safe_load(f.read()) @@ -221,10 +220,6 @@ def parse_args(): return parser.parse_args() def setup_logging(): - # Silence validation errors from pykwalify, which are logged at - # logging.ERROR level. We want to handle those ourselves as - # needed. - logging.getLogger('pykwalify').setLevel(logging.CRITICAL) logging.basicConfig(level=logging.INFO, format=' %(name)s: %(message)s') @@ -296,17 +291,15 @@ def load_snippet_yml(snippet_yml: Path) -> dict: except yaml.scanner.ScannerError: _err(f'snippets file {snippet_yml} is invalid YAML') - def pykwalify_err(e): - return f'''\ -invalid {SNIPPET_YML} file: {snippet_yml} -{textwrap.indent(e.msg, ' ')} -''' + validator_class = jsonschema.validators.validator_for(SNIPPET_SCHEMA) + validator_class.check_schema(SNIPPET_SCHEMA) + snippet_validator = validator_class(SNIPPET_SCHEMA) + errors = list(snippet_validator.iter_errors(snippet_data)) - try: - pykwalify.core.Core(source_data=snippet_data, - schema_data=SNIPPET_SCHEMA).validate() - except pykwalify.errors.PyKwalifyException as e: - _err(pykwalify_err(e)) + if errors: + sys.exit('ERROR: Malformed snippet YAML file: ' + f'{snippet_yml.as_posix()}\n' + f'{best_match(errors).message} in {best_match(errors).json_path}') name = snippet_data['name'] if not SNIPPET_NAME_RE.fullmatch(name): From bca090958bde928df26adebc1c12f8b7f37f60dc Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Fri, 24 Oct 2025 12:58:30 +0200 Subject: [PATCH 0057/1450] soc: silabs: silabs_s2: Fix radio interrupt init condition Radio interrupts were only initialized if CONFIG_ARM_SECURE_FIRMWARE=y, but should be initialized independently of security configuration. Move initialization from soc_prep_hook() to soc_early_init_hook(), there is no reason to configure interrupts earlier. Signed-off-by: Aksel Skauge Mellbye --- soc/silabs/silabs_s2/soc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/soc/silabs/silabs_s2/soc.c b/soc/silabs/silabs_s2/soc.c index bfdfc0847b2c9..b43a6176c62f5 100644 --- a/soc/silabs/silabs_s2/soc.c +++ b/soc/silabs/silabs_s2/soc.c @@ -55,6 +55,9 @@ void soc_early_init_hook(void) if (IS_ENABLED(CONFIG_PM)) { sl_power_manager_init(); } + if (IS_ENABLED(CONFIG_SOC_GECKO_USE_RAIL)) { + rail_isr_installer(); + } } #if defined(CONFIG_ARM_SECURE_FIRMWARE) && !defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS) @@ -114,9 +117,5 @@ void soc_prep_hook(void) IRQ_DIRECT_CONNECT(SMU_SECURE_IRQn, 0, smu_fault, 0); irq_enable(SMU_SECURE_IRQn); - - if (IS_ENABLED(CONFIG_SOC_GECKO_USE_RAIL)) { - rail_isr_installer(); - } #endif } From 2fa6e07eef4b5f12aa57d7ace711397c24753622 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 24 Oct 2025 16:11:23 +0200 Subject: [PATCH 0058/1450] drivers: dma: siwx91x: Simplify descriptors list creation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The management of the single-linked list was made in various places: - RSI_GPDMA_BuildDescriptors() - after sys_mem_blocks_alloc() - at the end of the loop Centralize it at the end of the loop. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx91x_gpdma.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dma_silabs_siwx91x_gpdma.c b/drivers/dma/dma_silabs_siwx91x_gpdma.c index 2cc6bb95fe9ca..b87469f63adb0 100644 --- a/drivers/dma/dma_silabs_siwx91x_gpdma.c +++ b/drivers/dma/dma_silabs_siwx91x_gpdma.c @@ -170,14 +170,10 @@ static int siwx91x_gpdma_desc_config(struct siwx19x_gpdma_data *data, goto free_desc; } - if (prev_desc == NULL) { - data->chan_info[channel].desc = cur_desc; - } - memset(cur_desc, 0, 32); ret = RSI_GPDMA_BuildDescriptors(&data->hal_ctx, (RSI_GPDMA_DESC_T *)xfer_cfg, - cur_desc, prev_desc); + cur_desc, NULL); if (ret) { goto free_desc; } @@ -194,6 +190,12 @@ static int siwx91x_gpdma_desc_config(struct siwx19x_gpdma_data *data, cur_desc->chnlCtrlConfig.srcFifoMode = 1; } + + if (prev_desc) { + prev_desc->pNextLink = (void *)cur_desc; + } else { + data->chan_info[channel].desc = cur_desc; + } prev_desc = cur_desc; block_addr = block_addr->next_block; } From b359d5d29b59ba222092abfdd96cb89b806b5c9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 24 Oct 2025 16:11:23 +0200 Subject: [PATCH 0059/1450] drivers: dma: siwx91x: Simplify variables naming MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the single-linked list management is well localized, the variable names can now be abbreviated a bit. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx91x_gpdma.c | 51 ++++++++++++-------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/dma/dma_silabs_siwx91x_gpdma.c b/drivers/dma/dma_silabs_siwx91x_gpdma.c index b87469f63adb0..b52ac2916fc01 100644 --- a/drivers/dma/dma_silabs_siwx91x_gpdma.c +++ b/drivers/dma/dma_silabs_siwx91x_gpdma.c @@ -145,62 +145,57 @@ static int siwx91x_gpdma_desc_config(struct siwx19x_gpdma_data *data, const RSI_GPDMA_DESC_T *xfer_cfg, uint32_t channel) { int operation_width = config->source_data_size * config->source_burst_length; - const struct dma_block_config *block_addr = config->head_block; - RSI_GPDMA_DESC_T *cur_desc = NULL; - RSI_GPDMA_DESC_T *prev_desc = NULL; + const struct dma_block_config *block = config->head_block; + RSI_GPDMA_DESC_T *desc, *prev = NULL; k_spinlock_key_t key; int ret; for (int i = 0; i < config->block_count; i++) { - if (!IS_ALIGNED(block_addr->source_address, config->source_burst_length) || - !IS_ALIGNED(block_addr->dest_address, config->dest_burst_length) || - !IS_ALIGNED(block_addr->block_size, operation_width)) { + if (!IS_ALIGNED(block->source_address, config->source_burst_length) || + !IS_ALIGNED(block->dest_address, config->dest_burst_length) || + !IS_ALIGNED(block->block_size, operation_width)) { LOG_ERR("Buffer not aligned"); goto free_desc; } - if (block_addr->block_size >= GPDMA_DESC_MAX_TRANSFER_SIZE) { - LOG_ERR("Buffer too large (%d bytes)", block_addr->block_size); + if (block->block_size >= GPDMA_DESC_MAX_TRANSFER_SIZE) { + LOG_ERR("Buffer too large (%d bytes)", block->block_size); goto free_desc; } key = k_spin_lock(&data->desc_pool_lock); - ret = sys_mem_blocks_alloc(data->desc_pool, 1, (void **)&cur_desc); + ret = sys_mem_blocks_alloc(data->desc_pool, 1, (void **)&desc); k_spin_unlock(&data->desc_pool_lock, key); if (ret) { goto free_desc; } - memset(cur_desc, 0, 32); - + memset(desc, 0, 32); ret = RSI_GPDMA_BuildDescriptors(&data->hal_ctx, (RSI_GPDMA_DESC_T *)xfer_cfg, - cur_desc, NULL); + desc, NULL); if (ret) { goto free_desc; } - - cur_desc->src = (void *)block_addr->source_address; - cur_desc->dest = (void *)block_addr->dest_address; - cur_desc->chnlCtrlConfig.transSize = block_addr->block_size; - - if (block_addr->dest_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { - cur_desc->chnlCtrlConfig.dstFifoMode = 1; + desc->src = (void *)block->source_address; + desc->dest = (void *)block->dest_address; + desc->chnlCtrlConfig.transSize = block->block_size; + if (block->dest_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { + desc->chnlCtrlConfig.dstFifoMode = 1; } - - if (block_addr->source_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { - cur_desc->chnlCtrlConfig.srcFifoMode = 1; + if (block->source_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { + desc->chnlCtrlConfig.srcFifoMode = 1; } - if (prev_desc) { - prev_desc->pNextLink = (void *)cur_desc; + if (prev) { + prev->pNextLink = (void *)desc; } else { - data->chan_info[channel].desc = cur_desc; + data->chan_info[channel].desc = desc; } - prev_desc = cur_desc; - block_addr = block_addr->next_block; + prev = desc; + block = block->next_block; } - if (block_addr != NULL) { + if (block != NULL) { /* next_block address for last block must be null */ goto free_desc; } From 42eff40bdcb15efeceefc4ee671f43ebc9928546 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 24 Oct 2025 11:21:13 +0200 Subject: [PATCH 0060/1450] drivers: dma: siwx91x: Fix DMA_ADDR_ADJ_NO_CHANGE w/ memory source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GPDMA does not support DMA_ADDR_ADJ_NO_CHANGE with a memory buffer. This feature is required for the SPI driver. Hopefully, SPI driver is the only user of this feature. Therefore, this commit introduces a hack for SPI. When the user request an Rx transaction, rather than copying content of mosi_overrun parameter, it configures the DMA to fill the destination memory (with either 0s or 1s). Obviously, this only works if mosi_overrun is 0x00 or 0xFF. Hopefully, none will need any other value. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx91x_gpdma.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/dma/dma_silabs_siwx91x_gpdma.c b/drivers/dma/dma_silabs_siwx91x_gpdma.c index b52ac2916fc01..177c80678bb3a 100644 --- a/drivers/dma/dma_silabs_siwx91x_gpdma.c +++ b/drivers/dma/dma_silabs_siwx91x_gpdma.c @@ -183,6 +183,22 @@ static int siwx91x_gpdma_desc_config(struct siwx19x_gpdma_data *data, } if (block->source_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { desc->chnlCtrlConfig.srcFifoMode = 1; + /* HACK: GPDMA does not support DMA_ADDR_ADJ_NO_CHANGE with a memory buffer. + * So, instead of transferring the real data, we fill the peripheral with 0s + * or 1s. It should be sufficient for most of the SPI usages. We hope the + * users won't need any values other than 0x00 of 0xFF. + */ + if (config->channel_direction == MEMORY_TO_PERIPHERAL) { + desc->miscChnlCtrlConfig.memoryFillEn = 1; + if (*(uint8_t *)block->source_address == 0xFF) { + desc->miscChnlCtrlConfig.memoryOneFill = 1; + } else if (*(uint8_t *)block->source_address == 0x00) { + desc->miscChnlCtrlConfig.memoryOneFill = 0; + } else { + LOG_ERR("Only 0xFF and 0x00 are supported as input"); + goto free_desc; + } + } } From e515c414a80d8b7116cfe073efe2b8b902761697 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Mon, 13 Oct 2025 16:18:00 +0200 Subject: [PATCH 0061/1450] drivers: spi: siwx91x: Fix compatibility with gpdma MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because of limitation of gpdma, DMA Rx won't run if user doesn't specify destination buffer. Thus, the DMA Rx may stop before the end of the full transaction. So, wait on DMA Tx instead. Then, the SPI data won't be consumed by the DMA. We need to properly reset the fifo before to start a new transaction (it is better to ensure we start with a clean state before every transaction). Signed-off-by: Jérôme Pouiller --- drivers/spi/spi_silabs_siwx91x_gspi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi_silabs_siwx91x_gspi.c b/drivers/spi/spi_silabs_siwx91x_gspi.c index 3435854db6e0b..4b60676abb670 100644 --- a/drivers/spi/spi_silabs_siwx91x_gspi.c +++ b/drivers/spi/spi_silabs_siwx91x_gspi.c @@ -192,7 +192,7 @@ static int gspi_siwx91x_config(const struct device *dev, const struct spi_config } #ifdef CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA -static void gspi_siwx91x_dma_rx_callback(const struct device *dev, void *user_data, +static void gspi_siwx91x_dma_tx_callback(const struct device *dev, void *user_data, uint32_t channel, int status) { const struct device *spi_dev = (const struct device *)user_data; @@ -230,7 +230,7 @@ static int gspi_siwx91x_dma_config(const struct device *dev, .block_count = block_count, .head_block = channel->dma_descriptors, .dma_slot = channel->dma_slot, - .dma_callback = !is_tx ? &gspi_siwx91x_dma_rx_callback : NULL, + .dma_callback = is_tx ? &gspi_siwx91x_dma_tx_callback : NULL, .user_data = (void *)dev, }; @@ -411,7 +411,8 @@ static int gspi_siwx91x_transceive_dma(const struct device *dev, const struct sp return -EINVAL; } - /* Reset the Rx and Tx FIFO register */ + cfg->reg->GSPI_FIFO_THRLD_b.RFIFO_RESET = 1; + cfg->reg->GSPI_FIFO_THRLD_b.WFIFO_RESET = 1; cfg->reg->GSPI_FIFO_THRLD = 0; ret = gspi_siwx91x_prepare_dma_transaction(dev, padded_transaction_size); From f3e72b094f3d747b0b60d4ed5956a7af37915c40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 24 Oct 2025 12:02:17 +0200 Subject: [PATCH 0062/1450] drivers: dma: siwx91x: Fix DMA_ADDR_ADJ_NO_CHANGE w/ memory destination MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GPDMA does not support DMA_ADDR_ADJ_NO_CHANGE with a memory buffer. This feature is required fro the SPI driver. Hopefully, SPI driver is the only user of this feature. Therefore, this commit introduces a hack for SPI. When the user want to ignore the Rx data (= when he pass a NULL pointer for the Rx buffer), rather than overwriting the destination in a loop, we just disable the rx DMA. This introduce a limitation: since Rx DMA stop early, any following Rx request will start earlier than expected. Therefore, this patch breaks cases with interleaved Rx buffers. In other words, the NULL buffer must be the last one. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx91x_gpdma.c | 17 +++++++++++++++++ tests/drivers/spi/spi_loopback/src/spi.c | 5 +++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dma_silabs_siwx91x_gpdma.c b/drivers/dma/dma_silabs_siwx91x_gpdma.c index 177c80678bb3a..629377698fb70 100644 --- a/drivers/dma/dma_silabs_siwx91x_gpdma.c +++ b/drivers/dma/dma_silabs_siwx91x_gpdma.c @@ -180,6 +180,23 @@ static int siwx91x_gpdma_desc_config(struct siwx19x_gpdma_data *data, desc->chnlCtrlConfig.transSize = block->block_size; if (block->dest_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { desc->chnlCtrlConfig.dstFifoMode = 1; + /* HACK: GPDMA does not support DMA_ADDR_ADJ_NO_CHANGE with a memory buffer. + * This configuration is mainly used by SPI to ignore the received bytes. + * The hack below disable the data transfer (in fact it reduce the length to + * one byte). Fortunately, SPI only watch DMA Tx termination so the + * early termination of the DMA Rx won't hurt. + */ + if (config->channel_direction == PERIPHERAL_TO_MEMORY) { + desc->chnlCtrlConfig.transSize = 1; + if (block->next_block && + block->next_block->dest_addr_adj != DMA_ADDR_ADJ_NO_CHANGE) { + /* ... however, it is not possible to receive a real buffer + * after the hack described above + */ + LOG_ERR("Buffer interleaving is not supported"); + goto free_desc; + } + } } if (block->source_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) { desc->chnlCtrlConfig.srcFifoMode = 1; diff --git a/tests/drivers/spi/spi_loopback/src/spi.c b/tests/drivers/spi/spi_loopback/src/spi.c index 9766708a3e0c1..3f3d0553b2f91 100644 --- a/tests/drivers/spi/spi_loopback/src/spi.c +++ b/tests/drivers/spi/spi_loopback/src/spi.c @@ -472,7 +472,7 @@ ZTEST(spi_loopback, test_spi_rx_half_start) ZTEST(spi_loopback, test_spi_rx_half_end) { - if (IS_ENABLED(CONFIG_SPI_STM32_DMA)) { + if (IS_ENABLED(CONFIG_SPI_STM32_DMA) || IS_ENABLED(CONFIG_DMA_SILABS_SIWX91X_GPDMA)) { TC_PRINT("Skipped spi_rx_hald_end"); return; } @@ -494,7 +494,8 @@ ZTEST(spi_loopback, test_spi_rx_half_end) ZTEST(spi_loopback, test_spi_rx_every_4) { - if (IS_ENABLED(CONFIG_SPI_STM32_DMA) || IS_ENABLED(CONFIG_DSPI_MCUX_EDMA)) { + if (IS_ENABLED(CONFIG_SPI_STM32_DMA) || IS_ENABLED(CONFIG_DSPI_MCUX_EDMA) || + IS_ENABLED(CONFIG_DMA_SILABS_SIWX91X_GPDMA)) { TC_PRINT("Skipped spi_rx_every_4"); return; }; From f0cbba0f8ef502adeee7b784577b9994a5e9e8a6 Mon Sep 17 00:00:00 2001 From: Martin Hoff Date: Fri, 24 Oct 2025 16:28:12 +0200 Subject: [PATCH 0063/1450] dts: arm: silabs: fix siwg917 default nwp power state This patch fixes a bug where the siwg917 SoC didn't enter deep sleep even when the CONFIG_PM Kconfig option was selected, due to the default power state of the network coprocessor. Users should only need to activate the CONFIG_PM Kconfig option when they want to enable power management and be able to deep sleep by default. Signed-off-by: Martin Hoff --- dts/arm/silabs/siwg917.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index 3a65d8019e610..3f16e13bef257 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -76,7 +76,7 @@ nwp: nwp { compatible = "silabs,siwx91x-nwp"; - power-profile = "high-performance"; + power-profile = "deep-sleep-with-ram-retention"; stack-size = <10240>; interrupt-parent = <&nvic>; interrupts = <30 0>, <74 0>; From 084609a7bbb9bfaed70301a4130724a15fc494b9 Mon Sep 17 00:00:00 2001 From: Tim Pambor Date: Tue, 28 Oct 2025 17:38:19 +0100 Subject: [PATCH 0064/1450] drivers: spi: shell: fix deprecation warning Remove deprecated delay parameter from SPI DT macro. Signed-off-by: Tim Pambor --- drivers/spi/spi_shell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi_shell.c b/drivers/spi/spi_shell.c index 16585790b1ae5..a45dafcbcee7c 100644 --- a/drivers/spi/spi_shell.c +++ b/drivers/spi/spi_shell.c @@ -57,7 +57,7 @@ struct map { #define INST_SPI_SHELL_DEVICE_AS_SPI_DEV(node_id) \ { \ .name = DEVICE_DT_NAME(node_id), \ - .spec = SPI_DT_SPEC_GET(node_id, 0, 0), \ + .spec = SPI_DT_SPEC_GET(node_id, 0), \ }, #define INST_SPI_SHELL_DEVICE_AS_SPI_DEV_AS_SPI_BUS(dev) \ From 6930d71447edc83c3a815ecf589fd05f1f67f4b2 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Sat, 25 Oct 2025 11:00:16 +0800 Subject: [PATCH 0065/1450] west.yml: update hal_nxp To fix tpm building issue on imx9131: west build -p -b frdm_imx91/mimx9131 tests/drivers/counter/counter_basic_api -T drivers.counter.basic_api Signed-off-by: Jiafei Pan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 5fde5be43590c..4c8c8861312a7 100644 --- a/west.yml +++ b/west.yml @@ -210,7 +210,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 75bb1262e5bc2a701c63602734738a9c8b096ee5 + revision: cf8f1631e862528ee044850bcc70273975b90771 path: modules/hal/nxp groups: - hal From 3559dd93ea72ed865f12f538a25a257cfccce40d Mon Sep 17 00:00:00 2001 From: Mohamed Moawad Date: Thu, 23 Oct 2025 19:25:36 +0300 Subject: [PATCH 0066/1450] drivers: spi: dw: Skip version detection on aux-reg platforms The version register is not accessible through aux-reg interface, So skip it entirely on platforms with aux-reg device tree property. Signed-off-by: Mohamed Moawad --- drivers/spi/spi_dw.c | 2 ++ drivers/spi/spi_dw.h | 21 +++++++++++---------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c index bd10447e4429a..9f00905a3f028 100644 --- a/drivers/spi/spi_dw.c +++ b/drivers/spi/spi_dw.c @@ -566,11 +566,13 @@ int spi_dw_init(const struct device *dev) write_imr(dev, DW_SPI_IMR_MASK); clear_bit_ssienr(dev); +#if !DT_ANY_INST_PROP_STATUS_OKAY(aux_reg) /* SSI component version */ spi->version = read_ssi_comp_version(dev); LOG_DBG("Version: %c.%c%c%c", (spi->version >> 24) & 0xff, (spi->version >> 16) & 0xff, (spi->version >> 8) & 0xff, spi->version & 0xff); +#endif LOG_DBG("Designware SPI driver initialized on device: %p", dev); diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h index 55a2580466484..c91ddbf7996c2 100644 --- a/drivers/spi/spi_dw.h +++ b/drivers/spi/spi_dw.h @@ -20,6 +20,15 @@ extern "C" { #endif +/* Helper macros for checking property status across instances */ +#define DT_INST_NODE_PROP_NOT_OR(inst, prop) !DT_INST_PROP(inst, prop) || +#define DT_ANY_INST_NOT_PROP_STATUS_OKAY(prop) \ + (DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_PROP_NOT_OR, prop) 0) + +#define DT_INST_NODE_PROP_AND_OR(inst, prop) DT_INST_PROP(inst, prop) || +#define DT_ANY_INST_PROP_STATUS_OKAY(prop) \ + (DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_PROP_AND_OR, prop) 0) + typedef void (*spi_dw_config_t)(void); typedef uint32_t (*spi_dw_read_t)(uint8_t size, mm_reg_t addr, uint32_t off); typedef void (*spi_dw_write_t)(uint8_t size, uint32_t data, mm_reg_t addr, uint32_t off); @@ -48,22 +57,14 @@ struct spi_dw_config { struct spi_dw_data { DEVICE_MMIO_RAM; struct spi_context ctx; +#if !DT_ANY_INST_PROP_STATUS_OKAY(aux_reg) uint32_t version; /* ssi comp version */ +#endif uint8_t dfs; /* dfs in bytes: 1,2 or 4 */ uint8_t fifo_diff; /* cannot be bigger than FIFO depth */ }; /* Register operation functions */ -#define DT_INST_NODE_PROP_NOT_OR(inst, prop) \ - !DT_INST_PROP(inst, prop) || -#define DT_ANY_INST_NOT_PROP_STATUS_OKAY(prop) \ - (DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_PROP_NOT_OR, prop) 0) - -#define DT_INST_NODE_PROP_AND_OR(inst, prop) \ - DT_INST_PROP(inst, prop) || -#define DT_ANY_INST_PROP_STATUS_OKAY(prop) \ - (DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_INST_NODE_PROP_AND_OR, prop) 0) - #if DT_ANY_INST_PROP_STATUS_OKAY(aux_reg) static uint32_t aux_reg_read(uint8_t size, mm_reg_t addr, uint32_t off) { From 6edfdb99f492b1352e3d1e4c8517a0e713f6d47e Mon Sep 17 00:00:00 2001 From: Zackery Backman Date: Fri, 24 Oct 2025 12:40:20 -0600 Subject: [PATCH 0067/1450] doc: develop: manifests: external: add wolfSSL Add documentation to external module section for adding wolfSSL to Zephyr Signed-off-by: Zackery Backman --- doc/develop/manifest/external/wolfssl.rst | 66 +++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 doc/develop/manifest/external/wolfssl.rst diff --git a/doc/develop/manifest/external/wolfssl.rst b/doc/develop/manifest/external/wolfssl.rst new file mode 100644 index 0000000000000..39f3ab0386391 --- /dev/null +++ b/doc/develop/manifest/external/wolfssl.rst @@ -0,0 +1,66 @@ +.. _external_module_wolfssl: + +wolfSSL +####### + +Introduction +************ + +wolfSSL is a lightweight, portable SSL/TLS library optimized for embedded systems, RTOS environments, and resource-constrained devices. It offers a range of cryptographic functions, and secure communication protocols (up to TLS 1.3 and DTLS 1.3) along with post-quantum cryptography support. Its support for multiple build configurations makes it suitable for a wide range of applications and hardware platforms that are utilizing the Zephyr RTOS. + +wolfSSL has support for the Zephyr networking stack so applications can use the wolfSSL API to establish secure connections with other devices or services over the network. + +wolfSSL is dual licensed under GPLv3 and commercial licenses. + +GitHub Repository: `wolfSSL Repository`_ + +Usage with Zephyr +***************** + +Add wolfssl as a project to your west.yml: + +.. code-block:: yaml + + manifest: + remotes: + # + - name: wolfssl + url-base: https://github.com/wolfssl + projects: + # + - name: wolfssl + path: modules/crypto/wolfssl + revision: master + remote: wolfssl + +Update west's modules: + +.. code-block:: bash + + west update + +Now west recognizes ``wolfssl`` as a module, and will include its Kconfig and +CMakeLists.txt in the build system. + +For more regarding the usage of wolfSSL with Zephyr, please refer to the `wolfSSL Zephyr Example Usage`_. + +For application code examples in Zephyr, please refer to the `wolfSSL NXP AppCodeHub`_. + +For wolfSSL API documentation, please refer to the `wolfSSL Documentation`_. + +Reference +********* + +.. target-notes:: + +.. _wolfssl Repository: + https://github.com/wolfSSL/wolfssl + +.. _wolfSSL Zephyr Example Usage: + https://github.com/wolfSSL/wolfssl/blob/master/zephyr/README.md#build-and-run-wolfcrypt-benchmark-application + +.. _wolfSSL NXP AppCodeHub: + https://github.com/wolfSSL/nxp-appcodehub + +.. _wolfSSL Documentation: + https://www.wolfssl.com/docs/ From 184ee4462074c561abaf523165158fe3a93bcaa7 Mon Sep 17 00:00:00 2001 From: Michael Hope Date: Fri, 24 Oct 2025 19:30:36 +0200 Subject: [PATCH 0068/1450] drivers: clock_control: fix the ch32v003/006 build A recent commit added support for the CH32V30x/20x PLL multiplier. The code is protected by a `IS_ENABLED(...)` but uses a constant that doesn't exist for the CH32V00x, breaking the build. Tested by building samples/basic/blinky for the ch32v003evt and linkw. Signed-off-by: Michael Hope --- drivers/clock_control/clock_control_wch_rcc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_control_wch_rcc.c b/drivers/clock_control/clock_control_wch_rcc.c index 25562269f932a..ba6243ef6fab6 100644 --- a/drivers/clock_control/clock_control_wch_rcc.c +++ b/drivers/clock_control/clock_control_wch_rcc.c @@ -35,6 +35,7 @@ #define WCH_RCC_SRC_IS_HSI 1 #endif +#if defined(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED) #if defined(CONFIG_SOC_CH32V307) /* TODO: Entry 13 is 6.5x (fractional multiple currently unsupported without * changes to RCC config datatype) @@ -43,6 +44,7 @@ static const uint8_t pllmul_lut[] = {18, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 #else static const uint8_t pllmul_lut[] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18}; #endif +#endif struct clock_control_wch_rcc_config { RCC_TypeDef *regs; @@ -165,7 +167,7 @@ static int clock_control_wch_rcc_init(const struct device *dev) } else if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSI)) { RCC->CFGR0 &= ~RCC_PLLSRC; } - +#if defined(RCC_PLLMULL) uint8_t pllmul = 0x0; /* Default Reset Value */ for (size_t i = 0; i < ARRAY_SIZE(pllmul_lut); i++) { @@ -175,6 +177,7 @@ static int clock_control_wch_rcc_init(const struct device *dev) } RCC->CFGR0 &= ~RCC_PLLMULL; RCC->CFGR0 |= WCH_RCC_PLLMUL_VAL(pllmul); +#endif RCC->CTLR |= RCC_PLLON; while ((RCC->CTLR & RCC_PLLRDY) == 0) { } From 54ebd72ed95c88ceec335f3be68359ebc0cbc020 Mon Sep 17 00:00:00 2001 From: Thorsten Klein Date: Fri, 24 Oct 2025 17:47:52 +0200 Subject: [PATCH 0069/1450] scripts: west_commands: add pyproject.toml file added pyproject.toml config file which allows to set paths for tools like mypy or pytest. With this config file it becomes possible to directly run those tools in a local zephyr tree. Signed-off-by: Thorsten Klein --- scripts/west_commands/mypy.ini | 2 -- scripts/west_commands/pyproject.toml | 6 ++++++ 2 files changed, 6 insertions(+), 2 deletions(-) delete mode 100644 scripts/west_commands/mypy.ini create mode 100644 scripts/west_commands/pyproject.toml diff --git a/scripts/west_commands/mypy.ini b/scripts/west_commands/mypy.ini deleted file mode 100644 index 285444c485707..0000000000000 --- a/scripts/west_commands/mypy.ini +++ /dev/null @@ -1,2 +0,0 @@ -[mypy] -ignore_missing_imports=True diff --git a/scripts/west_commands/pyproject.toml b/scripts/west_commands/pyproject.toml new file mode 100644 index 0000000000000..7a51a7119cf37 --- /dev/null +++ b/scripts/west_commands/pyproject.toml @@ -0,0 +1,6 @@ +[tool.mypy] +ignore_missing_imports = true +mypy_path = "." + +[tool.pytest.ini_options] +pythonpath = ["."] From d58bc085bd1d70dccda494babbe19f5c291196f6 Mon Sep 17 00:00:00 2001 From: Thorsten Klein Date: Fri, 24 Oct 2025 21:01:53 +0200 Subject: [PATCH 0070/1450] scripts: west_commands: rework run_tests.py reworked run_tests.py script: - removed obsolete arguments from commands called by this script - avoid code duplication by using a for-loop Signed-off-by: Thorsten Klein --- scripts/west_commands/run_tests.py | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/scripts/west_commands/run_tests.py b/scripts/west_commands/run_tests.py index c4131863349de..a45e9a1c14300 100755 --- a/scripts/west_commands/run_tests.py +++ b/scripts/west_commands/run_tests.py @@ -26,15 +26,12 @@ here = os.path.abspath(os.path.dirname(__file__)) -mypy = [sys.executable, '-m', 'mypy', f'--config-file={here}/mypy.ini', - '--package', 'runners'] -pytest = [sys.executable, '-m', 'pytest'] + sys.argv[1:] +mypy = ['mypy', '--package=runners'] +pytest = ['pytest'] + sys.argv[1:] -print(f'Running mypy from {here}:\n\t' + - ' '.join(shlex.quote(s) for s in mypy), - flush=True) -subprocess.run(mypy, check=True, cwd=here) -print(f'Running pytest from {here}:\n\t' + - ' '.join(shlex.quote(s) for s in pytest), - flush=True) -subprocess.run(pytest, check=True, cwd=here) +for cmd in [mypy, pytest]: + command = [sys.executable, '-m'] + cmd + print(f"Running {cmd[0]} in cwd '{here}':\n\t" + + ' '.join(shlex.quote(s) for s in command), + flush=True) + subprocess.run(command, check=True, cwd=here) From 30e5ea8eea5b6cbca091c35a1015642356001eac Mon Sep 17 00:00:00 2001 From: WenBin Zhang Date: Sat, 18 Oct 2025 23:53:53 +0800 Subject: [PATCH 0071/1450] twister: Enhanced device-testing Command Help Collect device-testing commands into a single location to enhance readability of help information and reduce the time spent locating device-testing options. Signed-off-by: WenBin Zhang --- .../pylib/twister/twisterlib/environment.py | 117 +++++++++--------- 1 file changed, 59 insertions(+), 58 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index e1936f503d8cc..e5039ed12b56c 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -171,29 +171,31 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser: "--emulation-only", action="store_true", help="Only build and run emulation platforms") - run_group_option.add_argument( - "--device-testing", action="store_true", - help="Test on device directly. Specify the serial device to " - "use with the --device-serial option.") - - run_group_option.add_argument("--generate-hardware-map", - help="""Probe serial devices connected to this platform - and create a hardware map file to be used with - --device-testing - """) - run_group_option.add_argument( "--simulation", dest="sim_name", choices=SUPPORTED_SIMS, help="Selects which simulation to use. Must match one of the names defined in the board's " "manifest. If multiple simulator are specified in the selected board and this " "argument is not passed, then the first simulator is selected.") + run_group_option.add_argument( + "--device-testing", action="store_true", + help="Test on device directly. Specify the serial device to " + "use with the --device-serial option.") + + parser.add_argument("--pre-script", + help="""specify a pre script. This will be executed + before device handler open serial port and invoke runner. + """) device.add_argument("--device-serial", help="""Serial device for accessing the board (e.g., /dev/ttyACM0) """) + parser.add_argument( + "--device-serial-baud", action="store", default=None, + help="Serial device baud rate (default 115200)") + device.add_argument("--device-serial-pty", help="""Script for controlling pseudoterminal. Twister believes that it interacts with a terminal @@ -203,13 +205,21 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser: --device-serial-pty