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The OpenROAD Project

OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).


  1. OpenROAD users should look at this repository first for instructions on getting started

    46 7

  2. OpenROAD Public

    OpenROAD's unified application implementing an RTL-to-GDS Flow

    Verilog 407 136

  3. yosys Public

    Forked from YosysHQ/yosys

    Logic synthesis and ABC based optimization

    C++ 18 14

  4. OpenLane Public

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Verilog 437 159