{"payload":{"header_redesign_enabled":false,"results":[{"id":"281208911","archived":false,"color":"#3572A5","followers":1239,"has_funding_file":false,"hl_name":"The-OpenROAD-Project/OpenLane","hl_trunc_description":"OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…","language":"Python","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":281208911,"name":"OpenLane","owner_id":42419825,"owner_login":"The-OpenROAD-Project","updated_at":"2024-05-28T07:28:24.373Z","has_issues":true}},"sponsorable":false,"topics":["magic","asic","rtl","verilog","vlsi","foundry","yosys","klayout","caravel","netgen","system-on-chip","openroad","openram","skywater","130nm","soc-design","rtl2gds"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":88,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AThe-OpenROAD-Project%252FOpenLane%2B%2Blanguage%253APython","metadata":null,"csrf_tokens":{"/The-OpenROAD-Project/OpenLane/star":{"post":"iP6KuglXxvFtqhEbBvQNb9CmIvdoG61IbdNL5TpPCTggy4JSBBx7AXE3fMFcb0O6vKj6GrLE-831VTVQpy29tw"},"/The-OpenROAD-Project/OpenLane/unstar":{"post":"ldRwic1iaPG6DU4wDTcHjOhhhqup8m3s58yw-b-SuEZGoASpyjaE6Mj0Ej7b-6hlrcV9SYbLOQ6Bpv8x9TzyVg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"0S20BVFtPRrZHLp_M99TJX5cJLzVu8rx8w39IZpwUjnZrVBcXnY-_6jhX2kwWw_YNcoDWS8-1CWJt6ZoWMp8LA"}}},"title":"Repository search results"}