-
Notifications
You must be signed in to change notification settings - Fork 274
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Eqy check #1447
Eqy check #1447
Conversation
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
…alence check post repair_timing Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
@vvbandeira This PR cannot be merged until the CI/CD container has these repos installed as the default (sudo make install). https://github.com/YosysHQ/yosys Please do let me know if I can help in any way. Thx ! |
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
@openroadie |
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
This reverts commit a0d89b5. Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
This conflicts yosys versions and causes eqy to not work Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Just this small question. CI is in a shape where is good to merge the PR, please let me know when to merge -- I would like to do a "squash and merge" due to the number of commits.
Edit: maybe add an exclude to the 4_eqy_output
folder so as to not save in CI as it contains a lot of files which is slowing down the pipeline?
@vvbandeira this is good to merge from my point of view. But CI/CD is still failing (pr-head) as far as I can see. |
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
This reverts commit 65a21d7. Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
fd9b5b5
to
7b9261e
Compare
* Add modified verilog files for equivalence checking * Add code to write out equivalence check config file and run the equivalence check post repair_timing * Enable equivalence checks after repair_timing * Use -remove_cells to remove TAP cells * Handle subdirectories in the log dir during cts_clean * Add verilog cells for nangate45 * Add missing/used cells * Add REMOVE_CELLS_FOR_EQY * Add doc for new variables * Add new variables for skipping cells for equivalence checks+cleanup * Fixes in flip flop definitions * Enable sky130hd/gcd eqy check * Bump OR submodule * etc: enable python before pip install * etc: add pip dependencies, remove dups w/OR * ci: enable python38 * ci: EQUIVALENCE_CHECK will be enabled per design * ci: remove source env.sh from test_helper and GHA This conflicts yosys versions and causes eqy not to work * ci: exclude 4_eqy_output from save artifacts --- Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com> Co-authored-by: Vitor Bandeira <vvbandeira@precisioninno.com> Signed-off-by: habibayassin <habibayassin@aucegypt.edu>
* Add modified verilog files for equivalence checking * Add code to write out equivalence check config file and run the equivalence check post repair_timing * Enable equivalence checks after repair_timing * Use -remove_cells to remove TAP cells * Handle subdirectories in the log dir during cts_clean * Add verilog cells for nangate45 * Add missing/used cells * Add REMOVE_CELLS_FOR_EQY * Add doc for new variables * Add new variables for skipping cells for equivalence checks+cleanup * Fixes in flip flop definitions * Enable sky130hd/gcd eqy check * Bump OR submodule * etc: enable python before pip install * etc: add pip dependencies, remove dups w/OR * ci: enable python38 * ci: EQUIVALENCE_CHECK will be enabled per design * ci: remove source env.sh from test_helper and GHA This conflicts yosys versions and causes eqy not to work * ci: exclude 4_eqy_output from save artifacts --- Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com> Co-authored-by: Vitor Bandeira <vvbandeira@precisioninno.com> Signed-off-by: habibayassin <habibayassin@aucegypt.edu>
|
eqy is trying to prove that OR hasn't introduced any logic errors in the course of optimization. We did hit one such case a while ago and wanted to have some checking. |
I am trying to build and execute a fresh clone of ORFS. |
@vvbandeira please help @refaay with eqy |
* Add modified verilog files for equivalence checking * Add code to write out equivalence check config file and run the equivalence check post repair_timing * Enable equivalence checks after repair_timing * Use -remove_cells to remove TAP cells * Handle subdirectories in the log dir during cts_clean * Add verilog cells for nangate45 * Add missing/used cells * Add REMOVE_CELLS_FOR_EQY * Add doc for new variables * Add new variables for skipping cells for equivalence checks+cleanup * Fixes in flip flop definitions * Enable sky130hd/gcd eqy check * Bump OR submodule * etc: enable python before pip install * etc: add pip dependencies, remove dups w/OR * ci: enable python38 * ci: EQUIVALENCE_CHECK will be enabled per design * ci: remove source env.sh from test_helper and GHA This conflicts yosys versions and causes eqy not to work * ci: exclude 4_eqy_output from save artifacts --- Signed-off-by: Harsh Vardhan <openroad@chez-vardhan.com> Co-authored-by: Vitor Bandeira <vvbandeira@precisioninno.com> Signed-off-by: habibayassin <habibayassin@aucegypt.edu>
Adding eqy checks into ORFS with help from the eqy team on how to structure the input config file.