K. Han, A. B. Kahng and J. Li, "Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution", IEEE Trans. on CAD (2018), doi:10.1109/TCAD.2018.2889756.
Many subsequent changes for open-sourcing were made by Mateus Fogaça.
Inputs and outputs
TritonCTS requires 5 input files and produces 2 output files. Refer to OpenROAD Flow and Notes for more information.
- Library characterization files
- Verilog with gate-level netlist
- Placed DEF with netlist
- Configuration file
- Placed DEF with clock buffers
- Verilog with clock buffers
Supported features / assumptions
- 1 clock source;
TritonCTS has been validated for the following list of platforms, tools and enablements.
|Operating system||CentOS 6|
|Enablements||ST28 and TSMC16|
Below we display the clock nets for the design jpeg_encoder implemented in TSMC65 with 24K instances, followed by TritonCTS routing topology.
|TritonCTS generated clock nets for jpeg_encoder|
|TritonCTS clock tree topology for jpeg_encoder|