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Source codes and calibration scripts for clock tree synthesis
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mpfogaca Merge pull request #22 from yrrapt/master
Slight Modifications Need to Generate Characterisation Files
Latest commit 291ded8 Sep 3, 2019
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third_party Update CtsHelper Aug 15, 2019
.dockerignore add Dockerfile to integrate with OpenROAD unified build Aug 27, 2019
.gitmodules Adding source code of lefdef2cts as a submodule Jul 15, 2019
Dockerfile add Dockerfile to integrate with OpenROAD unified build Aug 27, 2019
LICENSE Initial commit Nov 27, 2018
runTritonCTS.tcl Added percentile param Aug 15, 2019


Original work

K. Han, A. B. Kahng and J. Li, "Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution", IEEE Trans. on CAD (2018), doi:10.1109/TCAD.2018.2889756.

Many subsequent changes for open-sourcing were made by Mateus Fogaça.

Inputs and outputs

TritonCTS requires 5 input files and produces 2 output files. Refer to OpenROAD Flow and Notes for more information.



  • Placed DEF with clock buffers
  • Verilog with clock buffers

Supported features / assumptions

  • 1 clock source;


TritonCTS has been validated for the following list of platforms, tools and enablements.

Feature Support
Operating system CentOS 6
Compiler GCC 4.4.7
Enablements ST28 and TSMC16
TCL Version 8.4.20
Python Version 2.7.12
Lemon Version 1.3.1



Below we display the clock nets for the design jpeg_encoder implemented in TSMC65 with 24K instances, followed by TritonCTS routing topology.

TritonCTS generated clock nets for jpeg_encoder
TritonCTS clock tree topology for jpeg_encoder
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