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Source codes and calibration scripts for clock tree synthesis
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README.md

TritonCTS

Original work

K. Han, A. B. Kahng and J. Li, "Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution", IEEE Trans. on CAD (2018), doi:10.1109/TCAD.2018.2889756.

Many subsequent changes for open-sourcing were made by Mateus Fogaça.

Inputs and outputs

TritonCTS requires 5 input files and produces 2 output files. Refer to OpenROAD Flow and Notes for more information.

Inputs:

Outputs:

  • Placed DEF with clock buffers
  • Verilog with clock buffers

Supported features / assumptions

  • 1 clock source;

Validation

TritonCTS has been validated for the following list of platforms, tools and enablements.

Feature Support
Operating system CentOS 6
Compiler GCC 4.4.7
Enablements ST28 and TSMC16
TCL Version 8.4.20
Python Version 2.7.12
Lemon Version 1.3.1

Tutorials

Example

Below we display the clock nets for the design jpeg_encoder implemented in TSMC65 with 24K instances, followed by TritonCTS routing topology.

TritonCTS generated clock nets for jpeg_encoder
TritonCTS clock tree topology for jpeg_encoder
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