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SRAM (512kB), 1.5MHz, 16kiB insmem/rom, bugfix on ori/andi/xori, etc.

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Themaister committed Apr 15, 2011
1 parent a6f829e commit 8769951f2c136d41f4b975885eb936b7fabac41f
Showing with 295 additions and 152 deletions.
  1. +42 −13 clock_1hz.vhd
  2. +10 −10 grom.vhd
  3. +10 −10 insmem_rom.vhd
  4. +38 −6 mipsmem.vhd
  5. +32 −0 mipsparts.vhd
  6. +11 −9 mipssingle.vhd
  7. +107 −73 sram.vhd
  8. +45 −31 top.vhd
View
@@ -8,32 +8,61 @@ entity clock_1hz is
reset : in std_logic;
insmem_clk : out std_logic_vector(2 downto 0);
- ram_clk : out std_logic_vector(2 downto 0);
+ ram_clk : out std_logic_vector(5 downto 0);
cpu_clk : out std_logic
);
end;
architecture synth of clock_1hz is
signal count : integer := 0;
- signal clk_cnt : std_logic_vector(6 downto 0) := "0000001";
+ signal clk_cnt : std_logic_vector(19 downto 0) := x"00000";
begin
process (clk, reset) begin
if (reset = '1') then
count <= 0;
- clk_cnt <= "0000001";
+ clk_cnt <= x"80000";
elsif rising_edge(clk) then
- if (count = 8) then
- clk_cnt <= clk_cnt(5 downto 0) & clk_cnt(6); -- rotate the clk bits
- count <= 0;
- else
- count <= count + 1;
-
- end if;
+ case count is
+ -- instruction mem clk
+ when 1 => clk_cnt <= x"00001";
+ when 2 => clk_cnt <= x"00002";
+ when 3 => clk_cnt <= x"00004";
+ when 4 => clk_cnt <= x"00008";
+ when 5 => clk_cnt <= x"00010";
+ when 6 => clk_cnt <= x"00020";
+
+ -- SRAM clock - Stall a bit so the CPU has time to figure out what to load from RAM.
+
+ when 10 => clk_cnt <= x"00040";
+ when 11 => clk_cnt <= x"00080";
+ when 12 => clk_cnt <= x"00100";
+ when 13 => clk_cnt <= x"00200";
+ when 14 => clk_cnt <= x"00400";
+ when 15 => clk_cnt <= x"00800";
+ when 16 => clk_cnt <= x"01000";
+ when 17 => clk_cnt <= x"02000";
+ when 18 => clk_cnt <= x"04000";
+ when 19 => clk_cnt <= x"08000";
+ when 20 => clk_cnt <= x"10000";
+ when 21 => clk_cnt <= x"20000";
+
+ -- CPU clock - Stall a bit more...
+ when 31 => clk_cnt <= x"40000";
+ when 32 => clk_cnt <= x"80000";
+
+ when others => clk_cnt <= x"00000";
+ end case;
+
+ if count = 33 then -- Freq ~ 1.5MHz
+ count <= 0;
+ else
+ count <= count + 1;
+ end if;
end if;
end process;
- insmem_clk <= clk_cnt(2 downto 0);
- ram_clk <= clk_cnt(5 downto 3);
- cpu_clk <= clk_cnt(6);
+ insmem_clk <= clk_cnt(4) & clk_cnt(2) & clk_cnt(0);
+ ram_clk <= clk_cnt(16) & clk_cnt(14) & clk_cnt(12) & clk_cnt(10) & clk_cnt(8) & clk_cnt(6);
+ cpu_clk <= clk_cnt(18);
end;
View
@@ -42,7 +42,7 @@ USE altera_mf.all;
ENTITY grom IS
PORT
(
- address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+ address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
@@ -73,7 +73,7 @@ ARCHITECTURE SYN OF grom IS
);
PORT (
clock0 : IN STD_LOGIC ;
- address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+ address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
@@ -89,11 +89,11 @@ BEGIN
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1338",
lpm_type => "altsyncram",
- numwords_a => 2048,
+ numwords_a => 4096,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
- widthad_a => 11,
+ widthad_a => 12,
width_a => 32,
width_byteena_a => 1
)
@@ -128,14 +128,14 @@ END SYN;
-- Retrieval info: PRIVATE: JTAG_ID STRING "1338"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "test.global.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
@@ -144,17 +144,17 @@ END SYN;
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1338"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
+-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
--- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
View
@@ -42,7 +42,7 @@ USE altera_mf.all;
ENTITY insmem_rom IS
PORT
(
- address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+ address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
@@ -73,7 +73,7 @@ ARCHITECTURE SYN OF insmem_rom IS
);
PORT (
clock0 : IN STD_LOGIC ;
- address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+ address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
@@ -89,11 +89,11 @@ BEGIN
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1337",
lpm_type => "altsyncram",
- numwords_a => 2048,
+ numwords_a => 4096,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
- widthad_a => 11,
+ widthad_a => 12,
width_a => 32,
width_byteena_a => 1
)
@@ -128,14 +128,14 @@ END SYN;
-- Retrieval info: PRIVATE: JTAG_ID STRING "1337"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "test.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
@@ -144,17 +144,17 @@ END SYN;
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1337"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
+-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
--- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
View
@@ -15,15 +15,24 @@ use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dmem is -- data memory
- port(clk : in std_logic_vector(2 downto 0); -- 3-stage clock for eventual SRAM.
+ port(clk : in std_logic_vector(5 downto 0); -- 6-stage clock for eventual SRAM.
+ reset : in std_logic;
we: in std_logic;
wsize: in std_logic_vector(1 downto 0); -- sb, sh
a, wd: in std_logic_vector(31 downto 0);
rd: out std_logic_vector(31 downto 0);
switch : in std_logic_vector(15 downto 0);
led: out std_logic_vector(15 downto 0);
ledg : out std_logic_vector(7 downto 0);
- hex : out std_logic_vector(31 downto 0));
+ hex : out std_logic_vector(31 downto 0);
+
+ sram_addr : out std_logic_vector(17 downto 0);
+ sram_dq : inout std_logic_vector(15 downto 0);
+ sram_we_n : out std_logic;
+ sram_oe_n : out std_logic;
+ sram_ub_n : out std_logic;
+ sram_lb_n : out std_logic;
+ sram_ce_n : out std_logic);
end;
-- This stuff is memory mapped.
@@ -34,7 +43,7 @@ end;
architecture behave of dmem is
- COMPONENT altera_ram IS
+ COMPONENT altera_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
@@ -47,10 +56,31 @@ architecture behave of dmem is
);
END COMPONENT;
+ component sram_de2 is
+ port (
+ clk : in std_logic_vector(5 downto 0); -- 6-staged clock
+ reset : in std_logic;
+ a : in std_logic_vector(18 downto 0); -- 512kB RAM
+ byteen : in std_logic_vector(3 downto 0); -- sb/sh
+ wd : in std_logic_vector(31 downto 0); -- Write data
+ we : in std_logic;
+
+ rd : out std_logic_vector(31 downto 0);
+
+ sram_addr : out std_logic_vector(17 downto 0);
+ sram_dq : inout std_logic_vector(15 downto 0);
+ sram_we_n : out std_logic;
+ sram_oe_n : out std_logic;
+ sram_ub_n : out std_logic;
+ sram_lb_n : out std_logic;
+ sram_ce_n : out std_logic
+ );
+ end component;
+
COMPONENT grom IS
PORT
(
- address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+ address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
@@ -99,8 +129,10 @@ begin
end if;
end process;
- altera_ram1 : altera_ram port map(a(12 downto 2), byteena, wd_map, clk(0), clk(1), we_map, rd_ram);
- grom_1 : grom port map(a(12 downto 2), clk(0) or clk(2), rd_grom);
+ --altera_ram1 : altera_ram port map(a(12 downto 2), byteena, wd_map, clk(0), clk(1), we_map, rd_ram);
+ sram_de2_1 : sram_de2 port map(clk, reset, a(18 downto 0), byteena, wd_map, we_map, rd_ram,
+ sram_addr, sram_dq, sram_we_n, sram_oe_n, sram_ub_n, sram_lb_n, sram_ce_n);
+ grom_1 : grom port map(a(13 downto 2), clk(0) or clk(2), rd_grom);
-- A ROM that holds our global and static data.
-- This will have to be transferred to regular RAM. Had to do this since DE2 cannot handle
-- reprogrammable RAM apparently :/
View
@@ -238,4 +238,36 @@ begin
end;
+library altera;
+use altera.altera_primitives_components.all;
+library ieee;
+use ieee.std_logic_1164.all;
+entity tristate16 is
+ port (
+ input : in std_logic_vector(15 downto 0);
+ oe : in std_logic;
+ output : out std_logic_vector(15 downto 0));
+end;
+
+architecture synth of tristate16 is -- Gief for-loop plx :v
+begin
+ tribuf0 : TRI port map (input(0), oe, output(0));
+ tribuf1 : TRI port map (input(1), oe, output(1));
+ tribuf2 : TRI port map (input(2), oe, output(2));
+ tribuf3 : TRI port map (input(3), oe, output(3));
+ tribuf4 : TRI port map (input(4), oe, output(4));
+ tribuf5 : TRI port map (input(5), oe, output(5));
+ tribuf6 : TRI port map (input(6), oe, output(6));
+ tribuf7 : TRI port map (input(7), oe, output(7));
+ tribuf8 : TRI port map (input(8), oe, output(8));
+ tribuf9 : TRI port map (input(9), oe, output(9));
+ tribuf10 : TRI port map (input(10), oe, output(10));
+ tribuf11 : TRI port map (input(11), oe, output(11));
+ tribuf12 : TRI port map (input(12), oe, output(12));
+ tribuf13 : TRI port map (input(13), oe, output(13));
+ tribuf14 : TRI port map (input(14), oe, output(14));
+ tribuf15 : TRI port map (input(15), oe, output(15));
+end;
+
+
View
@@ -161,7 +161,9 @@ begin
(bne and (not zero)) or
(bgtz and (not ltez)) or
(bltz and ltez and (not zero)) or
- (bgez and (zero or (not ltez))); --blez
+ (bgez and (zero or (not ltez))); --blez
+
+ alu_unsigned <= alu_is_unsigned;
end;
library ieee; use ieee.std_logic_1164.all;
@@ -213,9 +215,9 @@ begin
when "000011" => controls <= "00000000110000001000010"; --jal
when "100001" => controls <= "00010000100010010000001"; --lh
when "100101" => controls <= "00000000100010010000001"; --lhu
- when "001100" => controls <= "00000000100010000100000"; --andi
- when "001110" => controls <= "00000000100010000111000"; --xori
- when "001101" => controls <= "00000000100010000101000"; --ori
+ when "001100" => controls <= "10000000100010000100000"; --andi
+ when "001110" => controls <= "10000000100010000111000"; --xori
+ when "001101" => controls <= "10000000100010000101000"; --ori
when others => controls <= "-----------------------"; -- illegal op
end case;
end process;
@@ -263,10 +265,10 @@ begin
when "100001" => l_alucontrol <= "10000010"; -- addu
when "100010" => l_alucontrol <= "00001010"; -- sub
when "100011" => l_alucontrol <= "10001010"; -- subu
- when "100100" => l_alucontrol <= "00000000"; -- and
- when "100101" => l_alucontrol <= "00000001"; -- or
- when "100110" => l_alucontrol <= "00001001"; -- xor
- when "100111" => l_alucontrol <= "00001111"; -- nor
+ when "100100" => l_alucontrol <= "10000000"; -- and
+ when "100101" => l_alucontrol <= "10000001"; -- or
+ when "100110" => l_alucontrol <= "10001001"; -- xor
+ when "100111" => l_alucontrol <= "10001111"; -- nor
when "101010" => l_alucontrol <= "00001011"; -- slt
when "101011" => l_alucontrol <= "10001011"; -- sltu
-- shifting
@@ -470,7 +472,7 @@ begin
resmux: mux2 generic map(32) port map(aluresult, memdata, --lh/lb
memtoreg, result);
- se: signext port map(instr(15 downto 0), signimm);
+ se: signext16 port map(instr(15 downto 0), not alu_unsigned, signimm);
ue: upimm port map(instr(15 downto 0), upperimm); --lui
-- alu logic
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