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Tighten timings slightly.

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1 parent c5c5f6f commit a6f829ea6f0210f9dff8d66be618f8eb71e13c3e @Themaister committed Mar 31, 2011
Showing with 1 addition and 1 deletion.
  1. +1 −1 clock_1hz.vhd
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@@ -24,7 +24,7 @@ begin
count <= 0;
clk_cnt <= "0000001";
elsif rising_edge(clk) then
- if (count = 10) then
+ if (count = 8) then
clk_cnt <= clk_cnt(5 downto 0) & clk_cnt(6); -- rotate the clk bits
count <= 0;
else

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