Tighten timings slightly.

Themaister · Mar 31, 2011 · a6f829e · a6f829e
1 parent c5c5f6f
commit a6f829e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/clock_1hz.vhd b/clock_1hz.vhd
@@ -24,7 +24,7 @@ begin
 		  count <= 0;
 		  clk_cnt <= "0000001";
       elsif rising_edge(clk) then 
-         if (count = 10) then
+         if (count = 8) then
             clk_cnt <= clk_cnt(5 downto 0) & clk_cnt(6); -- rotate the clk bits
             count <= 0;
          else