From 98dacaf698ce62c7a99d3e1f49250bddc451d356 Mon Sep 17 00:00:00 2001 From: tonyho Date: Fri, 29 Sep 2023 20:30:36 +0800 Subject: [PATCH] roll back axi_ctrl_logic.sv to get the error log --- .../fsic/user_proj_example/axi_ctrl_logic.sv | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/custom_design/fsic/user_proj_example/axi_ctrl_logic.sv b/custom_design/fsic/user_proj_example/axi_ctrl_logic.sv index 90494f1..4150db9 100755 --- a/custom_design/fsic/user_proj_example/axi_ctrl_logic.sv +++ b/custom_design/fsic/user_proj_example/axi_ctrl_logic.sv @@ -287,13 +287,7 @@ module axi_ctrl_logic( logic [9:0]aa_index; // for index of aa_regs logic [9:0]mb_index; // for index of mb_regs - //assign next_trans = (next_ss) ? TRANS_SS : TRANS_LS; - /* - if (next_ss) - next_trans = TRANS_SS; - else - next_trans = TRANS_LS; - */ + assign next_trans = (next_ss) ? TRANS_SS : TRANS_LS; // compute control signals according to source (LS / SS) and address range // note this is combinational, so the signals can only exist when state is AXI_DECIDE_DEST, @@ -320,10 +314,6 @@ module axi_ctrl_logic( //mb_index = 10'b0; //next_trans = (next_ss) ? TRANS_SS : TRANS_LS; - if (next_ss) - next_trans = TRANS_SS; - else - next_trans = TRANS_LS; if(axi_state == AXI_DECIDE_DEST)begin case(next_trans) @@ -787,4 +777,4 @@ module axi_ctrl_logic( end end -endmodule +endmodule \ No newline at end of file