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Endstop: overhauled the design to use a TCST1103 optical interrupter.

The design is a bit a compromise. As we want the LED to light up
only with an interrupted switch, there is a balance between
sending voltage to the signal line and sending current to the LED.
R3 has most influence in this balance. Bigger values give more current
to the signal, lower values more current to the LED.

The current balance gives 4 Volts to the signal and lets the LED
light up to about 80%.

Another design solution would be to connect the LED to Vcc instead of
GND, giving both, full voltage to the signal and full current to the LED.
However, the signal is inverted then, lighting the LED all the time.
Adding a transistor, too, would get the LED lighting right, but also
make the circuit more complex.
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1 parent 4ec52b5 commit 86ec84017becae77c4932535c696a8a268a8cefe @Traumflug committed Apr 6, 2011
Showing with 124 additions and 146 deletions.
  1. +65 −93 OptoEndstop.pcb
  2. +59 −53 OptoEndstop.sch
View
@@ -1,5 +1,5 @@
# release: pcb 20091103
-# date: Thu Mar 10 10:01:12 2011
+# date: Thu Apr 7 00:32:29 2011
# user: mah (Markus Hitter,,,)
# host: piccard
@@ -797,6 +797,8 @@ Symbol('~' 12)
SymbolLine(15 35 20 35 8)
SymbolLine(20 35 25 30 8)
)
+Via[132250 162500 15000 16000 0 12600 "" ""]
+Via[207750 162500 15000 16000 0 12600 "" ""]
Element["" "100-3-1" "CONN1" "unknown" 207500 141500 -12500 -4000 1 78 ""]
(
@@ -811,7 +813,7 @@ Element["" "100-3-1" "CONN1" "unknown" 207500 141500 -12500 -4000 1 78 ""]
)
-Element["" "ACY300_1" "R2" "220" 160000 142500 -5000 -3000 0 100 ""]
+Element["" "ACY300_1" "R2" "1K" 172500 132500 -5000 -3000 0 100 ""]
(
Pin[-15000 0 6000 2000 6500 3000 "1" "1" "edge2"]
Pin[15000 0 6000 2000 6500 3000 "2" "2" "edge2"]
@@ -824,55 +826,46 @@ Element["" "ACY300_1" "R2" "220" 160000 142500 -5000 -3000 0 100 ""]
)
-Element["" "H21L-1" "U1" "unknown" 170000 162500 -2500 5000 0 100 ""]
-(
- Pin[-14175 -5000 5500 2000 6000 3000 "Anode" "1" "edge2"]
- Pin[-14175 5000 5500 2000 6000 3000 "Cathode" "2" "edge2"]
- Pin[14175 5000 5000 2000 5500 3000 "Vcc" "3" "edge2"]
- Pin[19175 0 5000 2000 5500 3000 "Vout" "4" "edge2"]
- Pin[14175 -5000 5000 2000 5500 3000 "GND" "5" "edge2"]
- Pin[-37750 0 15000 16000 0 12600 "nc" "0" "edge2"]
- Pin[37750 0 15000 16000 0 12600 "nc" "0" "edge2"]
- ElementLine [23600 -12450 23600 12450 500]
- ElementLine [-23600 -12450 -23600 12450 500]
- ElementLine [50000 -8450 50000 8450 1000]
- ElementLine [-50000 -8450 -50000 8450 1000]
- ElementLine [-46000 12450 46000 12450 1000]
- ElementLine [-46000 -12450 46000 -12450 1000]
- ElementArc [46000 8450 4000 4000 90 90 1000]
- ElementArc [-46000 8450 4000 4000 0 90 1000]
- ElementArc [46000 -8450 4000 4000 180 90 1000]
- ElementArc [-46000 -8450 4000 4000 270 90 1000]
-
- )
-
-Element["" "ACY300_1" "R3" "1K" 160000 122500 -5000 -3000 0 100 ""]
+Element["" "ACY300_1" "R3" "2K2" 165000 122500 -5000 -3000 0 100 ""]
(
- Pin[15000 0 6000 2000 6500 3000 "1" "1" "edge2"]
- Pin[-15000 0 6000 2000 6500 3000 "2" "2" "edge2"]
- ElementLine [7500 0 15000 0 1000]
+ Pin[-15000 0 6000 2000 6500 3000 "1" "1" "edge2"]
+ Pin[15000 0 6000 2000 6500 3000 "2" "2" "edge2"]
ElementLine [-15000 0 -7500 0 1000]
- ElementLine [7500 -4000 7500 4000 1000]
+ ElementLine [7500 0 15000 0 1000]
ElementLine [-7500 -4000 -7500 4000 1000]
- ElementLine [-7500 4000 7500 4000 1000]
+ ElementLine [7500 -4000 7500 4000 1000]
ElementLine [-7500 -4000 7500 -4000 1000]
+ ElementLine [-7500 4000 7500 4000 1000]
)
-Element["" "ACY300_1" "R1" "10K" 172500 132500 -5000 -3000 0 100 ""]
+Element["" "TCST_11-1" "U1" "unknown" 169960 162500 -5000 5000 0 100 ""]
+(
+ Pin[-14960 -5000 6000 2000 6500 3000 "+" "1" "edge2"]
+ Pin[-14960 5000 6000 2000 6500 3000 "E" "2" "edge2"]
+ Pin[14960 5000 6000 2000 6500 3000 "+" "3" "edge2"]
+ Pin[14960 -5000 6000 2000 6500 3000 "D" "4" "edge2"]
+ ElementLine [23600 -12450 23600 12450 1000]
+ ElementLine [-23600 -12450 -23600 12450 1000]
+ ElementLine [-23600 12450 23600 12450 1000]
+ ElementLine [-23600 -12450 23600 -12450 1000]
+
+ )
+
+Element["" "ACY300_1" "R1" "180" 165000 142500 -5000 -3000 0 100 ""]
(
- Pin[15000 0 6000 2000 6500 3000 "1" "1" "edge2"]
- Pin[-15000 0 6000 2000 6500 3000 "2" "2" "edge2"]
- ElementLine [7500 0 15000 0 1000]
+ Pin[-15000 0 6000 2000 6500 3000 "1" "1" "edge2"]
+ Pin[15000 0 6000 2000 6500 3000 "2" "2" "edge2"]
ElementLine [-15000 0 -7500 0 1000]
- ElementLine [7500 -4000 7500 4000 1000]
+ ElementLine [7500 0 15000 0 1000]
ElementLine [-7500 -4000 -7500 4000 1000]
- ElementLine [-7500 4000 7500 4000 1000]
+ ElementLine [7500 -4000 7500 4000 1000]
ElementLine [-7500 -4000 7500 -4000 1000]
+ ElementLine [-7500 4000 7500 4000 1000]
)
-Element["" "LED3_1" "LED1" "unknown" 135000 132500 -5000 8000 0 100 ""]
+Element["" "LED3_1" "LED1" "unknown" 135000 127500 -5000 8000 0 100 ""]
(
Pin[0 5000 6500 3000 7100 3000 "A" "1" ""]
Pin[0 -5000 6500 3000 7100 3000 "K" "2" ""]
@@ -889,52 +882,32 @@ Layer(1 "component")
)
Layer(2 "solder")
(
- Line[165000 115000 187500 115000 2000 3200 "clearline"]
- Line[184175 167500 180000 167500 2000 3200 "clearline"]
- Line[206500 142500 207500 141500 2000 3200 "clearline"]
- Line[192500 150000 187500 145000 2000 3200 "clearline"]
- Line[187500 132500 187500 145000 2000 3200 "clearline"]
- Line[187500 170000 195000 170000 2000 3200 "clearline"]
- Line[145000 142500 145000 146675 2000 3200 "clearline"]
- Line[132500 115000 125000 122500 2000 3200 "clearline"]
- Line[155825 167500 152500 167500 2000 3200 "clearline"]
- Line[207500 141500 206000 141500 2000 3200 "clearline"]
- Line[140000 122500 135000 127500 2000 3200 "clearline"]
- Line[175000 162500 175000 142500 2000 3200 "clearline"]
- Line[177500 122500 187500 132500 2000 3200 "clearline"]
- Line[145000 146675 155825 157500 2000 3200 "clearline"]
- Line[182500 140000 175000 132500 2000 3200 "clearline"]
- Line[145000 122500 140000 122500 2000 3200 "clearline"]
- Line[175000 142500 167500 142500 2000 3200 "clearline"]
- Line[180000 167500 175000 162500 2000 3200 "clearline"]
- Line[212500 150000 217500 145000 2000 3200 "clearline"]
- Line[182500 155000 182500 145000 2000 3200 "clearline"]
- Line[195000 170000 197500 167500 2000 3200 "clearline"]
- Line[184175 157500 182500 155000 2000 3200 "clearline"]
- Line[182500 145000 182500 140000 2000 3200 "clearline"]
- Line[192500 150000 192500 160000 2000 3200 "clearline"]
- Line[170000 132500 152500 115000 2000 3200 "clearline"]
- Line[135000 137500 137500 135000 2000 3200 "clearline"]
- Line[187500 142500 206500 142500 2000 3200 "clearline"]
- Line[197500 167500 197500 152500 2000 3200 "clearline"]
- Line[137500 135000 155000 135000 2000 3200 "clearline"]
- Line[184175 167500 187500 170000 2000 3200 "clearline"]
- Line[125000 122500 125000 140000 2000 3200 "clearline"]
- Line[167500 142500 157500 132500 2000 3200 "clearline"]
- Line[152500 167500 125000 140000 2000 3200 "clearline"]
- Line[175000 122500 177500 122500 2000 3200 "clearline"]
- Line[155000 135000 157500 132500 2000 3200 "clearline"]
- Line[132500 115000 165000 115000 2000 3200 "clearline"]
- Line[207500 131500 204000 131500 2000 3200 "clearline"]
- Line[204000 131500 187500 115000 2000 3200 "clearline"]
- Line[207500 121500 214000 121500 2000 3200 "clearline"]
- Line[217500 145000 217500 125000 2000 3200 "clearline"]
- Line[214000 121500 217500 125000 2000 3200 "clearline"]
- Line[197500 152500 200000 150000 2000 3200 "clearline"]
- Line[200000 150000 212500 150000 2000 3200 "clearline"]
- Line[189175 162500 190000 162500 2000 3200 "clearline"]
- Line[190000 162500 192500 160000 2000 3200 "clearline"]
- Line[175000 132500 170000 132500 2000 3200 "clearline"]
+ Line[150000 122500 135000 122500 2000 3200 "clearline"]
+ Line[155000 167500 160000 167500 2000 3200 "clearline"]
+ Line[150000 152500 155000 157500 2000 3200 "clearline"]
+ Line[187500 135000 180000 142500 2000 3200 "clearline"]
+ Line[160000 167500 170000 157500 2000 3200 "clearline"]
+ Line[211000 141500 215000 137500 2000 3200 "clearline"]
+ Line[184920 157580 170000 157500 2000 3200 "clearline"]
+ Line[187500 132500 187500 135000 2000 3200 "clearline"]
+ Line[157500 125000 167500 115000 2000 3200 "clearline"]
+ Line[207500 144920 184920 167500 2000 3200 "clearline"]
+ Line[157500 132500 135000 132500 2000 3200 "clearline"]
+ Line[185000 157420 184920 157500 2000 3200 "clearline"]
+ Line[207500 141500 207500 144920 2000 3200 "clearline"]
+ Line[180000 122500 170000 132500 2000 3200 "clearline"]
+ Line[198500 121500 187500 132500 2000 3200 "clearline"]
+ Line[206000 131500 185000 152500 2000 3200 "clearline"]
+ Line[207500 131500 206000 131500 2000 3200 "clearline"]
+ Line[212500 115000 167500 115000 2000 3200 "clearline"]
+ Line[215000 137500 215000 117500 2000 3200 "clearline"]
+ Line[215000 117500 212500 115000 2000 3200 "clearline"]
+ Line[207500 121500 198500 121500 2000 3200 "clearline"]
+ Line[207500 141500 211000 141500 2000 3200 "clearline"]
+ Line[150000 142500 150000 152500 2000 3200 "clearline"]
+ Line[157500 132500 157500 125000 2000 3200 "clearline"]
+ Line[185000 152500 185000 157420 2000 3200 "clearline"]
+ Line[170000 157500 170000 132500 2000 3200 "clearline"]
)
Layer(3 "outline")
(
@@ -949,41 +922,40 @@ Layer(4 "silk")
Layer(5 "silk")
(
Text[213000 128000 0 121 "GND" ""]
- Text[123000 111000 0 121 "Gen7 Opto Endstop" ""]
- Text[213500 138000 0 121 "Signal" ""]
Text[213500 118000 0 121 "Vcc" ""]
+ Text[213500 138000 0 121 "Signal" ""]
+ Text[123000 111000 0 121 "Gen7 Opto Endstop" ""]
)
NetList()
(
Net("GND" "(unknown)")
(
Connect("CONN1-2")
+ Connect("R3-2")
Connect("U1-2")
- Connect("U1-5")
+ Connect("U1-4")
)
Net("unnamed_net1" "(unknown)")
(
+ Connect("CONN1-1")
+ Connect("LED1-1")
Connect("R2-1")
- Connect("U1-1")
+ Connect("U1-3")
)
Net("unnamed_net2" "(unknown)")
(
- Connect("CONN1-1")
Connect("R1-1")
- Connect("R3-1")
- Connect("U1-4")
+ Connect("U1-1")
)
Net("unnamed_net3" "(unknown)")
(
Connect("LED1-2")
- Connect("R3-2")
+ Connect("R3-1")
)
Net("Vcc" "(unknown)")
(
Connect("CONN1-3")
- Connect("LED1-1")
Connect("R1-2")
Connect("R2-2")
- Connect("U1-3")
)
)
View
@@ -1,76 +1,82 @@
v 20100214 2
-C 40700 45700 1 0 0 H21LOB-1.sym
+C 43800 47000 1 0 0 resistor-2.sym
{
-T 42200 46050 5 10 1 1 0 5 1
-device=H21LOB
-T 42200 48150 5 10 1 1 0 3 1
-refdes=U1
-T 42200 48300 5 10 0 0 0 3 1
-footprint=H21L-1
-}
-C 45300 48100 1 90 0 resistor-2.sym
-{
-T 45000 48300 5 10 1 1 90 0 1
-refdes=R3
-T 45300 48400 5 10 1 1 90 0 1
+T 44000 47200 5 10 1 1 0 0 1
+refdes=R2
+T 44100 47000 5 10 1 1 0 0 1
value=1K
-T 45300 48100 5 10 0 0 0 0 1
-footprint=ACY300_1
-}
-C 43800 45900 1 0 0 resistor-2.sym
-{
-T 44000 46100 5 10 1 1 0 0 1
-refdes=R1
-T 44000 45900 5 10 1 1 0 0 1
-value=10K
-T 43800 45900 5 10 0 0 0 0 1
+T 43800 47000 5 10 0 0 0 0 1
footprint=ACY300_1
}
C 43800 47800 1 0 0 resistor-2.sym
{
-T 44000 48100 5 10 1 1 0 0 1
-refdes=R2
+T 44000 48000 5 10 1 1 0 0 1
+refdes=R1
T 44100 47800 5 10 1 1 0 0 1
-value=220
+value=180
T 43800 47800 5 10 0 0 0 0 1
footprint=ACY300_1
}
-C 43200 45700 1 0 0 gnd-1.sym
-C 45600 50400 1 0 0 vcc-1.sym
-N 43000 47100 45800 47100 4
-N 43000 46700 45200 46700 4
-N 43000 46300 46000 46300 4
+C 44900 48300 1 0 0 vcc-1.sym
+N 43000 47100 43800 47100 4
+N 43000 46700 43200 46700 4
N 43000 47900 43800 47900 4
-N 43300 46000 43300 46300 4
-N 43800 46000 43700 46000 4
-N 43700 46000 43700 46700 4
-N 44700 46000 46000 46000 4
-N 43000 47500 43300 47500 4
-N 43300 47500 43300 46300 4
-N 45200 49000 45200 49200 4
-N 45200 50100 45200 50200 4
-N 45200 50200 45800 50200 4
-N 45800 46000 45800 50400 4
-N 44700 47900 45800 47900 4
-N 45200 46600 45200 48100 4
-T 43500 44700 9 10 1 0 0 0 3
+N 44700 47100 45100 47100 4
+N 43000 47500 43200 47500 4
+N 43600 46000 43600 47100 4
+N 45100 46400 45100 48300 4
+N 44700 47900 45100 47900 4
+T 43500 44400 9 10 1 0 0 0 2
RepRap Generation 7 Electronics Opto Endstop
http://reprap.org/wiki/Generation_7_Electronics
-Derivative of Opto Endstop v2.1
-C 47700 45800 1 0 1 connector3-1.sym
+C 47800 46200 1 0 1 connector3-1.sym
{
-T 47700 46900 5 10 1 1 0 6 1
+T 47800 47300 5 10 1 1 0 6 1
refdes=CONN1
-T 47200 45600 5 10 1 1 0 0 1
+T 47300 46000 5 10 1 1 0 0 1
device=22-23-2031
-T 47700 45800 5 10 0 0 0 0 1
+T 47800 46200 5 10 0 0 0 0 1
footprint=100-3-1
}
-N 45200 46600 46000 46600 4
-C 45000 50100 1 270 0 led-1.sym
+C 43800 45800 1 0 0 led-1.sym
{
-T 45000 49800 5 10 1 1 90 0 1
+T 44100 45800 5 10 1 1 180 0 1
refdes=LED1
-T 45000 50100 5 10 0 1 0 0 1
+T 43800 45800 5 10 0 1 90 0 1
footprint=LED3_1
}
+C 40700 46300 1 0 0 TCST.sym
+{
+T 42200 46450 5 10 1 1 0 5 1
+devicename=TCST 1103
+T 42200 48150 5 10 1 1 0 3 1
+refdes=U1
+T 42200 48300 5 10 0 0 0 3 1
+footprint=TCST_11-1
+}
+N 45100 46400 46100 46400 4
+C 43100 46400 1 0 0 gnd-1.sym
+N 43600 46700 45500 46700 4
+N 46100 47000 45500 47000 4
+N 45500 47000 45500 46700 4
+C 44700 45900 1 0 0 resistor-2.sym
+{
+T 44900 46100 5 10 1 1 0 0 1
+refdes=R3
+T 45000 45900 5 10 1 1 0 0 1
+value=2K2
+T 44700 45900 5 10 0 0 0 0 1
+footprint=ACY300_1
+}
+C 43100 47200 1 0 0 gnd-1.sym
+N 45900 46700 46100 46700 4
+C 45800 45500 1 0 0 gnd-1.sym
+N 45600 46000 45900 46000 4
+N 43600 46000 43800 46000 4
+N 45900 46700 45900 45800 4
+T 47900 46400 9 10 1 0 0 1 1
++5V
+T 47900 46700 9 10 1 0 0 1 1
+GND
+T 47900 47000 9 10 1 0 0 1 1
+Signal

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