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New version of FX2 core - fixed Spartan-6 coregen issue

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kienko committed May 31, 2012
1 parent 24f8bd3 commit 8e5b810e43c58ffa6348849433690e4f9bb9b09d
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+###################################################################
+##
+## $xilinx_legal_disclaimer
+## tx_fifo.ngc,
+###################################################################
+
+Files
+################################################################################
+rx_fifo.ngc, tx_addr_fifo.ngc
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+###################################################################
+##
+## Name : xps_fx2
+## Desc : Microprocessor Peripheral Description
+## : Automatically generated by PsfUtility
+##
+###################################################################
+
+BEGIN xps_fx2
+
+## Peripheral Options
+OPTION IPTYPE = PERIPHERAL
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = VHDL
+OPTION IP_GROUP = Communication High-Speed:MICROBLAZE:PPC
+OPTION DESC = XPS_FX2
+#OPTION STYLE = MIX # used only if netlists are included
+OPTION STYLE = HDL
+OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT)
+OPTION ELABORATE_PROC = xps_fx2_generate
+#OPTION RUN_NGCBUILD = TRUE
+
+## Bus Interfaces
+BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
+BUS_INTERFACE BUS = FIFO_IN, BUS_STD = TRANSPARENT, BUS_TYPE = TARGET
+BUS_INTERFACE BUS = FIFO_OUT, BUS_STD = TRANSPARENT, BUS_TYPE = INITIATOR
+
+## Generics for VHDL or Parameters for Verilog
+PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x400, BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR
+PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR
+PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
+PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
+PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
+PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
+PARAMETER C_FAMILY = virtex5, DT = STRING
+PARAMETER C_TX_FIFO_KBYTE = 2, DT = INTEGER, RANGE = (2,4,8,16,32)
+PARAMETER C_RX_FIFO_KBYTE = 2, DT = INTEGER, RANGE = (0,2)
+PARAMETER C_USE_ADDR_FIFO = 0, DT = INTEGER, RANGE = (0)
+PARAMETER C_TX_RDY_ALMOST_FULL = 0, DT = INTEGER, RANGE = (0,1)
+PARAMETER C_TX_FIFO_CLK_180 = 0, DT = INTEGER, RANGE = (0,1)
+
+## Ports
+# ChipScope 32 bit trigger
+PORT ChipScope = "", DIR = O, VEC = [0:31]
+
+## FX2 Ports
+PORT USB_IFCLK = "", DIR = I, SIGIS = CLK
+PORT USB_SLRD = "", DIR = O
+PORT USB_SLWR = "", DIR = O
+PORT USB_FLAGA = "", DIR = I
+PORT USB_FLAGB = "", DIR = I
+PORT USB_FLAGC = "", DIR = I
+PORT USB_FLAGD = "", DIR = I
+PORT USB_SLOE = "", DIR = O
+PORT USB_PKTEND = "", DIR = O
+PORT USB_FIFOADR = "", DIR = O, VEC = [1:0]
+#PORT USB_FD = "", DIR = IO, VEC = [7:0], ENABLE=SINGLE, THREE_STATE=TRUE
+PORT USB_FD = "", DIR = IO, VEC = [7:0], ENABLE=MULTI, THREE_STATE=TRUE
+
+## FIFO Ports
+PORT TX_FIFO_Clk = "", DIR = I, SIGIS = CLK
+PORT RX_FIFO_Clk = "", DIR = I, SIGIS = CLK
+
+PORT TX_FIFO_DIN = Data, DIR = I, VEC = [0:31], BUS = FIFO_IN
+PORT TX_FIFO_VLD = Valid, DIR = I, BUS = FIFO_IN
+PORT TX_FIFO_RDY = Ready, DIR = O, BUS = FIFO_IN
+
+PORT RX_FIFO_DOUT = Data, DIR = O, VEC = [0:31], BUS = FIFO_OUT
+PORT RX_FIFO_VLD = Valid, DIR = O, BUS = FIFO_OUT
+PORT RX_FIFO_RDY = Ready, DIR = I, BUS = FIFO_OUT
+
+PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
+PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
+PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
+PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
+PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
+PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
+PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
+PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
+PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
+PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
+PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
+PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
+PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
+PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
+PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
+PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
+PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
+PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
+PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
+PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
+PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
+PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
+PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
+PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
+PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
+PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
+PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
+PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
+PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
+PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
+PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT IP2INTC_Irpt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
+
+END
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+##############################################################################
+## Filename: E:/Projekti/DWUSB/Trenz/SUBMIT/v0.8/TE0300_v0.8.0.0/pcores/xps_fx2_v1_00_a/data/xps_fx2_v2_1_0.pao
+## Description: Peripheral Analysis Order
+## Date: Thu Apr 17 20:27:53 2008 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+lib proc_common_v3_00_a proc_common_pkg vhdl
+lib proc_common_v3_00_a ipif_pkg vhdl
+lib proc_common_v3_00_a or_muxcy vhdl
+lib proc_common_v3_00_a or_gate128 vhdl
+lib proc_common_v3_00_a family_support vhdl
+lib proc_common_v3_00_a pselect_f vhdl
+lib proc_common_v3_00_a counter_f vhdl
+lib plbv46_slave_single_v1_01_a plb_address_decoder vhdl
+lib plbv46_slave_single_v1_01_a plb_slave_attachment vhdl
+lib plbv46_slave_single_v1_01_a plbv46_slave_single vhdl
+lib proc_common_v3_00_a soft_reset vhdl
+lib interrupt_control_v2_01_a interrupt_control vhdl
+lib xps_fx2_v1_50_b fx2_core vhdl
+lib xps_fx2_v1_50_b fx2_engine vhdl
+lib xps_fx2_v1_50_b user_logic vhdl
+lib xps_fx2_v1_50_b xps_fx2 vhdl
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