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New version of FX2 core - fixed Spartan-6 coregen issue

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1 parent 24f8bd3 commit 8e5b810e43c58ffa6348849433690e4f9bb9b09d @kienko kienko committed
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9 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/data/xps_fx2_v2_1_0.bbd
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+###################################################################
+##
+## $xilinx_legal_disclaimer
+## tx_fifo.ngc,
+###################################################################
+
+Files
+################################################################################
+rx_fifo.ngc, tx_addr_fifo.ngc
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121 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/data/xps_fx2_v2_1_0.mpd
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+###################################################################
+##
+## Name : xps_fx2
+## Desc : Microprocessor Peripheral Description
+## : Automatically generated by PsfUtility
+##
+###################################################################
+
+BEGIN xps_fx2
+
+## Peripheral Options
+OPTION IPTYPE = PERIPHERAL
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = VHDL
+OPTION IP_GROUP = Communication High-Speed:MICROBLAZE:PPC
+OPTION DESC = XPS_FX2
+#OPTION STYLE = MIX # used only if netlists are included
+OPTION STYLE = HDL
+OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT)
+OPTION ELABORATE_PROC = xps_fx2_generate
+#OPTION RUN_NGCBUILD = TRUE
+
+## Bus Interfaces
+BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
+BUS_INTERFACE BUS = FIFO_IN, BUS_STD = TRANSPARENT, BUS_TYPE = TARGET
+BUS_INTERFACE BUS = FIFO_OUT, BUS_STD = TRANSPARENT, BUS_TYPE = INITIATOR
+
+## Generics for VHDL or Parameters for Verilog
+PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x400, BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR
+PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR
+PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
+PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
+PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
+PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
+PARAMETER C_FAMILY = virtex5, DT = STRING
+PARAMETER C_TX_FIFO_KBYTE = 2, DT = INTEGER, RANGE = (2,4,8,16,32)
+PARAMETER C_RX_FIFO_KBYTE = 2, DT = INTEGER, RANGE = (0,2)
+PARAMETER C_USE_ADDR_FIFO = 0, DT = INTEGER, RANGE = (0)
+PARAMETER C_TX_RDY_ALMOST_FULL = 0, DT = INTEGER, RANGE = (0,1)
+PARAMETER C_TX_FIFO_CLK_180 = 0, DT = INTEGER, RANGE = (0,1)
+
+## Ports
+# ChipScope 32 bit trigger
+PORT ChipScope = "", DIR = O, VEC = [0:31]
+
+## FX2 Ports
+PORT USB_IFCLK = "", DIR = I, SIGIS = CLK
+PORT USB_SLRD = "", DIR = O
+PORT USB_SLWR = "", DIR = O
+PORT USB_FLAGA = "", DIR = I
+PORT USB_FLAGB = "", DIR = I
+PORT USB_FLAGC = "", DIR = I
+PORT USB_FLAGD = "", DIR = I
+PORT USB_SLOE = "", DIR = O
+PORT USB_PKTEND = "", DIR = O
+PORT USB_FIFOADR = "", DIR = O, VEC = [1:0]
+#PORT USB_FD = "", DIR = IO, VEC = [7:0], ENABLE=SINGLE, THREE_STATE=TRUE
+PORT USB_FD = "", DIR = IO, VEC = [7:0], ENABLE=MULTI, THREE_STATE=TRUE
+
+## FIFO Ports
+PORT TX_FIFO_Clk = "", DIR = I, SIGIS = CLK
+PORT RX_FIFO_Clk = "", DIR = I, SIGIS = CLK
+
+PORT TX_FIFO_DIN = Data, DIR = I, VEC = [0:31], BUS = FIFO_IN
+PORT TX_FIFO_VLD = Valid, DIR = I, BUS = FIFO_IN
+PORT TX_FIFO_RDY = Ready, DIR = O, BUS = FIFO_IN
+
+PORT RX_FIFO_DOUT = Data, DIR = O, VEC = [0:31], BUS = FIFO_OUT
+PORT RX_FIFO_VLD = Valid, DIR = O, BUS = FIFO_OUT
+PORT RX_FIFO_RDY = Ready, DIR = I, BUS = FIFO_OUT
+
+PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
+PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
+PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
+PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
+PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
+PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
+PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
+PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
+PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
+PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
+PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
+PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
+PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
+PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
+PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
+PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
+PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
+PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
+PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
+PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
+PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
+PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
+PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
+PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
+PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
+PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
+PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
+PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
+PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
+PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
+PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT IP2INTC_Irpt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
+
+END
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22 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/data/xps_fx2_v2_1_0.pao
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+##############################################################################
+## Filename: E:/Projekti/DWUSB/Trenz/SUBMIT/v0.8/TE0300_v0.8.0.0/pcores/xps_fx2_v1_00_a/data/xps_fx2_v2_1_0.pao
+## Description: Peripheral Analysis Order
+## Date: Thu Apr 17 20:27:53 2008 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+lib proc_common_v3_00_a proc_common_pkg vhdl
+lib proc_common_v3_00_a ipif_pkg vhdl
+lib proc_common_v3_00_a or_muxcy vhdl
+lib proc_common_v3_00_a or_gate128 vhdl
+lib proc_common_v3_00_a family_support vhdl
+lib proc_common_v3_00_a pselect_f vhdl
+lib proc_common_v3_00_a counter_f vhdl
+lib plbv46_slave_single_v1_01_a plb_address_decoder vhdl
+lib plbv46_slave_single_v1_01_a plb_slave_attachment vhdl
+lib plbv46_slave_single_v1_01_a plbv46_slave_single vhdl
+lib proc_common_v3_00_a soft_reset vhdl
+lib interrupt_control_v2_01_a interrupt_control vhdl
+lib xps_fx2_v1_50_b fx2_core vhdl
+lib xps_fx2_v1_50_b fx2_engine vhdl
+lib xps_fx2_v1_50_b user_logic vhdl
+lib xps_fx2_v1_50_b xps_fx2 vhdl
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769 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/data/xps_fx2_v2_1_0.tcl
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+##----------------------------------------------------------------------------
+## $Revision: 1.5 $
+## $Date: 2005/09/15 01:44:39 $
+##----------------------------------------------------------------------------
+## xps_fx2
+##----------------------------------------------------------------------------
+##
+## ***************************************************************************
+## ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved. **
+## ** **
+## ** This text contains proprietary, confidential **
+## ** information of Xilinx, Inc. , is distributed by **
+## ** under license from Xilinx, Inc., and may be used, **
+## ** copied and/or disclosed only pursuant to the terms **
+## ** of a valid license agreement with Xilinx, Inc. **
+## ** **
+## ** Unmodified source code is guaranteed to place and route, **
+## ** function and run at speed according to the datasheet **
+## ** specification. Source code is provided "as-is", with no **
+## ** obligation on the part of Xilinx to provide support. **
+## ** **
+## ** Xilinx Hotline support of source code IP shall only include **
+## ** standard level Xilinx Hotline support, and will only address **
+## ** issues and questions related to the standard released Netlist **
+## ** version of the core (and thus indirectly, the original core source). **
+## ** **
+## ** The Xilinx Support Hotline does not have access to source **
+## ** code and therefore cannot answer specific questions related **
+## ** to source HDL. The Xilinx Support Hotline will only be able **
+## ** to confirm the problem in the Netlist version of the core. **
+## ** **
+## ** This copyright and support notice must be retained as part **
+## ** of this text at all times. **
+## ***************************************************************************
+##
+##----------------------------------------------------------------------------
+## Filename: xps_fx2_v2_1_0.tcl
+##
+##----------------------------------------------------------------------------
+## Author: AG
+## History:
+## AG 03.08.2009 - Updated to support S3A DSP and generation of all fifos
+## ole2 10.02.2011 - Fixed for CoreGen 7.2 and Xilinx 12.4 environment
+##
+##----------------------------------------------------------------------------
+
+proc xps_fx2_generate { handle } {
+
+##------COPY OTHER NETLIST FILE
+ #file copy -force [pwd]/pcores/xps_fx2_v1_00_a/netlist/rx_fifo.ngc [pwd]/implementation/
+ #file copy -force [pwd]/pcores/xps_fx2_v1_00_a/netlist/tx_addr_fifo.ngc [pwd]/implementation/
+
+ set param_names {
+ "INSTANCE"
+ "HW_VER"
+ "C_FAMILY"
+ "C_TX_FIFO_KBYTE"
+ "C_RX_FIFO_KBYTE"
+ "C_USE_ADDR_FIFO"
+ }
+
+ set param_table {}
+
+ foreach name $param_names {
+ lappend param_table $name
+ lappend param_table [xget_value $handle "PARAMETER" $name]
+ }
+
+ # put the PARAMETER name value pairs into an associative array
+ # for easy access Ex: set instance_name $params(INSTANCE)
+ array set params $param_table
+ set cg_projdir [pwd]/implementation/$params(INSTANCE)_wrapper
+ set logfilename "$cg_projdir/$params(INSTANCE)_fifo.log"
+ set logfile [open $logfilename "w"]
+
+##------GENERATE tx_fifo
+ set tx_fifo_detect 0
+
+ if { [file exists $cg_projdir/tx_fifo.ngc] } {
+ puts "Detected tx_fifo.ngc"
+ puts $logfile "Detected tx_fifo.ngc"
+ if { [file exists $cg_projdir/$params(INSTANCE)_tx_fifo$params(C_TX_FIFO_KBYTE)k.arg] } {
+ puts "Detected tx_fifo is of a right size"
+ puts $logfile "Detected tx_fifo is of a right size"
+ set tx_fifo_detect 1
+ }
+ }
+
+
+ if { $tx_fifo_detect == 1 } {
+ file copy -force $cg_projdir/tx_fifo.ngc [pwd]/implementation/
+ }
+
+ if { $tx_fifo_detect == 0 } {
+
+ puts ""
+ puts "*******************************************************************"
+ puts "* $params(INSTANCE) : Generating TX FIFO LogiCORE"
+ puts "*******************************************************************"
+ puts ""
+ puts " Param values are : $param_table"
+ puts ""
+ puts $logfile "**********************************************************"
+ puts $logfile "* $params(INSTANCE)"
+ puts $logfile "**********************************************************"
+
+ ############################################################################
+ # Write out a Core Generator arg file that matches
+ # the parameters set by the user.
+ ############################################################################
+
+ set projectfilename "$cg_projdir/coregen.cgp"
+ set argfile [open $projectfilename "w"]
+
+ #must be for any fifo
+ puts $argfile "NEWPROJECT $cg_projdir"
+ puts $argfile "SETPROJECT $cg_projdir"
+ puts $argfile "# BEGIN Project Options"
+ puts $argfile "SET addpads = False"
+ puts $argfile "SET asysymbol = True"
+ puts $argfile "SET busformat = BusFormatAngleBracketNotRipped"
+ puts $argfile "SET createndf = False"
+ puts $argfile "SET designentry = VHDL"
+
+ switch $params(C_FAMILY) {
+ "spartan3e" {
+ puts $argfile "SET device = xc3s500e"
+ puts $argfile "SET devicefamily = spartan3e"
+ }
+ "spartan3" {
+ puts $argfile "SET device = xc3s400"
+ puts $argfile "SET devicefamily = spartan3"
+ }
+ "spartan3adsp" {
+ puts $argfile "SET device = xc3sd1800a"
+ puts $argfile "SET devicefamily = spartan3adsp"
+ }
+ "spartan6" {
+ puts $argfile "SET device = xc6slx25"
+ puts $argfile "SET devicefamily = spartan6"
+ }
+ default {
+ puts "ERROR:invalid family $params(C_FAMILY)!!"
+ }
+ }
+ puts $argfile "SET flowvendor = Foundation_iSE"
+ puts $argfile "SET formalverification = False"
+ puts $argfile "SET foundationsym = False"
+ puts $argfile "SET implementationfiletype = Ngc"
+
+ switch $params(C_FAMILY) {
+ "spartan6" {
+ puts $argfile "SET package = ftg256"
+ puts $argfile "SET speedgrade = -3"
+ }
+ "spartan3adsp" {
+ puts $argfile "SET package = fg676"
+ puts $argfile "SET speedgrade = -4"
+ }
+ default {
+ puts $argfile "SET package = pq208"
+ puts $argfile "SET speedgrade = -4"
+ }
+ }
+
+
+ puts $argfile "SET removerpms = False"
+ puts $argfile "SET simulationfiles = Behavioral"
+ puts $argfile "SET verilogsim = True"
+
+ puts $argfile "SET vhdlsim = False"
+ puts $argfile "# END Project Options"
+ close $argfile
+
+ set filename "$cg_projdir/$params(INSTANCE)_tx_fifo$params(C_TX_FIFO_KBYTE)k.arg"
+ set argfile [open $filename "w"]
+ puts $argfile "SELECT Fifo_Generator family Xilinx,_Inc. 7.2"
+
+ # FOR tx_fifo
+
+ set tx_fifo_size $params(C_TX_FIFO_KBYTE)
+
+ puts $argfile "# BEGIN Parameters"
+ puts $argfile "CSET almost_empty_flag=false"
+ puts $argfile "CSET almost_full_flag=true"
+ puts $argfile "CSET component_name=tx_fifo"
+ puts $argfile "CSET data_count=false"
+ switch $tx_fifo_size {
+ "2" {
+ puts $argfile "CSET data_count_width=9"
+ }
+ "4" {
+ puts $argfile "CSET data_count_width=10"
+ }
+ "8" {
+ puts $argfile "CSET data_count_width=11"
+ }
+ "16" {
+ puts $argfile "CSET data_count_width=12"
+ }
+ "32" {
+ puts $argfile "CSET data_count_width=13"
+ }
+ default {
+ puts $argfile "CSET data_count_width=9"
+ }
+ }
+ puts $argfile "CSET dout_reset_value=0"
+ puts $argfile "CSET empty_threshold_assert_value=2"
+ puts $argfile "CSET empty_threshold_negate_value=3"
+ puts $argfile "CSET enable_ecc=false"
+# puts $argfile "CSET enable_int_clk=false"
+ puts $argfile "CSET fifo_implementation=Independent_Clocks_Block_RAM"
+ puts $argfile "CSET full_flags_reset_value=0"
+ switch $tx_fifo_size {
+ "2" {
+ puts $argfile "CSET full_threshold_assert_value=509"
+ puts $argfile "CSET full_threshold_negate_value=508"
+ puts $argfile "CSET input_data_width=32"
+ puts $argfile "CSET input_depth=512"
+ puts $argfile "CSET output_data_width=8"
+ puts $argfile "CSET output_depth=2048"
+ }
+
+ "4" {
+ puts $argfile "CSET full_threshold_assert_value=1018"
+ puts $argfile "CSET full_threshold_negate_value=1016"
+ puts $argfile "CSET input_data_width=32"
+ puts $argfile "CSET input_depth=1024"
+ puts $argfile "CSET output_data_width=8"
+ puts $argfile "CSET output_depth=4096"
+ }
+
+ "8" {
+ puts $argfile "CSET full_threshold_assert_value=2036"
+ puts $argfile "CSET full_threshold_negate_value=2032"
+ puts $argfile "CSET input_data_width=32"
+ puts $argfile "CSET input_depth=2048"
+ puts $argfile "CSET output_data_width=8"
+ puts $argfile "CSET output_depth=8192"
+ }
+ "16" {
+ puts $argfile "CSET full_threshold_assert_value=4072"
+ puts $argfile "CSET full_threshold_negate_value=4064"
+ puts $argfile "CSET input_data_width=32"
+ puts $argfile "CSET input_depth=4096"
+ puts $argfile "CSET output_data_width=8"
+ puts $argfile "CSET output_depth=16384"
+ }
+ "32" {
+ puts $argfile "CSET full_threshold_assert_value=8114"
+ puts $argfile "CSET full_threshold_negate_value=8128"
+ puts $argfile "CSET input_data_width=32"
+ puts $argfile "CSET input_depth=8192"
+ puts $argfile "CSET output_data_width=8"
+ puts $argfile "CSET output_depth=32768"
+ }
+
+ default {
+ puts $argfile "CSET full_threshold_assert_value=509"
+ puts $argfile "CSET full_threshold_negate_value=508"
+ puts $argfile "CSET input_data_width=32"
+ puts $argfile "CSET input_depth=512"
+ puts $argfile "CSET output_data_width=8"
+ puts $argfile "CSET output_depth=2048"
+ }
+ }
+
+ puts $argfile "CSET overflow_flag=true"
+ puts $argfile "CSET overflow_sense=Active_High"
+ puts $argfile "CSET performance_options=Standard_FIFO"
+ puts $argfile "CSET programmable_empty_type=No_Programmable_Empty_Threshold"
+ puts $argfile "CSET programmable_full_type=No_Programmable_Full_Threshold"
+ puts $argfile "CSET read_clock_frequency=1"
+ puts $argfile "CSET read_data_count=false"
+ puts $argfile "CSET read_data_count_width=11"
+ puts $argfile "CSET reset_pin=true"
+ puts $argfile "CSET reset_type=Asynchronous_Reset"
+ puts $argfile "CSET underflow_flag=true"
+ puts $argfile "CSET underflow_sense=Active_High"
+ puts $argfile "CSET use_dout_reset=true"
+ puts $argfile "CSET use_embedded_registers=false"
+ puts $argfile "CSET use_extra_logic=false"
+ puts $argfile "CSET valid_flag=true"
+ puts $argfile "CSET valid_sense=Active_High"
+ puts $argfile "CSET write_acknowledge_flag=false"
+ puts $argfile "CSET write_acknowledge_sense=Active_High"
+ puts $argfile "CSET write_clock_frequency=1"
+ puts $argfile "CSET write_data_count=true"
+ switch $tx_fifo_size {
+ "2" {
+ puts $argfile "CSET write_data_count_width=9"
+ }
+ "4" {
+ puts $argfile "CSET write_data_count_width=10"
+ }
+ "8" {
+ puts $argfile "CSET write_data_count_width=11"
+ }
+ "16" {
+ puts $argfile "CSET write_data_count_width=12"
+ }
+ "32" {
+ puts $argfile "CSET write_data_count_width=13"
+ }
+ default {
+ puts $argfile "CSET write_data_count_width=9"
+ }
+ }
+ puts $argfile "# END Parameters"
+ puts $argfile "GENERATE"
+
+
+
+ close $argfile
+
+ ############################################################################
+ # Call Core Generator with the arg file to create
+ # the core netlist in <proj>/implementation/CORE_INSTANCENAME/.
+ # Platgen will run ngcbuild from this location to merge the netlists
+ # into a single NGC file. This helps in case of multiple instantiations
+ # of the same core.
+ ############################################################################
+
+ puts " $params(INSTANCE) : Running Core Generator to generate TX FIFO."
+ puts " * This will take several minutes. . ."
+ puts ""
+ puts $logfile "$params(INSTANCE) : Running Core Generator to generate TX FIFO. . ."
+ file mkdir $cg_projdir
+ catch { exec coregen -p $projectfilename -b $filename } msg
+
+ if { [file exists $cg_projdir/tx_fifo.ngc] } {
+ file copy -force $cg_projdir/tx_fifo.ngc [pwd]/implementation/
+ puts ""
+ puts "*******************************************************************"
+ puts "* Successfully generated the TX FIFO LogiCORE: $params(INSTANCE)"
+ puts "* - copied to ./implementation/$params(INSTANCE)_wrapper/"
+ puts "*******************************************************************"
+ puts ""
+ file del $cg_projdir/coregen.cgc
+ } else {
+ puts "$params(INSTANCE): ERROR - TX FIFO Core Generation Failed"
+ puts ""
+ puts $logfile "$params(INSTANCE): ERROR TX FIFO Core Generation Failed"
+ puts ""
+ puts $logfile ""
+ close $logfile
+ return
+ }
+
+ puts ""
+
+ }
+
+
+ ##------GENERATE tx_addr_fifo
+ set tx_addr_fifo_detect 0
+
+ if { [file exists $cg_projdir/tx_addr_fifo.ngc] } {
+ puts "Detected tx_addr_fifo.ngc"
+ puts $logfile "Detected tx_addr_fifo.ngc"
+ if { [file exists $cg_projdir/$params(INSTANCE)_tx_addr_fifo$params(C_TX_FIFO_KBYTE)k.arg] } {
+ set tx_addr_fifo_detect 1
+ }
+ }
+
+ if { $tx_addr_fifo_detect == 1 } {
+ file copy -force $cg_projdir/tx_addr_fifo.ngc [pwd]/implementation/
+ }
+ if {$params(C_USE_ADDR_FIFO) == 0} {
+ set tx_addr_fifo_detect 1
+ }
+ if { $tx_addr_fifo_detect == 0 } {
+ puts ""
+ puts "*******************************************************************"
+ puts "* $params(INSTANCE) : Generating TX ADDR FIFO LogiCORE"
+ puts "*******************************************************************"
+ puts ""
+ puts " Param values are : $param_table"
+ puts ""
+ puts $logfile "**********************************************************"
+ puts $logfile "* $params(INSTANCE)"
+ puts $logfile "**********************************************************"
+
+ ############################################################################
+ # Write out a Core Generator arg file that matches
+ # the parameters set by the user.
+ ############################################################################
+
+ set filename "$cg_projdir/$params(INSTANCE)_tx_addr_fifo$params(C_RX_FIFO_KBYTE)k.arg"
+ set argfile [open $filename "w"]
+
+ #must be for any fifo
+# puts $argfile "NEWPROJECT $cg_projdir"
+# puts $argfile "SETPROJECT $cg_projdir"
+# puts $argfile "# BEGIN Project Options"
+# puts $argfile "SET addpads = False"
+# puts $argfile "SET asysymbol = True"
+# puts $argfile "SET busformat = BusFormatAngleBracketNotRipped"
+# puts $argfile "SET createndf = False"
+# puts $argfile "SET designentry = VHDL"
+# switch $params(C_FAMILY) {
+# "spartan3e" {
+# puts $argfile "SET device = xc3s500e"
+# puts $argfile "SET devicefamily = spartan3e"
+# }
+# "spartan3" {
+# puts $argfile "SET device = xc3s400"
+# puts $argfile "SET devicefamily = spartan3"
+# }
+# "spartan3adsp" {
+# puts $argfile "SET device = xc3sd1800a"
+# puts $argfile "SET devicefamily = spartan3adsp"
+# }
+# "spartan6" {
+# puts $argfile "SET device = xc6slx25"
+# puts $argfile "SET devicefamily = spartan6"
+# }
+# default {
+# puts "ERROR:invalid family $params(C_FAMILY)!!"
+# }
+# }
+# puts $argfile "SET flowvendor = Foundation_iSE"
+# puts $argfile "SET formalverification = False"
+# puts $argfile "SET foundationsym = False"
+# puts $argfile "SET implementationfiletype = Ngc"
+# switch $params(C_FAMILY) {
+# "spartan6" {
+# puts $argfile "SET package = ftg256"
+# puts $argfile "SET speedgrade = -3"
+# }
+# "spartan3adsp" {
+# puts $argfile "SET package = fg676"
+# puts $argfile "SET speedgrade = -4"
+# }
+# default {
+# puts $argfile "SET package = pq208"
+# puts $argfile "SET speedgrade = -4"
+# }
+# }
+# puts $argfile "SET removerpms = False"
+# puts $argfile "SET simulationfiles = Behavioral"
+# puts $argfile "SET verilogsim = True"
+# puts $argfile "SET vhdlsim = True"
+# puts $argfile "# END Project Options"
+
+ puts $argfile "# BEGIN Select"
+ puts $argfile "SELECT Fifo_Generator family Xilinx,_Inc. 7.2"
+ puts $argfile "# END Select"
+ puts $argfile "# BEGIN Parameters"
+ puts $argfile "CSET almost_empty_flag=false"
+ puts $argfile "CSET almost_full_flag=false"
+ puts $argfile "CSET component_name=tx_addr_fifo"
+ puts $argfile "CSET data_count=false"
+ puts $argfile "CSET data_count_width=9"
+ puts $argfile "CSET dout_reset_value=0"
+ puts $argfile "CSET empty_threshold_assert_value=4"
+ puts $argfile "CSET empty_threshold_negate_value=5"
+ puts $argfile "CSET enable_ecc=false"
+# puts $argfile "CSET enable_int_clk=false"
+ puts $argfile "CSET fifo_implementation=Independent_Clocks_Distributed_RAM"
+ puts $argfile "CSET full_flags_reset_value=0"
+
+ switch $tx_fifo_size {
+ "2" {
+ puts $argfile "CSET full_threshold_assert_value=509"
+ puts $argfile "CSET full_threshold_negate_value=508"
+ puts $argfile "CSET input_data_width=2"
+ puts $argfile "CSET input_depth=512"
+ puts $argfile "CSET output_data_width=2"
+ puts $argfile "CSET output_depth=512"
+ }
+
+ "4" {
+ puts $argfile "CSET full_threshold_assert_value=1018"
+ puts $argfile "CSET full_threshold_negate_value=1016"
+ puts $argfile "CSET input_data_width=2"
+ puts $argfile "CSET input_depth=1024"
+ puts $argfile "CSET output_data_width=2"
+ puts $argfile "CSET output_depth=1024"
+ }
+
+ "8" {
+ puts $argfile "CSET full_threshold_assert_value=2036"
+ puts $argfile "CSET full_threshold_negate_value=2032"
+ puts $argfile "CSET input_data_width=2"
+ puts $argfile "CSET input_depth=2048"
+ puts $argfile "CSET output_data_width=2"
+ puts $argfile "CSET output_depth=2048"
+ }
+ "16" {
+ puts $argfile "CSET full_threshold_assert_value=2036"
+ puts $argfile "CSET full_threshold_negate_value=2032"
+ puts $argfile "CSET input_data_width=2"
+ puts $argfile "CSET input_depth=4096"
+ puts $argfile "CSET output_data_width=2"
+ puts $argfile "CSET output_depth=4096"
+ }
+ "32" {
+ puts $argfile "CSET full_threshold_assert_value=2036"
+ puts $argfile "CSET full_threshold_negate_value=2032"
+ puts $argfile "CSET input_data_width=2"
+ puts $argfile "CSET input_depth=8192"
+ puts $argfile "CSET output_data_width=2"
+ puts $argfile "CSET output_depth=8192"
+ }
+ default {
+ puts $argfile "CSET full_threshold_assert_value=509"
+ puts $argfile "CSET full_threshold_negate_value=508"
+ puts $argfile "CSET input_data_width=2"
+ puts $argfile "CSET input_depth=512"
+ puts $argfile "CSET output_data_width=2"
+ puts $argfile "CSET output_depth=512"
+ }
+ }
+
+ puts $argfile "CSET overflow_flag=false"
+ puts $argfile "CSET overflow_sense=Active_High"
+ puts $argfile "CSET performance_options=First_Word_Fall_Through"
+ puts $argfile "CSET programmable_empty_type=No_Programmable_Empty_Threshold"
+ puts $argfile "CSET programmable_full_type=No_Programmable_Full_Threshold"
+ puts $argfile "CSET read_clock_frequency=1"
+ puts $argfile "CSET read_data_count=false"
+ puts $argfile "CSET read_data_count_width=9"
+ puts $argfile "CSET reset_pin=true"
+ puts $argfile "CSET reset_type=Asynchronous_Reset"
+ puts $argfile "CSET underflow_flag=false"
+ puts $argfile "CSET underflow_sense=Active_High"
+ puts $argfile "CSET use_dout_reset=true"
+ puts $argfile "CSET use_embedded_registers=false"
+ puts $argfile "CSET use_extra_logic=false"
+ puts $argfile "CSET valid_flag=false"
+ puts $argfile "CSET valid_sense=Active_High"
+ puts $argfile "CSET write_acknowledge_flag=false"
+ puts $argfile "CSET write_acknowledge_sense=Active_High"
+ puts $argfile "CSET write_clock_frequency=1"
+ puts $argfile "CSET write_data_count=false"
+ puts $argfile "CSET write_data_count_width=9"
+ puts $argfile "# END Parameters"
+ puts $argfile "GENERATE"
+ puts $argfile "GENERATE"
+
+ close $argfile
+
+ ############################################################################
+ # Call Core Generator with the arg file to create
+ # the core netlist in <proj>/implementation/CORE_INSTANCENAME/.
+ # Platgen will run ngcbuild from this location to merge the netlists
+ # into a single NGC file. This helps in case of multiple instantiations
+ # of the same core.
+ ############################################################################
+
+ puts " $params(INSTANCE) : Running Core Generator to generate TX ADDR FIFO."
+ puts " * This will take several minutes. . ."
+ puts ""
+ puts $logfile "$params(INSTANCE) : Running Core Generator to generate TX ADDR FIFO. . ."
+ catch { exec coregen -p $projectfilename -b $filename } msg
+
+ if { [file exists $cg_projdir/tx_addr_fifo.ngc] } {
+ file copy -force $cg_projdir/tx_addr_fifo.ngc [pwd]/implementation/
+ puts ""
+ puts "*******************************************************************"
+ puts "* Successfully generated the TX ADDR FIFO LogiCORE: $params(INSTANCE)"
+ puts "* - copied to ./implementation/$params(INSTANCE)_wrapper/"
+ puts "*******************************************************************"
+ puts ""
+ file del $cg_projdir/coregen.cgc
+ } else {
+ puts "$params(INSTANCE): ERROR - TX ADDR FIFO Core Generation Failed"
+ puts ""
+ puts $logfile "$params(INSTANCE): ERROR TX ADDR FIFO Core Generation Failed"
+ puts ""
+ puts $logfile ""
+ close $logfile
+ return
+ }
+
+ }
+
+
+
+ ##------GENERATE rx_fifo
+ if {$params(C_RX_FIFO_KBYTE) == 0} {
+ close $logfile
+ return
+ }
+
+
+ set rx_fifo_detect 0
+
+ if { [file exists $cg_projdir/rx_fifo.ngc] } {
+ puts "Detected rx_fifo.ngc"
+ puts $logfile "Detected rx_fifo.ngc"
+ if { [file exists $cg_projdir/$params(INSTANCE)_rx_fifo$params(C_RX_FIFO_KBYTE)k.arg] } {
+ set rx_fifo_detect 1
+ }
+ }
+
+ if { $rx_fifo_detect == 1 } {
+ file copy -force $cg_projdir/rx_fifo.ngc [pwd]/implementation/
+ }
+ if { $rx_fifo_detect == 0 } {
+ puts ""
+ puts "*******************************************************************"
+ puts "* $params(INSTANCE) : Generating RX FIFO LogiCORE"
+ puts "*******************************************************************"
+ puts ""
+ puts " Param values are : $param_table"
+ puts ""
+ puts $logfile "**********************************************************"
+ puts $logfile "* $params(INSTANCE)"
+ puts $logfile "**********************************************************"
+
+ ############################################################################
+ # Write out a Core Generator arg file that matches
+ # the parameters set by the user.
+ ############################################################################
+
+ set filename "$cg_projdir/$params(INSTANCE)_rx_fifo$params(C_RX_FIFO_KBYTE)k.arg"
+ set argfile [open $filename "w"]
+
+ #must be for any fifo
+# puts $argfile "NEWPROJECT $cg_projdir"
+# puts $argfile "SETPROJECT $cg_projdir"
+# puts $argfile "# BEGIN Project Options"
+# puts $argfile "SET addpads = False"
+# puts $argfile "SET asysymbol = False"
+# puts $argfile "SET busformat = BusFormatAngleBracketNotRipped"
+# puts $argfile "SET createndf = False"
+# puts $argfile "SET designentry = VHDL"
+# switch $params(C_FAMILY) {
+# "spartan3e" {
+# puts $argfile "SET device = xc3s500e"
+# puts $argfile "SET devicefamily = spartan3e"
+# }
+# "spartan3" {
+# puts $argfile "SET device = xc3s400"
+# puts $argfile "SET devicefamily = spartan3"
+# }
+# "spartan3adsp" {
+# puts $argfile "SET device = xc3sd1800a"
+# puts $argfile "SET devicefamily = spartan3adsp"
+# }
+# "spartan6" {
+# puts $argfile "SET device = xc6slx25"
+# puts $argfile "SET devicefamily = spartan6"
+# }
+# default {
+# puts "ERROR:invalid family $params(C_FAMILY)!!"
+# }
+# }
+# puts $argfile "SET flowvendor = Foundation_iSE"
+# puts $argfile "SET formalverification = False"
+# puts $argfile "SET foundationsym = False"
+# puts $argfile "SET implementationfiletype = Ngc"
+# switch $params(C_FAMILY) {
+# "spartan6" {
+# puts $argfile "SET package = ftg256"
+# puts $argfile "SET speedgrade = -3"
+# }
+# "spartan3adsp" {
+# puts $argfile "SET package = fg676"
+# puts $argfile "SET speedgrade = -4"
+# }
+# default {
+# puts $argfile "SET package = pq208"
+# puts $argfile "SET speedgrade = -4"
+# }
+# }
+# puts $argfile "SET removerpms = False"
+# puts $argfile "SET simulationfiles = Behavioral"
+# puts $argfile "SET verilogsim = True"
+# puts $argfile "SET vhdlsim = True"
+# puts $argfile "# END Project Options"
+
+ puts $argfile "# BEGIN Select"
+ puts $argfile "SELECT Fifo_Generator family Xilinx,_Inc. 7.2"
+ puts $argfile "# END Select"
+ puts $argfile "# BEGIN Parameters"
+ puts $argfile "CSET almost_empty_flag=false"
+ puts $argfile "CSET almost_full_flag=true"
+ puts $argfile "CSET component_name=rx_fifo"
+ puts $argfile "CSET data_count=false"
+ puts $argfile "CSET data_count_width=12"
+ puts $argfile "CSET dout_reset_value=0"
+ puts $argfile "CSET empty_threshold_assert_value=4"
+ puts $argfile "CSET empty_threshold_negate_value=5"
+ puts $argfile "CSET enable_ecc=false"
+# puts $argfile "CSET enable_int_clk=false"
+ puts $argfile "CSET fifo_implementation=Independent_Clocks_Block_RAM"
+ puts $argfile "CSET full_flags_reset_value=0"
+ puts $argfile "CSET full_threshold_assert_value=2047"
+ puts $argfile "CSET full_threshold_negate_value=2046"
+ puts $argfile "CSET input_data_width=8"
+ puts $argfile "CSET input_depth=2048"
+ puts $argfile "CSET output_data_width=32"
+ puts $argfile "CSET output_depth=512"
+ puts $argfile "CSET overflow_flag=true"
+ puts $argfile "CSET overflow_sense=Active_High"
+ puts $argfile "CSET performance_options=First_Word_Fall_Through"
+ puts $argfile "CSET programmable_empty_type=No_Programmable_Empty_Threshold"
+ puts $argfile "CSET programmable_full_type=No_Programmable_Full_Threshold"
+ puts $argfile "CSET read_clock_frequency=1"
+ puts $argfile "CSET read_data_count=true"
+ puts $argfile "CSET read_data_count_width=10"
+ puts $argfile "CSET reset_pin=true"
+ puts $argfile "CSET reset_type=Asynchronous_Reset"
+ puts $argfile "CSET underflow_flag=true"
+ puts $argfile "CSET underflow_sense=Active_High"
+ puts $argfile "CSET use_dout_reset=true"
+ puts $argfile "CSET use_embedded_registers=false"
+ puts $argfile "CSET use_extra_logic=true"
+ puts $argfile "CSET valid_flag=true"
+ puts $argfile "CSET valid_sense=Active_High"
+ puts $argfile "CSET write_acknowledge_flag=false"
+ puts $argfile "CSET write_acknowledge_sense=Active_High"
+ puts $argfile "CSET write_clock_frequency=1"
+ puts $argfile "CSET write_data_count=false"
+ puts $argfile "CSET write_data_count_width=12"
+ puts $argfile "# END Parameters"
+ puts $argfile "GENERATE"
+
+
+ close $argfile
+
+
+ ############################################################################
+ # Call Core Generator with the arg file to create
+ # the core netlist in <proj>/implementation/CORE_INSTANCENAME/.
+ # Platgen will run ngcbuild from this location to merge the netlists
+ # into a single NGC file. This helps in case of multiple instantiations
+ # of the same core.
+ ############################################################################
+
+ puts " $params(INSTANCE) : Running Core Generator to generate FIFO."
+ puts " * This will take several minutes. . ."
+ puts ""
+ puts $logfile "$params(INSTANCE) : Running Core Generator to generate RX FIFO. . ."
+ file mkdir $cg_projdir
+ catch { exec coregen -p $projectfilename -b $filename } msg
+
+ if { [file exists $cg_projdir/rx_fifo.ngc] } {
+ file copy -force $cg_projdir/rx_fifo.ngc [pwd]/implementation/
+ puts ""
+ puts "*******************************************************************"
+ puts "* Successfully generated the RX FIFO LogiCORE: $params(INSTANCE)"
+ puts "* - copied to ./implementation/$params(INSTANCE)_wrapper/"
+ puts "*******************************************************************"
+ puts ""
+ file del $cg_projdir/coregen.cgc
+ } else {
+ puts "$params(INSTANCE): ERROR - RX FIFO Core Generation Failed"
+ puts ""
+ puts $logfile "$params(INSTANCE): ERROR RX FIFO Core Generation Failed"
+ puts ""
+ puts $logfile ""
+ close $logfile
+ return
+ }
+
+ }
+
+
+ close $logfile
+
+ return
+
+}
+
View
23 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/fx2_core.ucf
@@ -0,0 +1,23 @@
+#================================================
+# EZ-USB FX2 Interface
+#================================================
+Net USB_IFCLK_pin TNM_Net = USB_IFCLK_pin;
+TIMESPEC TS_USB_IFCLK_pin = PERIOD USB_IFCLK_pin 20833 ps;
+
+# FX2 timing constrains
+NET "USB_FD_pin<*>" OFFSET = IN 9 ns BEFORE "USB_IFCLK_pin" RISING;
+TIMESPEC TS_B2P = FROM RAMS TO PADS 10 ns;
+NET "USB_FLAGB_pin" OFFSET = IN 10 ns BEFORE "USB_IFCLK_pin" RISING;
+NET "USB_FLAGD_pin" OFFSET = IN 10 ns BEFORE "USB_IFCLK_pin" RISING;
+NET "USB_SLWR_pin" OFFSET = OUT 9 ns AFTER "USB_IFCLK_pin" RISING;
+# USB_SLRD_pin drived from flip-flop in OPAD, so there is maximum that you can get from this device
+NET "USB_SLRD_pin" OFFSET = OUT 7.4 ns AFTER "USB_IFCLK_pin" RISING; # If you don't use DCM
+#NET "USB_SLRD_pin" OFFSET = OUT 5.7 ns AFTER "USB_IFCLK_pin" RISING; # If you use DCM
+NET "USB_SLOE_pin" OFFSET = OUT 9 ns AFTER "USB_IFCLK_pin" RISING;
+NET "USB_PKTEND_pin" OFFSET = OUT 9 ns AFTER "USB_IFCLK_pin" RISING;
+NET "USB_FIFOADR_pin<*>" OFFSET = OUT 9.5 ns AFTER "USB_IFCLK_pin" RISING;
+
+#NET "USB_IFCLK_pin" CLOCK_DEDICATED_ROUTE = FALSE;
+
+Net USB_*_pin* IOSTANDARD = LVCMOS33;
+
View
438 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/hdl/vhdl/fx2_core.vhd
@@ -0,0 +1,438 @@
+-----------------------------------------------------
+--
+-- Filename: mfx2_core.vhd
+-- Version: 0.3
+-- Author: Ales Gorkic
+-- Company: KOLT
+-- Phone: 031 345993
+-- Email: ales.gorkic@fs.uni-lj.si
+-- Change History:
+-- Date Version Comments
+-- 07.04.06 0.3 The OPB Master, FIFO and Frontend work !
+--
+-------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics/parameters: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_cmb"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port "*_i"
+-- ports: - Names begin with Uppercase
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Port Declaration
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+--
+-- Definition of Generics:
+-- C_FAMILY -- Target FGPA family
+-- C_OPB_AWIDTH -- OPB address bus width
+-- C_OPB_DWIDTH -- OPB data bus width
+-- C_SOPB_BASEADDR -- SOPB base address
+-- C_SOPB_HIGHADDR -- SOPB high address
+--
+-- Definition of Ports:
+-- Interrupt -- Interrupt output to MB or INTC
+--
+-- SYS_Clk -- Slave OPB clock
+-- SOPB_Rst -- Slave OPB bus reset
+-- SOPB_ABus -- Slave OPB address bus
+-- SOPB_BE -- Slave OPB error acknowledge
+-- SOPB_DBus -- Slave OPB data bus
+-- SOPB_RNW -- Slave OPB timeout
+-- SOPB_select -- Slave OPB select
+-- SOPB_seqAddr -- Slave OPB sequential address
+-- Sl_DBus -- Slave OPB data bus
+-- Sl_errAck -- Slave OPB error acknowledge
+-- Sl_retry -- Slave OPB retry
+-- Sl_toutSup -- Slave OPB timeout supression
+-- Sl_xferAck -- Slave OPB xferack
+--
+--
+-- USB_IFCLK -- FX2 IF clock (48MHz)
+-- USB_SLRD -- read from FX2 fifo en (not used)
+-- USB_SLWR -- write to FX2 fifo en
+-- USB_FLAGA -- FX2 fifo status programable full flag
+-- USB_FLAGB -- FX2 fifo status full flag
+-- USB_FLAGC -- FX2 fifo status empty flag
+-- USB_PA_T -- FX2 port A tristate toggle (1= FPGA read)
+-- USB_PA_O -- FX2 port A output
+-- USB_PA_I -- FX2 port A input
+-- USB_FD_T -- FX2 Data port tristate toggle (1= FPGA read)
+-- USB_FD_O -- FX2 Data port output
+-- USB_FD_I -- FX2 Data port input
+--
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Libraries
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library unisim;
+use unisim.vcomponents.all;
+
+Library XilinxCoreLib;
+
+library proc_common_v3_00_a;
+use proc_common_v3_00_a.proc_common_pkg.all;
+library xps_fx2_v1_50_b;
+use xps_fx2_v1_50_b.fx2_engine;
+
+-------------------------------------------------------------------------------
+-- Entity section
+-------------------------------------------------------------------------------
+
+entity fx2_core is
+ generic (
+ C_TX_FIFO_KBYTE : integer := 32;
+ C_RX_FIFO_KBYTE : integer := 0;
+ C_USE_ADDR_FIFO : integer := 0;
+ C_TX_RDY_ALMOST_FULL : integer := 1;
+ C_TX_FIFO_CLK_180 : integer := 0;
+ C_USE_CRITICAL : integer := 0
+ );
+ port (
+ SYS_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+
+ Reg_in_0 : in std_logic_vector(0 to 31);
+ Reg_in_1 : in std_logic_vector(0 to 31);
+ Reg_out_0 : out std_logic_vector(0 to 31);
+
+ Interrupt : out std_logic_VECTOR(0 to 7);
+ USB_RX_CLK : in std_logic;
+ USB_IFCLK : in std_logic;
+ USB_SLRD : out std_logic;
+ USB_SLWR : out std_logic;
+ USB_FLAGA : in std_logic;
+ USB_FLAGB : in std_logic;
+ USB_FLAGC : in std_logic;
+ USB_FLAGD : in std_logic;
+ USB_SLOE : out std_logic;
+ USB_PKTEND : out std_logic;
+ USB_FIFOADR : out std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
+ USB_FD_T : out std_logic_vector(7 downto 0) := (others => '1');
+ USB_FD_O : out std_logic_vector(7 downto 0) := (others => '0');
+ USB_FD_I : in std_logic_vector(7 downto 0);
+
+ TX_FIFO_Clk : in std_logic := '0';
+ RX_FIFO_Clk : in std_logic := '0';
+
+ TX_FIFO_DIN : in std_logic_vector(0 to 31) := (others => '0');
+ TX_FIFO_VLD : in std_logic := '0';
+ TX_FIFO_RDY : out std_logic := '0';
+
+ RX_FIFO_DOUT : out std_logic_vector(0 to 31) := (others => '0');
+ RX_FIFO_VLD : out std_logic := '0';
+ RX_FIFO_RDY : in std_logic := '0';
+
+ ChipScope : out std_logic_vector(0 to 31) := (others => '0')
+ );
+
+end entity fx2_core;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture IMP of fx2_core is
+
+-------------------------------------------------------------------------------
+-- Constant Declarations
+-------------------------------------------------------------------------------
+constant TX_FIFO_COUNT_BITS : integer := 8 + log2(C_TX_FIFO_KBYTE);
+constant RX_FIFO_COUNT_BITS : integer := 9 + log2(C_RX_FIFO_KBYTE);
+------------------------------------------
+-- Component declaration
+------------------------------------------
+
+component tx_fifo
+ port (
+ din: IN std_logic_VECTOR(31 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ --almost_full: OUT std_logic; -- In repository but not in reference
+ overflow: OUT std_logic;
+ valid: OUT std_logic;
+ underflow: OUT std_logic;
+ wr_data_count: OUT std_logic_VECTOR(TX_FIFO_COUNT_BITS-1 downto 0));
+end component;
+
+component tx_addr_fifo IS
+ port (
+ din: IN std_logic_VECTOR(1 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(1 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+end component;
+
+component rx_fifo
+ port (
+ din: IN std_logic_VECTOR(7 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ almost_full: OUT std_logic;
+ dout: OUT std_logic_VECTOR(31 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ overflow: OUT std_logic;
+ valid: OUT std_logic;
+ rd_data_count: OUT std_logic_VECTOR(RX_FIFO_COUNT_BITS-1 downto 0);
+ underflow: OUT std_logic);
+end component;
+
+component fx2_engine is
+ generic (
+ TX_FIFO_COUNT_BITS : integer := 13;
+ RX_FIFO_COUNT_BITS : integer := 9;
+ C_TX_FIFO_KBYTE : integer := 32;
+ C_RX_FIFO_KBYTE : integer := 0;
+ C_USE_ADDR_FIFO : integer := 0;
+ C_TX_RDY_ALMOST_FULL : integer := 1;
+ C_TX_FIFO_CLK_180 : integer := 0
+ --C_USE_CRITICAL : integer := 0
+ );
+ port (
+ SYS_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+
+ Reg_in_0 : in std_logic_vector(0 to 31);
+ Reg_in_1 : in std_logic_vector(0 to 31);
+ Reg_out_0 : out std_logic_vector(0 to 31);
+
+ Interrupt : out std_logic_VECTOR(0 to 7);
+
+ USB_RX_CLK : in std_logic;
+ USB_IFCLK : in std_logic;
+ USB_SLRD : out std_logic;
+ USB_SLWR : out std_logic;
+ USB_FLAGA : in std_logic; -- Not used
+ USB_FLAGB : in std_logic;
+ USB_FLAGC : in std_logic;
+ USB_FLAGD : in std_logic;
+ USB_SLOE : out std_logic;
+ USB_PKTEND : out std_logic;
+ USB_FIFOADR : out std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
+ USB_FD_T : out std_logic_vector(7 downto 0) := (others => '1'); --OE active low
+ USB_FD_O : out std_logic_vector(7 downto 0) := (others => '0');
+ USB_FD_I : in std_logic_vector(7 downto 0);
+
+ tx_fifo_rd : out std_logic;
+ tx_fifo_data : in std_logic_vector(7 downto 0);
+ tx_fifo_reset : out std_logic;
+ tx_fifo_full : in std_logic;
+ tx_fifo_empty : in std_logic;
+ tx_fifo_overflow : in std_logic;
+ tx_fifo_count : in std_logic_vector(TX_FIFO_COUNT_BITS-1 downto 0);
+ tx_fifo_valid : in std_logic;
+
+ tx_fifo_rdy : out std_logic;
+
+ tx_addr_fifo_rd : out std_logic;
+ tx_addr_fifo_data : in std_logic_vector(1 downto 0);
+ tx_addr_fifo_reset : out std_logic;
+
+ rx_fifo_wr : out std_logic;
+ rx_fifo_data : out std_logic_vector(7 downto 0);
+ rx_fifo_reset : out std_logic;
+ rx_fifo_full : in std_logic;
+ rx_fifo_empty : in std_logic;
+ rx_fifo_almostfull : in std_logic;
+ rx_fifo_underflow : in std_logic;
+ rx_fifo_count : in std_logic_vector(RX_FIFO_COUNT_BITS-1 downto 0);
+
+ ChipScope : out std_logic_vector(0 to 31) := (others => '0')
+ );
+end component;
+
+------------------------------------------
+-- Signals declaration
+------------------------------------------
+signal tx_fifo_rd : std_logic;
+signal tx_fifo_data : std_logic_vector(7 downto 0);
+signal tx_fifo_reset : std_logic;
+signal tx_fifo_full : std_logic;
+signal tx_fifo_empty : std_logic;
+signal tx_fifo_overflow : std_logic;
+signal tx_fifo_count : std_logic_vector(TX_FIFO_COUNT_BITS-1 downto 0);
+signal tx_fifo_valid : std_logic;
+
+signal tx_addr_fifo_rd : std_logic;
+signal tx_addr_fifo_data : std_logic_vector(1 downto 0);
+signal tx_addr_fifo_reset : std_logic;
+
+signal rx_fifo_wr : std_logic;
+signal rx_fifo_data : std_logic_vector(7 downto 0);
+signal rx_fifo_reset : std_logic;
+signal rx_fifo_full : std_logic;
+signal rx_fifo_empty : std_logic;
+signal rx_fifo_almostfull : std_logic;
+signal rx_fifo_underflow : std_logic;
+signal rx_fifo_count : std_logic_vector(RX_FIFO_COUNT_BITS-1 downto 0);
+
+-- Blackbox attr: tx_fifo rx_fifo tx_addr_fifo
+attribute BOX_TYPE : string;
+attribute BOX_TYPE of tx_fifo : component is "BLACK_BOX";
+
+------------------------------------------
+-- Implementation
+------------------------------------------
+begin
+------------------------------------------
+-- Signal connections
+------------------------------------------
+
+--------------------------------------------
+---- Port Maps
+--------------------------------------------
+fx2_eng: fx2_engine
+ generic map(
+ TX_FIFO_COUNT_BITS => TX_FIFO_COUNT_BITS,
+ RX_FIFO_COUNT_BITS => RX_FIFO_COUNT_BITS,
+ C_TX_FIFO_KBYTE => C_TX_FIFO_KBYTE,
+ C_RX_FIFO_KBYTE => C_RX_FIFO_KBYTE,
+ C_USE_ADDR_FIFO => C_USE_ADDR_FIFO,
+ C_TX_RDY_ALMOST_FULL => C_TX_RDY_ALMOST_FULL,
+ C_TX_FIFO_CLK_180 => C_TX_FIFO_CLK_180
+ --C_USE_CRITICAL => C_USE_CRITICAL
+ )
+ port map(
+ SYS_Clk => SYS_Clk,
+ SYS_Rst => SYS_Rst,
+
+ Reg_in_0 => Reg_in_0,
+ Reg_in_1 => Reg_in_1,
+ Reg_out_0 => Reg_out_0,
+
+ Interrupt => Interrupt,
+ USB_RX_CLK => USB_RX_CLK,
+ USB_IFCLK => USB_IFCLK,
+ USB_SLRD => USB_SLRD,
+ USB_SLWR => USB_SLWR,
+ USB_FLAGA => USB_FLAGA,
+ USB_FLAGB => USB_FLAGB,
+ USB_FLAGC => USB_FLAGC,
+ USB_FLAGD => USB_FLAGD,
+ USB_SLOE => USB_SLOE,
+ USB_PKTEND => USB_PKTEND,
+ USB_FIFOADR => USB_FIFOADR,
+ USB_FD_T => USB_FD_T,
+ USB_FD_O => USB_FD_O,
+ USB_FD_I => USB_FD_I,
+
+ tx_fifo_rd => tx_fifo_rd,
+ tx_fifo_data => tx_fifo_data,
+ tx_fifo_reset => tx_fifo_reset,
+ tx_fifo_full => tx_fifo_full,
+ tx_fifo_empty => tx_fifo_empty,
+ tx_fifo_overflow => tx_fifo_overflow,
+ tx_fifo_count => tx_fifo_count,
+ tx_fifo_rdy => TX_FIFO_RDY,
+ tx_fifo_valid => tx_fifo_valid,
+
+ tx_addr_fifo_rd => tx_addr_fifo_rd,
+ tx_addr_fifo_data => tx_addr_fifo_data,
+ tx_addr_fifo_reset => tx_addr_fifo_reset,
+
+ rx_fifo_wr => rx_fifo_wr,
+ rx_fifo_data => rx_fifo_data,
+ rx_fifo_reset => rx_fifo_reset,
+ rx_fifo_full => rx_fifo_full,
+ rx_fifo_empty => rx_fifo_empty,
+ rx_fifo_almostfull => rx_fifo_almostfull,
+ rx_fifo_underflow => rx_fifo_underflow,
+ rx_fifo_count => rx_fifo_count,
+
+ ChipScope => ChipScope
+ );
+
+
+TX_FIFI : tx_fifo
+ port map(
+ din => TX_FIFO_DIN,
+ rd_clk => USB_IFCLK,
+ rd_en => tx_fifo_rd,
+ rst => tx_fifo_reset,
+ wr_clk => TX_FIFO_Clk,
+ wr_en => TX_FIFO_VLD,
+ dout => tx_fifo_data,
+ empty => tx_fifo_empty,
+ full => tx_fifo_full,
+ overflow => tx_fifo_overflow,
+ valid => tx_fifo_valid,
+ underflow => open,
+ wr_data_count => tx_fifo_count
+ );
+
+--REG_FIFOADR <= Reg_in_0(26 to 27); --signal to select EP addr
+
+TX_FIFI_ADDR_GEN :
+if C_USE_ADDR_FIFO=1
+generate
+ begin
+ TX_FIFI_ADDR : tx_addr_fifo
+ port map (
+ din => Reg_in_0(26 to 27),
+ rd_clk => USB_IFCLK,
+ rd_en => tx_addr_fifo_rd,
+ rst => tx_addr_fifo_reset,
+ wr_clk => TX_FIFO_Clk,
+ wr_en => TX_FIFO_VLD,
+ dout => tx_addr_fifo_data,
+ empty => open,
+ full => open
+ );
+end generate;
+
+RX_FIFO_GEN :
+if C_RX_FIFO_KBYTE>0
+generate
+ begin
+ RX_FIFI : rx_fifo
+ port map (
+ din => rx_fifo_data,
+ rd_clk => RX_FIFO_Clk,
+ rd_en => RX_FIFO_RDY,
+ rst => rx_fifo_reset,
+ wr_clk => USB_IFCLK,
+ wr_en => rx_fifo_wr,
+ almost_full => rx_fifo_almostfull,
+ dout => RX_FIFO_DOUT,
+ empty => rx_fifo_empty,
+ full => rx_fifo_full,
+ overflow => open,
+ valid => RX_FIFO_VLD,
+ rd_data_count => rx_fifo_count,
+ underflow => rx_fifo_underflow
+ );
+end generate;
+--------------------------------------------
+
+end IMP;
View
408 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/hdl/vhdl/fx2_engine.vhd
@@ -0,0 +1,408 @@
+-- "r" test always failed
+-- "w" test 20.8 MB/s
+----------------------------------------------------------------------------------
+-- Company: Trenz Electronic GmbH
+-- Engineer: Alexander Kinko
+--
+-- Create Date: 20:29:43 08/25/2011
+-- Design Name:
+-- Module Name: fx2_engine - Behavioral
+-- Project Name: FX2 core
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Port Declaration
+-------------------------------------------------------------------------------
+-- USB_IFCLK -- FX2 IF clock (48MHz)
+-- USB_SLRD -- read from FX2 fifo en
+-- USB_SLWR -- write to FX2 fifo en
+-- USB_FLAGA -- FX2 fifo status programable full flag
+-- USB_FLAGB -- FX2 fifo status full flag
+-- USB_FLAGC -- FX2 fifo status empty flag
+-- USB_PA_T -- FX2 port A tristate toggle (1= FPGA read)
+-- USB_PA_O -- FX2 port A output
+-- USB_PA_I -- FX2 port A input
+-- USB_FD_T -- FX2 Data port tristate toggle (1= FPGA read)
+-- USB_FD_O -- FX2 Data port output
+-- USB_FD_I -- FX2 Data port input
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Libraries
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+-------------------------------------------------------------------------------
+-- Entity section
+-------------------------------------------------------------------------------
+entity fx2_engine is
+ generic (
+ TX_FIFO_COUNT_BITS : integer := 13;
+ RX_FIFO_COUNT_BITS : integer := 9;
+ C_TX_FIFO_KBYTE : integer := 32;
+ C_RX_FIFO_KBYTE : integer := 0;
+ C_USE_ADDR_FIFO : integer := 0;
+ C_TX_RDY_ALMOST_FULL : integer := 1;
+ C_TX_FIFO_CLK_180 : integer := 0;
+ C_USE_CRITICAL : integer := 0
+ );
+ port (
+ SYS_Clk : in std_logic;
+ SYS_Rst : in std_logic;
+
+ Reg_in_0 : in std_logic_vector(0 to 31);
+ Reg_in_1 : in std_logic_vector(0 to 31);
+ Reg_out_0 : out std_logic_vector(0 to 31);
+
+ Interrupt : out std_logic_VECTOR(0 to 7);
+
+ USB_IFCLK : in std_logic;
+ USB_RX_CLK : in std_logic;
+ USB_SLRD : out std_logic;
+ USB_SLWR : out std_logic;
+ USB_FLAGA : in std_logic; -- Not used
+ USB_FLAGB : in std_logic;
+ USB_FLAGC : in std_logic;
+ USB_FLAGD : in std_logic;
+ USB_SLOE : out std_logic;
+ USB_PKTEND : out std_logic;
+ USB_FIFOADR : out std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
+ USB_FD_T : out std_logic_vector(7 downto 0) := (others => '1');
+ USB_FD_O : out std_logic_vector(7 downto 0) := (others => '0');
+ USB_FD_I : in std_logic_vector(7 downto 0);
+
+ tx_fifo_rd : out std_logic;
+ tx_fifo_data : in std_logic_vector(7 downto 0);
+ tx_fifo_reset : out std_logic;
+ tx_fifo_full : in std_logic;
+ tx_fifo_empty : in std_logic;
+ tx_fifo_overflow : in std_logic;
+ tx_fifo_count : in std_logic_vector(TX_FIFO_COUNT_BITS-1 downto 0);
+ tx_fifo_valid : in std_logic;
+
+ tx_fifo_rdy : out std_logic;
+
+ tx_addr_fifo_rd : out std_logic;
+ tx_addr_fifo_data : in std_logic_vector(1 downto 0);
+ tx_addr_fifo_reset : out std_logic;
+
+ rx_fifo_wr : out std_logic;
+ rx_fifo_data : out std_logic_vector(7 downto 0);
+ rx_fifo_reset : out std_logic;
+ rx_fifo_full : in std_logic;
+ rx_fifo_empty : in std_logic;
+ rx_fifo_almostfull : in std_logic;
+ rx_fifo_underflow : in std_logic;
+ rx_fifo_count : in std_logic_vector(RX_FIFO_COUNT_BITS-1 downto 0);
+
+ ChipScope : out std_logic_vector(0 to 31) := (others => '0')
+ );
+end entity fx2_engine;
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+architecture rtl of fx2_engine is
+-------------------------------------------------------------------------------
+-- Constant Declarations
+-------------------------------------------------------------------------------
+constant C_USB_SLOE_ENABLE_LEVEL : std_logic := '1';
+constant C_USB_SLOE_DISABLE_LEVEL : std_logic := '0';
+constant C_USB_SLRD_ACTIVE : std_logic := '1';
+constant C_USB_SLRD_PASSIVE : std_logic := '0';
+constant C_USB_SLWR_ACTIVE : std_logic := '1';
+constant C_USB_SLWR_PASSIVE : std_logic := '0';
+
+------------------------------------------
+-- Signals declaration
+------------------------------------------
+-- Registers for all input signals
+signal usb_tx_empty : std_logic; -- FX2 transmit fifo empty
+signal usb_tx_full : std_logic; -- FX2 transmit fifo full
+signal usb_rx_empty : std_logic; -- FX2 receive fifo empty
+signal fd_i_reg : std_logic_vector(7 downto 0);
+
+-- Drivers for outputs
+signal fd_o_drv : std_logic_vector(7 downto 0) := (others => '0');
+signal fd_t_drv : std_logic_vector(7 downto 0) := (others => '1');
+signal slrd_drv : std_logic;
+signal slwr_drv : std_logic;
+signal sloe_drv : std_logic;
+signal pktend_drv : std_logic;
+signal fifoaddr_drv : std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
+
+-- FSM
+type wr_state_type is (
+ STATE_WR_INIT,
+ STATE_WR,
+ STATE_WR_REM,
+ STATE_READ_1,
+ STATE_READ_2
+);
+signal wr_fsm_state : wr_state_type;
+
+signal addr_fifo_rd_cnt : std_logic_vector(1 downto 0);
+
+ -- Others
+signal tx_fifo_rst : std_logic := '0';
+signal rx_fifo_rst : std_logic := '0';
+signal TX_FIFO_RDY_reg : std_logic := '0';
+signal REG_FIFOADR : std_logic_vector(1 downto 0) := "10";
+signal tx_fifo_threshold : std_logic_VECTOR(TX_FIFO_COUNT_BITS-1 downto 0);
+signal rx_fifo_threshold : std_logic_VECTOR(RX_FIFO_COUNT_BITS-1 downto 0);
+signal rx_fifo_prog_full : std_logic := '0';
+signal tx_fifo_prog_empty : std_logic := '0';
+signal tx_fifo_reset_drv : std_logic;
+signal rx_fifo_reset_drv : std_logic;
+signal tx_fifo_read_req : std_logic;
+signal read_fsm_enable : std_logic;
+signal fd_t_bit : std_logic;
+signal last_write : std_logic;
+attribute box_type : string;
+attribute iob : string;
+------------------------------------------
+-- Implementation
+------------------------------------------
+begin
+------------------------------------------
+-- Register slicing
+------------------------------------------
+ tx_fifo_rst <= Reg_in_0(31); --signal to reset fifo
+ rx_fifo_rst <= Reg_in_0(30); --signal to reset fifo
+ TX_FIFO_RDY_reg <= not Reg_in_0(29); --signal to disable external fifo port
+ REG_FIFOADR <= Reg_in_0(26 to 27); --signal to select EP addr
+ tx_fifo_threshold(TX_FIFO_COUNT_BITS-1 downto 0) <= Reg_in_1(32-TX_FIFO_COUNT_BITS to 31); --signal to set fifo threshold
+ rx_fifo_threshold(RX_FIFO_COUNT_BITS-1 downto 0) <= Reg_in_1(16-RX_FIFO_COUNT_BITS to 15); --signal to set fifo threshold
+ Reg_out_0(32-TX_FIFO_COUNT_BITS to 31) <= tx_fifo_count(TX_FIFO_COUNT_BITS-1 downto 0);
+ --Reg_out_0(19) <= tx_fifo_prog_empty;
+ Reg_out_0(18) <= tx_fifo_overflow;
+ Reg_out_0(17) <= tx_fifo_full;
+ Reg_out_0(16) <= tx_fifo_empty;
+ Reg_out_0(16-RX_FIFO_COUNT_BITS to 15) <= rx_fifo_count(RX_FIFO_COUNT_BITS-1 downto 0);
+ Reg_out_0(3) <= rx_fifo_prog_full;
+ Reg_out_0(2) <= rx_fifo_underflow;
+ Reg_out_0(1) <= rx_fifo_full;
+ Reg_out_0(0) <= rx_fifo_empty;
+------------------------------------------
+ --Chipscope trigger
+ ChipScope <=
+ x"0000_000" &
+ "0" &
+ slwr_drv & -- Write
+ USB_FLAGB & -- USB_TX_FULL
+ USB_FLAGA; -- Unknown
+------------------------------------------
+-- USB Inputs
+------------------------------------------
+process(USB_IFCLK,SYS_Rst)
+begin
+ if(SYS_Rst = '1')then
+ usb_tx_empty <= '1';
+ elsif(USB_IFCLK = '1' and USB_IFCLK'event)then
+ usb_tx_empty <= USB_FLAGC;
+ end if;
+end process;
+usb_rx_empty <= USB_FLAGD;
+usb_tx_full <= USB_FLAGB;
+
+process(USB_RX_CLK)
+begin
+ if(USB_RX_CLK = '1' and USB_RX_CLK'event)then
+ fd_i_reg <= USB_FD_I;
+ end if;
+end process;
+------------------------------------------
+-- USB Outputs
+------------------------------------------
+USB_SLRD <= slrd_drv;
+USB_SLWR <= tx_fifo_valid;
+USB_SLOE <= sloe_drv;
+USB_PKTEND <= pktend_drv;
+USB_FIFOADR <= fifoaddr_drv;
+USB_FD_T <= fd_t_drv;
+USB_FD_O <= fd_o_drv;
+------------------------------------------
+ -- Write FSM
+------------------------------------------
+ process(USB_IFCLK,SYS_Rst)
+ begin
+ if(SYS_Rst = '1')then
+ wr_fsm_state <= STATE_WR_INIT;
+ tx_fifo_read_req <= '0';
+ read_fsm_enable <= '0';
+ rx_fifo_wr <= '0';
+ rx_fifo_data <= (others => '0');
+ last_write <= '0';
+ elsif(USB_IFCLK = '1' and USB_IFCLK'event)then
+ case wr_fsm_state is
+ when STATE_WR_INIT =>
+ rx_fifo_wr <= '0'; -- stop write
+ sloe_drv <= C_USB_SLOE_DISABLE_LEVEL;
+ slwr_drv <= C_USB_SLWR_PASSIVE;
+ last_write <= '0';
+ if(usb_rx_empty = '0')then
+ sloe_drv <= C_USB_SLOE_ENABLE_LEVEL;
+ read_fsm_enable <= '1';
+ wr_fsm_state <= STATE_READ_1; -- V7
+ elsif(tx_fifo_empty = '0' and usb_tx_full = '0')then
+ sloe_drv <= C_USB_SLOE_DISABLE_LEVEL;
+ tx_fifo_read_req <= '1';
+ read_fsm_enable <= '0';
+ wr_fsm_state <= STATE_WR;
+ end if;
+
+ when STATE_WR =>
+ sloe_drv <= C_USB_SLOE_DISABLE_LEVEL;
+ if(tx_fifo_empty = '1')then
+ tx_fifo_read_req <= '0';
+ slwr_drv <= C_USB_SLWR_PASSIVE;
+ last_write <= '1';
+ wr_fsm_state <= STATE_WR_INIT;
+ elsif(usb_tx_full = '1' or usb_rx_empty = '0')then
+ tx_fifo_read_req <= '0';
+ slwr_drv <= C_USB_SLWR_PASSIVE;
+ wr_fsm_state <= STATE_WR_REM;
+ else
+ tx_fifo_read_req <= '1';
+ slwr_drv <= C_USB_SLWR_ACTIVE;
+ end if;
+
+ when STATE_WR_REM =>
+ sloe_drv <= C_USB_SLOE_DISABLE_LEVEL;
+ slwr_drv <= C_USB_SLWR_PASSIVE;
+ if(usb_tx_full = '0')then
+ wr_fsm_state <= STATE_WR;
+ end if;
+
+ when STATE_READ_1 =>
+ rx_fifo_wr <= '0'; -- stop write
+ wr_fsm_state <= STATE_READ_2;
+
+ when STATE_READ_2 =>
+ rx_fifo_data <= fd_i_reg;
+ rx_fifo_wr <= '1'; -- Write result
+ if(usb_rx_empty = '0' -- We have something to read
+ and rx_fifo_almostfull = '0' -- and have room in FIFO
+ )then -- Go to next read cycle
+ sloe_drv <= C_USB_SLOE_ENABLE_LEVEL; -- Drive OE
+ wr_fsm_state <= STATE_READ_1;
+ else
+ sloe_drv <= C_USB_SLOE_DISABLE_LEVEL; -- Disable OE
+ wr_fsm_state <= STATE_WR_INIT;
+ end if;
+
+ when others => null;
+ end case;
+ end if;
+ end process;
+
+process(USB_IFCLK)
+begin
+ if(USB_IFCLK = '1' and USB_IFCLK'event)then
+ pktend_drv <= last_write;
+ end if;
+end process;
+
+fd_t_bit <= '0' when (wr_fsm_state = STATE_WR) or (wr_fsm_state = STATE_WR_REM) else '1';
+
+t_drv_gen: for j in 0 to 7 generate
+attribute iob of FDCE_inst : label is "true";
+attribute box_type of FDCE_inst : label is "black_box";
+begin
+ FDCE_inst : FDCE
+ generic map (
+ INIT => '1'
+ )
+ port map (
+ Q => fd_t_drv(j),
+ C => USB_IFCLK,
+ CE => '1',
+ CLR => '0',
+ D => fd_t_bit
+ );
+end generate;
+
+process(USB_IFCLK)
+begin
+ if(USB_IFCLK = '1' and USB_IFCLK'event)then
+ if((wr_fsm_state = STATE_WR_INIT or wr_fsm_state = STATE_READ_2) and usb_rx_empty = '0' and rx_fifo_almostfull = '0')then
+ slrd_drv <= C_USB_SLRD_ACTIVE; -- Start Read
+ else
+ slrd_drv <= C_USB_SLRD_PASSIVE;
+ end if;
+ end if;
+end process;
+------------------------------------------
+-- FIFOs
+------------------------------------------
+tx_fifo_reset_drv <= SYS_Rst or tx_fifo_rst;
+rx_fifo_reset_drv <= SYS_Rst or rx_fifo_rst;
+tx_fifo_reset <= tx_fifo_reset_drv;
+rx_fifo_reset <= rx_fifo_reset_drv;
+tx_addr_fifo_reset <= tx_fifo_reset_drv;
+fd_o_drv <= tx_fifo_data;
+tx_fifo_rd <= '1' when (tx_fifo_empty = '0' and usb_tx_full = '0' and tx_fifo_read_req = '1') else '0';
+tx_addr_fifo_rd <= '1' when (tx_fifo_empty = '0' and usb_tx_full = '0' and tx_fifo_read_req = '1' and addr_fifo_rd_cnt = "00") else '0';
+fifoaddr_drv <= "11" when (read_fsm_enable = '1') else tx_addr_fifo_data when (C_USE_ADDR_FIFO=1) else REG_FIFOADR;
+------------------------------------------
+-- Address FIFO engine
+------------------------------------------
+process(tx_fifo_reset_drv, USB_IFCLK)
+begin
+ if(tx_fifo_reset_drv = '1')then
+ addr_fifo_rd_cnt <= (others => '0');
+ elsif(USB_IFCLK = '1' and USB_IFCLK'event)then
+ if(tx_fifo_empty = '0' and usb_tx_full = '0' and tx_fifo_read_req = '1')then
+ addr_fifo_rd_cnt <= addr_fifo_rd_cnt + 1;
+ end if;
+ end if;
+end process;
+------------------------------------------
+-- INTERRUPT signals connection
+------------------------------------------
+Interrupt <= "0000" & rx_fifo_underflow & tx_fifo_overflow & rx_fifo_prog_full & tx_fifo_prog_empty;
+------------------------------------------
+-- FIFO threshold
+------------------------------------------
+TX_FIFO_PROG_EMPTY_DETECT : process (SYS_Clk)
+begin
+ if (SYS_Clk'event and SYS_Clk = '1') then
+ if (tx_fifo_reset_drv = '1') then --reset
+ tx_fifo_prog_empty <= '1';
+ elsif (tx_fifo_count <= tx_fifo_threshold) then --under threshold
+ tx_fifo_prog_empty <= '1';
+ else
+ tx_fifo_prog_empty <= '0';
+ end if;
+ end if;
+end process;
+
+RX_FIFO_PROG_FULL_DETECT : process (SYS_Clk)
+begin
+ if (SYS_Clk'event and SYS_Clk = '1') then
+ if (tx_fifo_reset_drv = '1') then --reset
+ rx_fifo_prog_full <= '0';
+ elsif (rx_fifo_count >= rx_fifo_threshold) then --over threshold
+ rx_fifo_prog_full <= '1';
+ else
+ rx_fifo_prog_full <= '0';
+ end if;
+ end if;
+end process;
+------------------------------------------
+-- Drive tx_fifo_rdy
+------------------------------------------
+tx_fifo_rdy <= '0' when ((tx_fifo_reset_drv = '1') or (tx_fifo_full = '1')) else TX_FIFO_RDY_reg;
+------------------------------------------
+end rtl;
View
396 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/hdl/vhdl/user_logic.vhd
@@ -0,0 +1,396 @@
+------------------------------------------------------------------------------
+-- user_logic.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+--
+-- ***************************************************************************
+-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
+-- ** **
+-- ** Xilinx, Inc. **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
+-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
+-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
+-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
+-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
+-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
+-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
+-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
+-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
+-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
+-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
+-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
+-- ** FOR A PARTICULAR PURPOSE. **
+-- ** **
+-- ***************************************************************************
+--
+------------------------------------------------------------------------------
+-- Filename: user_logic.vhd
+-- Version: 1.00.a
+-- Description: User logic.
+-- Date: Thu Apr 17 20:27:53 2008 (by Create and Import Peripheral Wizard)
+-- VHDL Standard: VHDL'93
+------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"
+------------------------------------------------------------------------------
+
+-- DO NOT EDIT BELOW THIS LINE --------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library proc_common_v3_00_a;
+use proc_common_v3_00_a.proc_common_pkg.all;
+
+library xps_fx2_v1_50_b;
+use xps_fx2_v1_50_b.all;
+
+-- DO NOT EDIT ABOVE THIS LINE --------------------
+
+--USER libraries added here
+
+------------------------------------------------------------------------------
+-- Entity section
+------------------------------------------------------------------------------
+-- Definition of Generics:
+-- C_SLV_DWIDTH -- Slave interface data bus width
+-- C_NUM_REG -- Number of software accessible registers
+-- C_NUM_INTR -- Number of interrupt event
+--
+-- Definition of Ports:
+-- Bus2IP_Clk -- Bus to IP clock
+-- Bus2IP_Reset -- Bus to IP reset
+-- Bus2IP_Data -- Bus to IP data bus
+-- Bus2IP_BE -- Bus to IP byte enables
+-- Bus2IP_RdCE -- Bus to IP read chip enable
+-- Bus2IP_WrCE -- Bus to IP write chip enable
+-- IP2Bus_Data -- IP to Bus data bus
+-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
+-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
+-- IP2Bus_Error -- IP to Bus error response
+-- IP2Bus_IntrEvent -- IP to Bus interrupt event
+------------------------------------------------------------------------------
+
+entity user_logic is
+ generic
+ (
+ -- ADD USER GENERICS BELOW THIS LINE ---------------
+ --USER generics added here
+ C_TX_FIFO_KBYTE : integer := 32;
+ C_RX_FIFO_KBYTE : integer := 2;
+ C_USE_ADDR_FIFO : integer := 1;
+ C_TX_FIFO_CLK_180 : integer := 0;
+ C_USE_CRITICAL : integer := 0;
+ -- ADD USER GENERICS ABOVE THIS LINE ---------------
+
+ -- DO NOT EDIT BELOW THIS LINE ---------------------
+ -- Bus protocol parameters, do not add to or delete
+ C_SLV_DWIDTH : integer := 32;
+ C_NUM_REG : integer := 5;
+ C_NUM_INTR : integer := 8
+ -- DO NOT EDIT ABOVE THIS LINE ---------------------
+ );
+ port
+ (
+ -- ADD USER PORTS BELOW THIS LINE ------------------
+ --USER ports added here
+ USB_RX_CLK : in std_logic;
+ USB_IFCLK : in std_logic;
+ USB_SLRD : out std_logic;
+ USB_SLWR : out std_logic;
+ USB_FLAGA : in std_logic;
+ USB_FLAGB : in std_logic;
+ USB_FLAGC : in std_logic;
+ USB_FLAGD : in std_logic;
+ USB_SLOE : out std_logic;
+ USB_PKTEND : out std_logic;
+ USB_FIFOADR : out std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
+ USB_FD_T : out std_logic_vector(7 downto 0) := (others => '1');
+ USB_FD_O : out std_logic_vector(7 downto 0) := (others => '0');
+ USB_FD_I : in std_logic_vector(7 downto 0);
+
+ TX_FIFO_Clk : in std_logic := '0';
+ RX_FIFO_Clk : in std_logic := '0';
+
+ TX_FIFO_DIN : in std_logic_vector(0 to 31) := (others => '0');
+ TX_FIFO_VLD : in std_logic := '0';
+ TX_FIFO_RDY : out std_logic := '0';
+
+ RX_FIFO_DOUT : out std_logic_vector(0 to 31) := (others => '0');
+ RX_FIFO_VLD : out std_logic := '0';
+ RX_FIFO_RDY : in std_logic := '0';
+
+ ChipScope : out std_logic_vector(0 to 31) := (others => '0');
+ -- ADD USER PORTS ABOVE THIS LINE ------------------
+
+ -- DO NOT EDIT BELOW THIS LINE ---------------------
+ -- Bus protocol ports, do not add to or delete
+ Bus2IP_Clk : in std_logic;
+ Bus2IP_Reset : in std_logic;
+ Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
+ Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
+ Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
+ Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
+ IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
+ IP2Bus_RdAck : out std_logic;
+ IP2Bus_WrAck : out std_logic;
+ IP2Bus_Error : out std_logic;
+ IP2Bus_IntrEvent : out std_logic_vector(0 to C_NUM_INTR-1)
+ -- DO NOT EDIT ABOVE THIS LINE ---------------------
+ );
+
+ attribute SIGIS : string;
+ attribute SIGIS of Bus2IP_Clk : signal is "CLK";
+ attribute SIGIS of Bus2IP_Reset : signal is "RST";
+
+end entity user_logic;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture IMP of user_logic is
+
+ --USER signal declarations added here, as needed for user logic
+ signal TX_FIFO_DIN_i : std_logic_vector(0 to 31) := (others => '0');
+ signal TX_FIFO_DVALID_ce : std_logic := '0';
+ signal TX_FIFO_DVALID_ce_r0 : std_logic := '0';
+ signal TX_FIFO_DVALID_ce_r1 : std_logic := '0';
+ signal TX_FIFO_VLD_i : std_logic := '0';
+ signal RX_FIFO_DOUT_i : std_logic_vector(0 to 31) := (others => '0');
+ signal RX_FIFO_RDY_i : std_logic := '0';
+ signal RX_FIFO_OUT_EN_ce : std_logic := '0';
+ signal RX_FIFO_OUT_EN_ce_r0 : std_logic := '0';
+ signal RX_FIFO_OUT_EN_ce_r1 : std_logic := '0';
+ signal RX_FIFO_OUT_EN_ack : std_logic := '0';
+ ------------------------------------------
+ -- Signals for user logic slave model s/w accessible register example
+ ------------------------------------------
+ signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
+ signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
+ signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
+ signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
+ signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
+ signal slv_reg_write_sel : std_logic_vector(0 to 4);
+ signal slv_reg_read_sel : std_logic_vector(0 to 4);
+ signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
+ signal slv_read_ack : std_logic;
+ signal slv_write_ack : std_logic;
+
+ ------------------------------------------
+ -- Signals for user logic interrupt example
+ ------------------------------------------
+ signal intr_counter : std_logic_vector(0 to C_NUM_INTR-1);
+
+begin
+
+ ------------------------------------------
+ -- Example code to read/write user logic slave model s/w accessible registers
+ --
+ -- Note:
+ -- The example code presented here is to show you one way of reading/writing
+ -- software accessible registers implemented in the user logic slave model.
+ -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
+ -- to one software accessible register by the top level template. For example,
+ -- if you have four 32 bit software accessible registers in the user logic,
+ -- you are basically operating on the following memory mapped registers:
+ --
+ -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
+ -- "1000" C_BASEADDR + 0x0
+ -- "0100" C_BASEADDR + 0x4
+ -- "0010" C_BASEADDR + 0x8
+ -- "0001" C_BASEADDR + 0xC
+ --
+ ------------------------------------------
+ slv_reg_write_sel <= Bus2IP_WrCE(0 to 4);
+ slv_reg_read_sel <= Bus2IP_RdCE(0 to 4);
+ slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
+ slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);
+
+ -- implement slave model software accessible register(s)
+ SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
+ begin
+
+ if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
+ TX_FIFO_DVALID_ce <= '0'; --user
+ if Bus2IP_Reset = '1' then
+ slv_reg0 <= (others => '0');
+ slv_reg1 <= (others => '0');
+-- slv_reg2 <= (others => '0');
+ slv_reg3 <= (others => '0');
+-- slv_reg4 <= (others => '0');
+ else
+ case slv_reg_write_sel is
+ when "10000" =>
+ for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
+ if ( Bus2IP_BE(byte_index) = '1' ) then
+ slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
+ end if;
+ end loop;
+ when "01000" =>
+ for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
+ if ( Bus2IP_BE(byte_index) = '1' ) then
+ slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
+ end if;
+ end loop;
+ when "00100" =>
+-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
+-- if ( Bus2IP_BE(byte_index) = '1' ) then
+-- slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
+-- end if;
+-- end loop;
+ when "00010" =>
+ TX_FIFO_DVALID_ce <= '1'; --user writes fifo
+ for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
+ if ( Bus2IP_BE(byte_index) = '1' ) then
+ slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
+ end if;
+ end loop;
+ when "00001" =>
+-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
+-- if ( Bus2IP_BE(byte_index) = '1' ) then
+-- slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
+-- end if;
+-- end loop;
+ when others => null;
+ end case;
+ end if;
+ end if;
+
+ end process SLAVE_REG_WRITE_PROC;
+
+ -- implement slave model software accessible register(s) read mux
+ SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4 ) is
+ begin
+ RX_FIFO_OUT_EN_ce <= '0'; --user
+ case slv_reg_read_sel is
+ when "10000" => slv_ip2bus_data <= slv_reg0;
+ when "01000" => slv_ip2bus_data <= slv_reg1;
+ when "00100" => slv_ip2bus_data <= slv_reg2;
+ when "00010" => slv_ip2bus_data <= slv_reg3;
+ when "00001" =>
+ RX_FIFO_OUT_EN_ce <= '1'; --user
+ slv_ip2bus_data <= slv_reg4;
+ when others => slv_ip2bus_data <= (others => '0');
+ end case;
+
+ end process SLAVE_REG_READ_PROC;
+
+ ------------------------------------------
+ -- Example code to drive IP to Bus signals
+ ------------------------------------------
+ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
+ (others => '0');
+
+ IP2Bus_WrAck <= slv_write_ack;
+ IP2Bus_RdAck <= slv_read_ack;
+ IP2Bus_Error <= '0';
+
+
+ --USER logic implementation added here
+
+ slv_reg4 <= RX_FIFO_DOUT_i;
+ RX_FIFO_DOUT <= RX_FIFO_DOUT_i;
+ RX_FIFO_RDY_i <= RX_FIFO_RDY or RX_FIFO_OUT_EN_ack;
+ ------------------------------------------
+ -- Rising edge detect
+ ------------------------------------------
+ RX_FIFO_CLK_REGISTERS : process(RX_FIFO_Clk)
+ begin
+ if rising_edge(RX_FIFO_Clk) then
+ RX_FIFO_OUT_EN_ce_r0 <= RX_FIFO_OUT_EN_ce;
+ RX_FIFO_OUT_EN_ce_r1 <= RX_FIFO_OUT_EN_ce_r0;
+ if (RX_FIFO_OUT_EN_ce_r1 < RX_FIFO_OUT_EN_ce_r0) then --rising edge
+ RX_FIFO_OUT_EN_ack <= '1';
+ else
+ RX_FIFO_OUT_EN_ack <= '0';
+ end if;
+ end if;
+ end process RX_FIFO_CLK_REGISTERS;
+
+ TX_FIFO_CLK_REGISTERS : process(TX_FIFO_Clk)
+ begin
+ if rising_edge(TX_FIFO_Clk) then
+ TX_FIFO_DVALID_ce_r0 <= TX_FIFO_DVALID_ce;
+ TX_FIFO_DVALID_ce_r1 <= TX_FIFO_DVALID_ce_r0;
+
+ if (TX_FIFO_DVALID_ce_r1 < TX_FIFO_DVALID_ce_r0) then --rising edge
+ --write from register
+ TX_FIFO_VLD_i <= '1';
+ TX_FIFO_DIN_i <= slv_reg3;
+ elsif (TX_FIFO_VLD = '1') then
+ --write from TX_FIFO port
+ TX_FIFO_VLD_i <= '1';
+ TX_FIFO_DIN_i <= TX_FIFO_DIN;
+ else --idle
+ TX_FIFO_VLD_i <= '0';
+ end if;
+ end if;
+ end process TX_FIFO_CLK_REGISTERS;
+
+ ------------------------------------------
+ -- Component instantiations
+ ------------------------------------------
+ CORE_IMPLEMENTATION : entity xps_fx2_v1_50_b.fx2_core
+ generic map(
+ C_TX_FIFO_KBYTE => C_TX_FIFO_KBYTE,
+ C_RX_FIFO_KBYTE => C_RX_FIFO_KBYTE,
+ C_USE_ADDR_FIFO => C_USE_ADDR_FIFO,
+ C_TX_FIFO_CLK_180 => C_TX_FIFO_CLK_180,
+ C_USE_CRITICAL => C_USE_CRITICAL
+ )
+ Port map(
+ SYS_Clk => Bus2IP_Clk,
+ SYS_Rst => Bus2IP_Reset,
+
+ Reg_in_0 => slv_reg0,
+ Reg_in_1 => slv_reg1,
+ Reg_out_0 => slv_reg2,
+
+ Interrupt => IP2Bus_IntrEvent,
+ USB_RX_CLK => USB_RX_CLK,
+ USB_IFCLK => USB_IFCLK,
+ USB_SLRD => USB_SLRD,
+ USB_SLWR => USB_SLWR,
+ USB_FLAGA => USB_FLAGA,
+ USB_FLAGB => USB_FLAGB,
+ USB_FLAGC => USB_FLAGC,
+ USB_FLAGD => USB_FLAGD,
+ USB_SLOE => USB_SLOE,
+ USB_PKTEND => USB_PKTEND,
+ USB_FIFOADR => USB_FIFOADR,
+ USB_FD_T => USB_FD_T,
+ USB_FD_O => USB_FD_O,
+ USB_FD_I => USB_FD_I,
+
+ TX_FIFO_Clk => TX_FIFO_Clk,
+ RX_FIFO_Clk => RX_FIFO_Clk,
+
+ TX_FIFO_DIN => TX_FIFO_DIN_i,
+ TX_FIFO_VLD => TX_FIFO_VLD_i,
+ TX_FIFO_RDY => TX_FIFO_RDY,
+
+ RX_FIFO_DOUT => RX_FIFO_DOUT_i,
+ RX_FIFO_VLD => RX_FIFO_VLD,
+ RX_FIFO_RDY => RX_FIFO_RDY_i,
+
+ ChipScope => ChipScope
+
+);
+
+end IMP;
View
636 MyProcessorIPLib/pcores/xps_fx2_v1_50_b/hdl/vhdl/xps_fx2.vhd
<
@@ -0,0 +1,636 @@
+------------------------------------------------------------------------------
+-- xps_fx2.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+-- IMPORTANT:
+-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
+--
+-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
+--
+-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
+-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
+-- OF THE USER_LOGIC ENTITY.
+------------------------------------------------------------------------------
+--
+-- ***************************************************************************
+-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
+-- ** **
+-- ** Xilinx, Inc. **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
+-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
+-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
+-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
+-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
+-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
+-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
+-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
+-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
+-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
+-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
+-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
+-- ** FOR A PARTICULAR PURPOSE. **
+-- ** **
+-- ***************************************************************************
+--
+------------------------------------------------------------------------------
+-- Filename: xps_fx2.vhd
+-- Version: 1.00.a
+-- Description: Top level design, instantiates library components and user logic.
+-- Date: Thu Apr 17 20:27:53 2008 (by Create and Import Peripheral Wizard)
+-- VHDL Standard: VHDL'93
+------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library proc_common_v3_00_a;
+use proc_common_v3_00_a.proc_common_pkg.all;
+use proc_common_v3_00_a.ipif_pkg.all;
+use proc_common_v3_00_a.soft_reset;
+
+library interrupt_control_v2_01_a;
+use interrupt_control_v2_01_a.interrupt_control;
+
+library plbv46_slave_single_v1_01_a;
+use plbv46_slave_single_v1_01_a.plbv46_slave_single;
+
+library xps_fx2_v1_50_b;
+use xps_fx2_v1_50_b.user_logic;
+
+------------------------------------------------------------------------------
+-- Entity section
+------------------------------------------------------------------------------
+-- Definition of Generics:
+-- C_BASEADDR -- PLBv46 slave: base address
+-- C_HIGHADDR -- PLBv46 slave: high address
+-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
+-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
+-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
+-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
+-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
+-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
+-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
+-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
+-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
+-- C_FAMILY -- Xilinx FPGA family
+--
+-- Definition of Ports:
+-- SPLB_Clk -- PLB main bus clock
+-- SPLB_Rst -- PLB main bus reset
+-- PLB_ABus -- PLB address bus
+-- PLB_UABus -- PLB upper address bus
+-- PLB_PAValid -- PLB primary address valid indicator
+-- PLB_SAValid -- PLB secondary address valid indicator
+-- PLB_rdPrim -- PLB secondary to primary read request indicator
+-- PLB_wrPrim -- PLB secondary to primary write request indicator
+-- PLB_masterID -- PLB current master identifier
+-- PLB_abort -- PLB abort request indicator
+-- PLB_busLock -- PLB bus lock
+-- PLB_RNW -- PLB read/not write
+-- PLB_BE -- PLB byte enables
+-- PLB_MSize -- PLB master data bus size
+-- PLB_size -- PLB transfer size
+-- PLB_type -- PLB transfer type
+-- PLB_lockErr -- PLB lock error indicator
+-- PLB_wrDBus -- PLB write data bus
+-- PLB_wrBurst -- PLB burst write transfer indicator
+-- PLB_rdBurst -- PLB burst read transfer indicator
+-- PLB_wrPendReq -- PLB write pending bus request indicator
+-- PLB_rdPendReq -- PLB read pending bus request indicator
+-- PLB_wrPendPri -- PLB write pending request priority
+-- PLB_rdPendPri -- PLB read pending request priority
+-- PLB_reqPri -- PLB current request priority
+-- PLB_TAttribute -- PLB transfer attribute
+-- Sl_addrAck -- Slave address acknowledge
+-- Sl_SSize -- Slave data bus size
+-- Sl_wait -- Slave wait indicator
+-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
+-- Sl_wrDAck -- Slave write data acknowledge
+-- Sl_wrComp -- Slave write transfer complete indicator
+-- Sl_wrBTerm -- Slave terminate write burst transfer
+-- Sl_rdDBus -- Slave read data bus
+-- Sl_rdWdAddr -- Slave read word address
+-- Sl_rdDAck -- Slave read data acknowledge
+-- Sl_rdComp -- Slave read transfer complete indicator
+-- Sl_rdBTerm -- Slave terminate read burst transfer
+-- Sl_MBusy -- Slave busy indicator
+-- Sl_MWrErr -- Slave write error indicator
+-- Sl_MRdErr -- Slave read error indicator
+-- Sl_MIRQ -- Slave interrupt indicator
+-- IP2INTC_Irpt -- Interrupt output to processor
+------------------------------------------------------------------------------
+
+entity xps_fx2 is
+ generic
+ (
+ -- ADD USER GENERICS BELOW THIS LINE ---------------
+ --USER generics added here
+ C_TX_FIFO_KBYTE : integer := 32;
+ C_RX_FIFO_KBYTE : integer := 2;
+ C_USE_ADDR_FIFO : integer := 1;
+ C_TX_FIFO_CLK_180 : integer := 0;
+ C_USE_CRITICAL : integer := 0;
+ -- ADD USER GENERICS ABOVE THIS LINE ---------------
+
+ -- DO NOT EDIT BELOW THIS LINE ---------------------
+ -- Bus protocol parameters, do not add to or delete
+ C_BASEADDR : std_logic_vector := X"FFFFFFFF";
+ C_HIGHADDR : std_logic_vector := X"00000000";
+ C_SPLB_AWIDTH : integer := 32;
+ C_SPLB_DWIDTH : integer := 128;
+ C_SPLB_NUM_MASTERS : integer := 8;
+ C_SPLB_MID_WIDTH : integer := 3;
+ C_SPLB_NATIVE_DWIDTH : integer := 32;
+ C_SPLB_P2P : integer := 0;
+ C_SPLB_SUPPORT_BURSTS : integer := 0;
+ C_SPLB_SMALLEST_MASTER : integer := 32;
+ C_SPLB_CLK_PERIOD_PS : integer := 10000;
+ C_FAMILY : string := "virtex5"
+ -- DO NOT EDIT ABOVE THIS LINE ---------------------
+ );
+ port
+ (
+ -- ADD USER PORTS BELOW THIS LINE ------------------
+ --USER ports added here
+ --USB_RX_CLK : in std_logic;
+ USB_IFCLK : in std_logic;