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#The TLUT tool flow: An introduction The TLUT tool flow is a tool flow that generates FPGA configurations. Its biggest difference with the traditional FPGA flow is the use of a new technology mapper, the TLUT mapper. The TLUT tool flow was developed to implement Dynamic Circuit Specialization (DCS) on FPGAs. A DCS implementation of an application specializes its circuit for the current values of a number of specific inputs, called parameters. This specialized circuit is smaller, and in some cases faster, than the original circuit. However, it is only correct for one set of parameter values. Each time the parameters change value, a new specialized circuit is generated. This new specialized circuit is then loaded into the FPGA using partial run-time reconfiguration.

The TLUT tool flow offers an efficient implementation of DCS because it uses the concept of parameterized configurations. A parameterized configuration is a configuration in which some bits are expressed as Boolean functions of the parameters. Before the FPGA can be configured, the parameter values are used to evaluate the Boolean functions. This generates the specialized configuration. Several papers on the academic underpinnings of the TLUT tool flow are listed in the wiki of this project or are contained in the documentation directory. There you can also find more information on our current research on extending and improving the TLUT tool flow. The TLUT tool flow itself and how to use it, is described in much more detail in this user guide.

##What can I do with this tool flow? First, you can evaluate our adapted TLUT technology mapper. This allows you to compare its results with a conventional technology mapper and see for yourself if Dynamic Circuit Specialization can be used to optimize your application. We have included a framework to make this comparison very easy. The following pages provide clear examples and show how to adapt the framework for you own uses.

Second, our tool flow has been integrated with the Xilinx FPGA tool flow so that you can perform DCS on a commercial Virtex 2 Pro or Virtex 5 FPGA. A number of examples that you can run right away on either the XUPV2P board (Virtex 2 Pro) or ML507 board (Virtex 5) are included in this repository. Information on creating your own project is also included in this document. The tool flow may be extended in the future to support more FPGAs, such as the Virtex 6 and 7.

##License The tlut tool flow is licensed by Ghent University. The license is included in all licensed code and in the repository, it is also printed below.


This software license agreement (hereinafter referred to as the "Agreement") provides the terms and conditions under which Universiteit Gent - Ghent University (hereinafter referred to as "UGent") is willing to grant you (being the person or entity installing and using the Licensed Software for Non-Commercial Purposes, hereinafter referred to as the "Licensee") a non-exclusive, limited right to use the Licensed Software under UGent Copyright.

By downloading the Licensed Software, or installing Licensed Software, or using Licensed Software, or clicking on the "accept" button under this Agreement, Licensee agrees to accept the terms and conditions of this Agreement and agrees to be bound by this Agreement. If Licensee does not agree with any of the terms or conditions of this Agreement, he should not download or install or use the Licensed Software.

(1) Licensee warrants and represents that the person accepting this Agreement on behalf of Licensee is its legally authorized representative and is duly authorized to accept agreements of this type on behalf of Licensee and obligate Licensee to the terms and conditions herein. Any breach of this warranty and representation is a material breach of this Agreement and, in such event, this Agreement and the rights granted to Licensee shall terminate automatically.

(2) Definitions - For the purposes of this Agreement, the following terms shall have the following meanings: a) "Software": refers to the computer software supplied with this Agreement named "tlut flow" and provided in Python and Java code form. b) "Licensed Software": refers to the Software, and any other computer software and documentation, if any, supplied with this Agreement. c) "Adaptation": refers to any work based on the Licensed Software, including: 1) any work which incorporates all or part of the Licensed Software, 2) any work which includes modifications to the Software, including but not limited to bug fixes, 3) any work which would be regarded as a derivative work of the Software under the Belgian Copyright Law, and 4) any work which is otherwise covered by any of UGent's intellectual property rights in the Licensed Software. d) "Grant Back Software": refers to any 1) modification of the objects distributed as the Software, including but not limited to the addition, deletion, and modification of verbs and properties on the objects, 2) creation of children to the objects distributed as the Software. e) "Copyright Holder": refers to Universiteit Gent - Ghent University, public institution with legal personality, having its administrative offices in Belgium, B-9000 Gent, Sint-Pietersnieuwstraat 25 (herein also referred to as "UGent") f) "Non-Commercial Purpose": refers to use of the Licensed Software solely for the purpose of education or research. "Non-Commercial Purpose" excludes, without limitation, any use of the Software as part of or in connection with a product (including software) or service which is sold, offered for sale, licensed, leased, loaned or rented.

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##Installation and usage manual For installation instructions and an introduction to using the tool flow, please read documentation/user_guide.pdf


The user should provide the following dependencies:


  • A Xilinx XUP Virtex-II Pro Development System (XUPV2P board) and Xilinx Design Suite 9 (tested with version 9.1 SP2), Xilinx Inc.,
    Version 9 is old, but newer versions don't work well with the Virtex-II Pro.
  • A Xilinx ML507 Virtex-5 Development System and Xilinx Design Suite (tested with version 13.4), Xilinx Inc.

##Contact us The TLUT tool flow is released by Ghent University, ELIS department, Hardware and Embedded Systems (HES) group (

If you encounter bugs, want to use the TLUT tool flow but need support or want to tell us about your results, please contact us. We can be reached at

##Referencing the TLUT tool flow If you use the TLUT tool flow in your work, please reference in your publications the following paper:

Karel Bruneel, Wim Heirman, and Dirk Stroobandt. 2011. “Dynamic Data Folding with Parameterizable FPGA Configurations.” ACM Transactions on Design Automation of Electronic Systems 16 (4).

You may also refer to one of our others papers if you think it is more related. alpha


TLUT tool flow for parameterised configurations for FPGAs







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