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  1. UVVM Public

    UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

    VHDL 262 72

  2. UVVM_Light Public

    This repository is a subset of UVVM with Utility library and BFMs, and is intended as a UVVM starting platform for thos who only need the Utility Library and BFMs. Community forum: https://forum.uv…

    VHDL 13 6

  3. Repository for the UVVM community to share VIPs. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

    VHDL 10 5

  4. UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

    VHDL 5 2

  5. UVVM_3_BETA Public

    VHDL 3

47 contributions in the last year

Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Mon Wed Fri

Contribution activity

October 2022

Created 1 commit in 1 repository
Reviewed 1 pull request in 1 repository
UVVM/UVVM 1 pull request
2 contributions in private repositories Oct 5

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