diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml index 9f84198cf..46755f8a3 100644 --- a/.github/workflows/Pipeline.yml +++ b/.github/workflows/Pipeline.yml @@ -5,8 +5,18 @@ on: pull_request: jobs: + Prepare: + uses: pyTooling/Actions/.github/workflows/PrepareJob.yml@dev + Build-OSVVM: name: Build OSVVM + strategy: + fail-fast: false + matrix: + include: + - {simulator: 'nvc', backend: 'llvm', startScript: 'StartNVC.tcl'} + - {simulator: 'ghdl', backend: 'mcode', startScript: 'StartGHDL.tcl'} + - {simulator: 'ghdl', backend: 'llvm', startScript: 'StartGHDL.tcl'} runs-on: ubuntu-24.04 steps: - name: ⏬ Checkout repository @@ -18,34 +28,50 @@ jobs: - name: 🔧 Install tcllib run: sudo apt-get install -y --no-install-recommends tcllib - - name: Setup GHDL ${{ inputs.ghdl_backend }} + - name: Setup GHDL ${{ matrix.backend }} uses: ghdl/setup-ghdl@v1 + if: matrix.simulator == 'ghdl' + with: + version: latest + backend: ${{ matrix.backend }} + + - name: Setup NVC + uses: nickg/setup-nvc@v1 + if: matrix.simulator == 'nvc' with: version: latest - backend: llvm - name: Prepare run: | - mkdir -p temp/ghdl + mkdir -p temp/${{ matrix.simulator }} - - name: 🔨 Pre-compile OSVVM + - name: 🔨 Prepare Script run: | - cd temp/ghdl + cd temp/${{ matrix.simulator }} tee run.tcl < '0'); done : out std_logic; -- Completion - res : out std_logic_vector -- Result + res : out std_logic_vector -- Result ); -end entity arith_scaler; +end entity; architecture rtl of arith_scaler is @@ -75,15 +75,14 @@ architecture rtl of arith_scaler is constant R : positive := log2ceil(imax(DIVS)+1); -- Division Properties - type tDivProps is - record -- Properties of the operation for a divisor + type tDivProps is record -- Properties of the operation for a divisor steps : T_POSVEC(DIVS'range); -- Steps to perform align : T_POSVEC(DIVS'range); -- Left-aligned divisor - end record; + end record; function computeProps return tDivProps is - variable res : tDivProps; - variable min_steps : positive; + variable res : tDivProps; + variable min_steps : positive; begin for i in DIVS'range loop res.steps(i) := N+X - log2ceil(DIVS(i)+1) + 1; @@ -103,6 +102,7 @@ architecture rtl of arith_scaler is subtype tResMask is std_logic_vector(MAX_DIV_STEPS-1 downto 0); type tResMasks is array(natural range<>) of tResMask; + function computeMasks return tResMasks is variable res : tResMasks(DIVS'range); begin @@ -112,6 +112,7 @@ architecture rtl of arith_scaler is end loop; return res; end computeMasks; + constant RES_MASKS : tResMasks(DIVS'range) := computeMasks; -- Values computed for the selected multiplier/divisor pair. @@ -134,22 +135,23 @@ begin begin if rising_edge(clk) then if rst = '1' then - MS <= (others => '-'); + MS <= (others => '0'); elsif start = '1' then MS <= unsigned(msel); end if; end if; end process; - multiplier <= (others => 'X') when Is_X(std_logic_vector(MS)) else - to_unsigned(MULS(to_integer(MS)), multiplier'length); + + multiplier <= (others => 'X') when Is_X(std_logic_vector(MS)) else to_unsigned(MULS(to_integer(MS)), multiplier'length); end generate genMultiMul; + genSingleMul: if MULS'length = 1 generate multiplier <= to_unsigned(MULS(0), multiplier'length); end generate genSingleMul; -- Selection of Divisor genMultiDiv: if DIVS'length > 1 generate - signal DS : unsigned(dsel'range) := (others => '-'); + signal DS : unsigned(dsel'range) := (others => '0'); begin process(clk) begin @@ -161,15 +163,13 @@ begin end if; end if; end process; - muloffset <= (others => 'X') when Is_X(dsel) else - to_unsigned(DIVS(to_integer(unsigned(dsel)))/2, muloffset'length); - divisor <= (others => 'X') when Is_X(std_logic_vector(DS)) else - to_unsigned(DIV_PROPS.align(to_integer(DS)), divisor'length); - divcini <= (others => 'X') when Is_X(std_logic_vector(DS)) else - to_unsigned(DIV_PROPS.steps(to_integer(DS))-1, divcini'length); - divmask <= (others => 'X') when Is_X(std_logic_vector(DS)) else - RES_MASKS(to_integer(DS)); + + muloffset <= (others => 'X') when Is_X(dsel) else to_unsigned(DIVS(to_integer(unsigned(dsel)))/2, muloffset'length); + divisor <= (others => 'X') when Is_X(std_logic_vector(DS)) else to_unsigned(DIV_PROPS.align(to_integer(DS)), divisor'length); + divcini <= (others => 'X') when Is_X(std_logic_vector(DS)) else to_unsigned(DIV_PROPS.steps(to_integer(DS))-1, divcini'length); + divmask <= (others => 'X') when Is_X(std_logic_vector(DS)) else RES_MASKS(to_integer(DS)); end generate genMultiDiv; + genSingleDiv: if DIVS'length = 1 generate muloffset <= to_unsigned(DIVS(0)/2, muloffset'length); divisor <= to_unsigned(DIV_PROPS.align(0), divisor'length); @@ -180,8 +180,8 @@ begin ----------------------------------------------------------------------------- -- Implementation of Scaling Operation blkMain : block - signal C : unsigned(1+log2ceil(MAX_ANY_STEPS) downto 0) := ('0', others => '-'); - signal Q : unsigned(X+N downto 0) := (others => '-'); + signal C : unsigned(1+log2ceil(MAX_ANY_STEPS) downto 0) := (others => '0'); + signal Q : unsigned( X+N downto 0) := (others => '0'); begin process(clk) variable cnxt : unsigned(C'range); @@ -189,8 +189,8 @@ begin begin if rising_edge(clk) then if rst = '1' then - C <= ('0', others => '-'); - Q <= (others => '-'); + C <= (others => '0'); + Q <= (others => '0'); else if start = '1' then C <= "11" & to_unsigned(MAX_MUL_STEPS-1, C'length-2); @@ -213,6 +213,7 @@ begin -- DIV Phase d := Q(Q'left downto Q'left-R) - divisor; Q <= Q(Q'left-1 downto 0) & not d(d'left); + if d(d'left) = '0' then Q(Q'left downto Q'left-R+1) <= d(d'left-1 downto 0); end if; @@ -223,16 +224,17 @@ begin end if; end if; end process; + done <= not C(C'left); + process(Q, divmask) variable r : std_logic_vector(res'length-1 downto 0); begin - r := (others => '0'); - r(imin(r'left, tResMask'left) downto 0) := - std_logic_vector(Q(imin(r'left, tResMask'left) downto 0)) and - divmask(imin(r'left, tResMask'left) downto 0); + r := (others => '0'); + r(imin(r'left, tResMask'left) downto 0) := std_logic_vector(Q(imin(r'left, tResMask'left) downto 0)) and divmask(imin(r'left, tResMask'left) downto 0); res <= r; end process; + end block blkMain; -end rtl; +end architecture; diff --git a/src/arith/arith_shifter_barrel.files b/src/arith/arith_shifter_barrel.files deleted file mode 100644 index 119f40a4e..000000000 --- a/src/arith/arith_shifter_barrel.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package -vhdl PoC "src/arith/arith_shifter_barrel.vhdl" # Top-Level diff --git a/src/arith/arith_sqrt.files b/src/arith/arith_sqrt.files deleted file mode 100644 index 4f3af3528..000000000 --- a/src/arith/arith_sqrt.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package -vhdl PoC "src/arith/arith_sqrt.vhdl" # Top-Level diff --git a/src/arith/arith_trng.files b/src/arith/arith_trng.files deleted file mode 100644 index 0e896392d..000000000 --- a/src/arith/arith_trng.files +++ /dev/null @@ -1,13 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" -include "src/misc/sync/sync_Bits.files" - -# PoC.arith -vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package -vhdl PoC "src/arith/arith_trng.vhdl" # Top-Level diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl index 5e83cc7bc..44aba0b6c 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite.pkg.vhdl @@ -45,7 +45,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl index e82e709f1..52f829494 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO.vhdl @@ -27,7 +27,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl index 2f462d2d0..9c710f750 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_FIFO_cdc.vhdl @@ -25,7 +25,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl new file mode 100644 index 000000000..999e932d8 --- /dev/null +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl @@ -0,0 +1,129 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Stefan Unrein +-- +-- Entity: A generic AXI4-Lite version register for Git. +-- +-- Description: +-- ------------------------------------- +-- This version register can be auto filled with constants from Git. Software +-- can read from what revision a firmware (bitstream, PL code) was build. +-- +-- Use the pre-synthesis script from +-- PoC/tools/git/preSynth_GitVersionRegister_Vivado.tcl +-- to create a memory file with all necessary information. Add this file name to +-- the VERSION_FILE_NAME generic. +-- +-- License: +-- ============================================================================= +-- Copyright 2024-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.config.all; +use work.utils.all; +use work.vectors.all; +use work.strings.all; +use work.axi4lite.all; +use work.xil.all; + +use work.mem_GitVersionRegister.all; + + +entity AXI4Lite_GitVersionRegister is + Generic ( + VERSION_FILE_NAME : string; -- Path to version-memory generated by preSynth_GitVersionRegister_Vivado.tcl + WRITE_FILE_NAME : string := ""; -- Writes the Version-Register structure to a csv file with this name. Leave empty if not used. + INCLUDE_XIL_DNA : boolean := false; -- Enable Xilinx DNA Port + INCLUDE_XIL_USER_EFUSE : boolean := false; -- Enable Xilinx User eFuse + USER_ID : std_logic_vector(95 downto 0) := (others => '0'); -- User ID saved in register "UID.User_ID" + IGNORE_HIGH_ADDRESS : boolean := true; -- Disables the High-Address Check. If the Base-Address of the whole register can be ignored, leave as true, otherwhise, the addresses in the config need be set with base-address + RESPONSE_ON_ERROR : T_AXI4_Response := C_AXI4_RESPONSE_DECODE_ERROR -- If not address matches then config of the AXI4Lite transaction, return this code + ); + Port ( + Clock : in std_logic; + Reset : in std_logic; + + AXI4Lite_m2s : in T_AXI4Lite_BUS_M2S; + AXI4Lite_s2m : out T_AXI4Lite_BUS_S2M + ); +end entity; + + +architecture rtl of AXI4Lite_GitVersionRegister is + constant CONFIG : T_AXI4_Register_Vector := get_Version_Descriptor; + constant VersionData : T_SLVV_32(0 to C_Num_Version_Header - 1) := read_Version_from_mem(PROJECT_DIR & VERSION_FILE_NAME); + + signal RegisterFile_ReadPort : T_SLVV(0 to CONFIG'Length -1)(DATA_BITS - 1 downto 0); + signal RegisterFile_WritePort : T_SLVV(0 to CONFIG'Length -1)(DATA_BITS - 1 downto 0); + + signal UID_vec : T_SLVV(0 to C_Num_Reg_UID -1)(DATA_BITS - 1 downto 0); + +begin + Header_file_gen : if WRITE_FILE_NAME'length > 0 generate + begin + assert write_csv_file(PROJECT_DIR & WRITE_FILE_NAME, CONFIG) report "Failure in writing CSV File" severity warning; + end generate; + + AXI4LiteReg : entity work.AXI4Lite_Register + generic map( + CONFIG => CONFIG, + IGNORE_HIGH_ADDRESS => IGNORE_HIGH_ADDRESS, + RESPONSE_ON_ERROR => RESPONSE_ON_ERROR + ) + port map( + Clock => Clock, + Reset => Reset, + + AXI4Lite_m2s => AXI4Lite_m2s, + AXI4Lite_s2m => AXI4Lite_s2m, + + RegisterFile_ReadPort => RegisterFile_ReadPort, + RegisterFile_WritePort => RegisterFile_WritePort + ); + RegisterFile_WritePort(0 to C_Num_Version_Header -1) <= VersionData; + RegisterFile_WritePort(C_Num_Version_Header to C_Num_Version_Register -1) <= UID_vec; + + --------------------------------- + -- Generate data for UID-vector + --------------------------------- + UID_vec(low(C_Num_reg_UID_vec, 2) to high(C_Num_reg_UID_vec, 2)) <= to_slvv_32(USER_ID); + + dna_gen : if INCLUDE_XIL_DNA generate + signal DNA : std_logic_vector(get_DNABITS -1 downto 0); + begin + DNA_inst : component xil_DNAPort + port map( + Clock => Clock, + Reset => Reset, + Valid => open, + DataOut => DNA + ); + UID_vec(low(C_Num_reg_UID_vec, 0) to high(C_Num_reg_UID_vec, 0)) <= rev(to_slvv_32(resize(DNA, C_Num_reg_UID_vec(0) * 32))); + else generate + UID_vec(low(C_Num_reg_UID_vec, 0) to high(C_Num_reg_UID_vec, 0)) <= (others => (others => '0')); + end generate; + + efuse_gen : if INCLUDE_XIL_USER_EFUSE generate + assert false report "AXI4Lite_GitVersionRegister:: INCLUDE_XIL_USR_EFUSE is currently not supported, feel free to implement it ;)" severity failure; + else generate + UID_vec(low(C_Num_reg_UID_vec, 1) to high(C_Num_reg_UID_vec, 1)) <= (others => (others => '0')); + end generate; +end architecture; diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl index c1ed0f5b3..b2b8d7d22 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl index 8a7851c9e..10e491e0a 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl @@ -33,7 +33,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl index ccf551867..c0001bfe5 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Manager.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl index 16c9de726..11041223d 100644 --- a/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl +++ b/src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl index 3a7e264a2..eec417aaf 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream.pkg.vhdl @@ -45,7 +45,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl index 67f504a42..111aa7281 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_DeMux.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl index cc94db984..691b8c53a 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl index 3a3a03fff..b1a43f6bf 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_cdc.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl index 7d2055bc1..03362e5b8 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempgot.vhdl @@ -28,7 +28,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl index 534d36f44..559730484 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_FIFO_tempput.vhdl @@ -37,7 +37,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl index 437a43956..66cde6076 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_Mux.vhdl @@ -32,7 +32,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl b/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl index 9b88dd3bc..ad1a4689e 100644 --- a/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl +++ b/src/bus/axi4/AXI4Stream/AXI4Stream_Stage.vhdl @@ -22,7 +22,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_Common.pkg.vhdl b/src/bus/axi4/AXI4_Common.pkg.vhdl index 892a833dc..dd41b8fd1 100644 --- a/src/bus/axi4/AXI4_Common.pkg.vhdl +++ b/src/bus/axi4/AXI4_Common.pkg.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_FIFO.vhdl b/src/bus/axi4/AXI4_FIFO.vhdl index 9a2a75170..4c6986d6b 100644 --- a/src/bus/axi4/AXI4_FIFO.vhdl +++ b/src/bus/axi4/AXI4_FIFO.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_FIFO_cdc.vhdl b/src/bus/axi4/AXI4_FIFO_cdc.vhdl index b8de666c1..485bd0d81 100644 --- a/src/bus/axi4/AXI4_FIFO_cdc.vhdl +++ b/src/bus/axi4/AXI4_FIFO_cdc.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_Full.pkg.vhdl b/src/bus/axi4/AXI4_Full.pkg.vhdl index 08434066f..957a07a12 100644 --- a/src/bus/axi4/AXI4_Full.pkg.vhdl +++ b/src/bus/axi4/AXI4_Full.pkg.vhdl @@ -45,7 +45,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_Termination_Manager.vhdl b/src/bus/axi4/AXI4_Termination_Manager.vhdl index 878945d5a..2f57ebb37 100644 --- a/src/bus/axi4/AXI4_Termination_Manager.vhdl +++ b/src/bus/axi4/AXI4_Termination_Manager.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_Termination_Subordinate.vhdl b/src/bus/axi4/AXI4_Termination_Subordinate.vhdl index 6ff525eb9..d04e34dc7 100644 --- a/src/bus/axi4/AXI4_Termination_Subordinate.vhdl +++ b/src/bus/axi4/AXI4_Termination_Subordinate.vhdl @@ -25,7 +25,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/AXI4_to_AXI4Lite.vhdl b/src/bus/axi4/AXI4_to_AXI4Lite.vhdl index 8b8256c0b..607a9d94e 100644 --- a/src/bus/axi4/AXI4_to_AXI4Lite.vhdl +++ b/src/bus/axi4/AXI4_to_AXI4Lite.vhdl @@ -21,7 +21,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/axi4.pkg.vhdl b/src/bus/axi4/axi4.pkg.vhdl index f51d9a005..e6e44cf5c 100644 --- a/src/bus/axi4/axi4.pkg.vhdl +++ b/src/bus/axi4/axi4.pkg.vhdl @@ -27,7 +27,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/axi4/axi4.pro b/src/bus/axi4/axi4.pro index a9df8175e..6637471c2 100644 --- a/src/bus/axi4/axi4.pro +++ b/src/bus/axi4/axi4.pro @@ -1,6 +1,6 @@ # ============================================================================= # Authors: -# Adrian Weiland +# Adrian Weiland, Stefan Unrein # # License: # ============================================================================= @@ -19,26 +19,28 @@ # limitations under the License. # ============================================================================= -analyze AXI4_Common.pkg.vhdl -analyze AXI4_Full.pkg.vhdl -analyze ./AXI4Stream/AXI4Stream.pkg.vhdl -analyze ./AXI4Lite/AXI4Lite.pkg.vhdl +#Packages included on main PoC.pro +#analyze AXI4_Common.pkg.vhdl +#analyze AXI4_Full.pkg.vhdl +#analyze ./AXI4Stream/AXI4Stream.pkg.vhdl +#analyze ./AXI4Lite/AXI4Lite.pkg.vhdl +#analyze axi4.pkg.vhdl + analyze AXI4_FIFO.vhdl analyze AXI4_FIFO_cdc.vhdl analyze AXI4_Termination_Manager.vhdl analyze AXI4_Termination_Subordinate.vhdl analyze AXI4_to_AXI4Lite.vhdl -analyze axi4.pkg.vhdl analyze AXI4_OSVVM.pkg.vhdl analyze ./AXI4Lite/AXI4Lite_FIFO.vhdl analyze ./AXI4Lite/AXI4Lite_FIFO_cdc.vhdl -# analyze ./AXI4Lite/AXI4Lite_GitVersionRegister.vhdl analyze ./AXI4Lite/AXI4Lite_Register.vhdl analyze ./AXI4Lite/AXI4Lite_Termination_Manager.vhdl analyze ./AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl analyze ./AXI4Lite/AXI4Lite_OSVVM.pkg.vhdl +analyze ./AXI4Lite/AXI4Lite_GitVersionRegister.vhdl analyze ./AXI4Stream/AXI4Stream_FIFO.vhdl analyze ./AXI4Stream/AXI4Stream_FIFO_cdc.vhdl @@ -47,4 +49,6 @@ analyze ./AXI4Stream/AXI4Stream_FIFO_tempput.vhdl analyze ./AXI4Stream/AXI4Stream_Stage.vhdl analyze ./AXI4Stream/AXI4Stream_Mux.vhdl analyze ./AXI4Stream/AXI4Stream_DeMux.vhdl +analyze ../../misc/gearbox/gearbox_down_cc.vhdl +analyze ../../misc/gearbox/gearbox_up_cc.vhdl diff --git a/src/bus/bus.pro b/src/bus/bus.pro index ac5e20f27..b5a1f68ed 100644 --- a/src/bus/bus.pro +++ b/src/bus/bus.pro @@ -19,6 +19,7 @@ # limitations under the License. # ============================================================================= -analyze bus_Arbiter.vhdl +analyze ./bus_Arbiter.vhdl + include ./stream/stream.pro include ./axi4/axi4.pro diff --git a/src/bus/bus_Arbiter.files b/src/bus/bus_Arbiter.files deleted file mode 100644 index 7f503475e..000000000 --- a/src/bus/bus_Arbiter.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus -# vhdl PoC "src/bus/bus.pkg.vhdl" # PoC.bus package -vhdl PoC "src/bus/bus_Arbiter.vhdl" # Top-Level diff --git a/src/bus/bus_Arbiter.vhdl b/src/bus/bus_Arbiter.vhdl index 35d43ce01..8ffa1047b 100644 --- a/src/bus/bus_Arbiter.vhdl +++ b/src/bus/bus_Arbiter.vhdl @@ -68,7 +68,7 @@ begin -- Assert STRATEGY for known strings -- ========================================================================================================================================================== - assert ((STRATEGY = "RR") or (STRATEGY = "LOT")) + assert ((STRATEGY = "RR") )--or (STRATEGY = "LOT")) report "Unknown arbiter strategy." severity FAILURE; -- Round Robin Arbiter diff --git a/src/bus/stream/stream.pkg.vhdl b/src/bus/stream/stream.pkg.vhdl index 203f767c4..496b718f1 100644 --- a/src/bus/stream/stream.pkg.vhdl +++ b/src/bus/stream/stream.pkg.vhdl @@ -39,7 +39,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/stream/stream.pro b/src/bus/stream/stream.pro index adb23e468..746356a68 100644 --- a/src/bus/stream/stream.pro +++ b/src/bus/stream/stream.pro @@ -1,7 +1,25 @@ # ============================================================================= # Authors: -# Adrian Weiland +# Adrian Weiland, Stefan Unrein +# +# License: # ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +library PoC analyze stream.pkg.vhdl analyze stream_FIFO.vhdl @@ -10,3 +28,4 @@ analyze stream_FrameGenerator.vhdl analyze stream_Mirror.vhdl analyze stream_Mux.vhdl analyze stream_Source.vhdl + diff --git a/src/bus/stream/stream_DeMux.files b/src/bus/stream/stream_DeMux.files deleted file mode 100644 index 2cfb308e2..000000000 --- a/src/bus/stream/stream_DeMux.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus.stream -vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package -vhdl PoC "src/bus/stream/stream_DeMux.vhdl" # Top-Level diff --git a/src/bus/stream/stream_DeMux.vhdl b/src/bus/stream/stream_DeMux.vhdl index 086187de1..d81dc5c2b 100644 --- a/src/bus/stream/stream_DeMux.vhdl +++ b/src/bus/stream/stream_DeMux.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/stream/stream_FIFO.files b/src/bus/stream/stream_FIFO.files deleted file mode 100644 index ce396ce4e..000000000 --- a/src/bus/stream/stream_FIFO.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus.stream -vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package -vhdl PoC "src/bus/stream/stream_FIFO.vhdl" # Top-Level diff --git a/src/bus/stream/stream_FIFO.vhdl b/src/bus/stream/stream_FIFO.vhdl index d6366f4d8..354e13cb8 100644 --- a/src/bus/stream/stream_FIFO.vhdl +++ b/src/bus/stream/stream_FIFO.vhdl @@ -27,7 +27,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/stream/stream_FrameGenerator.files b/src/bus/stream/stream_FrameGenerator.files deleted file mode 100644 index ee8c78b1a..000000000 --- a/src/bus/stream/stream_FrameGenerator.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus.stream -vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package -vhdl PoC "src/bus/stream/stream_FrameGenerator.vhdl" # Top-Level diff --git a/src/bus/stream/stream_FrameGenerator.vhdl b/src/bus/stream/stream_FrameGenerator.vhdl index 91dc30793..b160484ad 100644 --- a/src/bus/stream/stream_FrameGenerator.vhdl +++ b/src/bus/stream/stream_FrameGenerator.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/stream/stream_Mirror.files b/src/bus/stream/stream_Mirror.files deleted file mode 100644 index 43aa81444..000000000 --- a/src/bus/stream/stream_Mirror.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus.stream -vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package -vhdl PoC "src/bus/stream/stream_Mirror.vhdl" # Top-Level diff --git a/src/bus/stream/stream_Mirror.vhdl b/src/bus/stream/stream_Mirror.vhdl index ecd0070d4..071a5ed13 100644 --- a/src/bus/stream/stream_Mirror.vhdl +++ b/src/bus/stream/stream_Mirror.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/bus/stream/stream_Mux.files b/src/bus/stream/stream_Mux.files deleted file mode 100644 index 2ce4bc921..000000000 --- a/src/bus/stream/stream_Mux.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus.stream -vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package -vhdl PoC "src/bus/stream/stream_Mux.vhdl" # Top-Level diff --git a/src/bus/stream/stream_Mux.vhdl b/src/bus/stream/stream_Mux.vhdl index a29cddd5c..52bd18452 100644 --- a/src/bus/stream/stream_Mux.vhdl +++ b/src/bus/stream/stream_Mux.vhdl @@ -2,9 +2,10 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann +-- Stefan Unrein -- --- Entity: A generic buffer module for the PoC.Stream protocol. +-- Entity: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------- @@ -12,18 +13,19 @@ -- -- License: -- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= @@ -39,107 +41,106 @@ use work.vectors.all; entity stream_Mux is generic ( - PORTS : positive := 2; - DATA_BITS : positive := 8; - META_BITS : natural := 8; - META_REV_BITS : natural := 2--; --- WEIGHTS : T_INTVEC := (1, 1) + PORTS : positive := 2; + DATA_BITS : positive := 8; + META_BITS : natural := 8; + META_REV_BITS : natural := 2 ); port ( - Clock : in std_logic; - Reset : in std_logic; + Clock : in std_logic; + Reset : in std_logic; -- IN Ports - In_Valid : in std_logic_vector(PORTS - 1 downto 0); - In_Data : in T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); - In_Meta : in T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0); - In_Meta_rev : out T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0); - In_SOF : in std_logic_vector(PORTS - 1 downto 0); - In_EOF : in std_logic_vector(PORTS - 1 downto 0); - In_Ack : out std_logic_vector(PORTS - 1 downto 0); + In_Valid : in std_logic_vector(PORTS - 1 downto 0); + In_Data : in T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0); + In_Meta : in T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0); + In_Meta_rev : out T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0); + In_SOF : in std_logic_vector(PORTS - 1 downto 0); + In_EOF : in std_logic_vector(PORTS - 1 downto 0); + In_Ack : out std_logic_vector(PORTS - 1 downto 0); -- OUT Port - Out_Valid : out std_logic; - Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0); - Out_Meta : out std_logic_vector(META_BITS - 1 downto 0); - Out_Meta_rev : in std_logic_vector(META_REV_BITS - 1 downto 0); - Out_SOF : out std_logic; - Out_EOF : out std_logic; - Out_Ack : in std_logic + Out_Valid : out std_logic; + Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0); + Out_Meta : out std_logic_vector(META_BITS - 1 downto 0); + Out_Meta_rev : in std_logic_vector(META_REV_BITS - 1 downto 0); + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic ); end entity; architecture rtl of stream_Mux is - attribute KEEP : boolean; - attribute FSM_ENCODING : string; + attribute KEEP : boolean; + attribute FSM_ENCODING : string; subtype T_CHANNEL_INDEX is natural range 0 to PORTS - 1; type T_STATE is (ST_IDLE, ST_DATAFLOW); - signal State : T_STATE := ST_IDLE; - signal NextState : T_STATE; + signal State : T_STATE := ST_IDLE; + signal NextState : T_STATE; - signal FSM_Dataflow_en : std_logic; + signal FSM_Dataflow_en : std_logic; - signal RequestVector : std_logic_vector(PORTS - 1 downto 0); - signal RequestWithSelf : std_logic; - signal RequestWithoutSelf : std_logic; + signal RequestVector : std_logic_vector(PORTS - 1 downto 0); + signal RequestWithSelf : std_logic; + signal RequestWithoutSelf : std_logic; - signal RequestLeft : unsigned(PORTS - 1 downto 0); - signal SelectLeft : unsigned(PORTS - 1 downto 0); - signal SelectRight : unsigned(PORTS - 1 downto 0); + signal RequestLeft : unsigned(PORTS - 1 downto 0); + signal SelectLeft : unsigned(PORTS - 1 downto 0); + signal SelectRight : unsigned(PORTS - 1 downto 0); - signal ChannelPointer_en : std_logic; - signal ChannelPointer : std_logic_vector(PORTS - 1 downto 0); - signal ChannelPointer_d : std_logic_vector(PORTS - 1 downto 0) := to_slv(2 ** (PORTS - 1), PORTS); - signal ChannelPointer_nxt : std_logic_vector(PORTS - 1 downto 0); - signal ChannelPointer_bin : unsigned(log2ceilnz(PORTS) - 1 downto 0); + signal ChannelPointer_en : std_logic; + signal ChannelPointer : std_logic_vector(PORTS - 1 downto 0); + signal ChannelPointer_d : std_logic_vector(PORTS - 1 downto 0) := to_slv(2 ** (PORTS - 1), PORTS); + signal ChannelPointer_nxt : std_logic_vector(PORTS - 1 downto 0); + signal ChannelPointer_bin : unsigned(log2ceilnz(PORTS) - 1 downto 0); - signal idx : T_CHANNEL_INDEX; + signal idx : T_CHANNEL_INDEX; - signal Out_EOF_i : std_logic; + signal Out_EOF_i : std_logic; begin - RequestVector <= In_Valid and In_SOF; - RequestWithSelf <= slv_or(RequestVector); - RequestWithoutSelf <= slv_or(RequestVector and not ChannelPointer_d); + RequestVector <= In_Valid and In_SOF; + RequestWithSelf <= slv_or(RequestVector); + RequestWithoutSelf <= slv_or(RequestVector and not ChannelPointer_d); process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then - State <= ST_IDLE; + State <= ST_IDLE; else - State <= NextState; + State <= NextState; end if; end if; end process; - process(State, RequestWithSelf, RequestWithoutSelf, Out_Ack, Out_EOF_i, ChannelPointer_d, ChannelPointer_nxt) + process(all) begin - NextState <= State; + NextState <= State; - FSM_Dataflow_en <= '0'; + FSM_Dataflow_en <= '0'; - ChannelPointer_en <= '0'; - ChannelPointer <= ChannelPointer_d; + ChannelPointer_en <= '0'; + ChannelPointer <= ChannelPointer_d; case State is when ST_IDLE => if (RequestWithSelf = '1') then - ChannelPointer_en <= '1'; + ChannelPointer_en <= '1'; - NextState <= ST_DATAFLOW; + NextState <= ST_DATAFLOW; end if; when ST_DATAFLOW => - FSM_Dataflow_en <= '1'; + FSM_Dataflow_en <= '1'; if ((Out_Ack and Out_EOF_i) = '1') then if (RequestWithoutSelf = '0') then - NextState <= ST_IDLE; + NextState <= ST_IDLE; else - ChannelPointer_en <= '1'; + ChannelPointer_en <= '1'; end if; end if; end case; @@ -149,44 +150,45 @@ begin begin if rising_edge(Clock) then if (Reset = '1') then - ChannelPointer_d <= to_slv(2 ** (PORTS - 1), PORTS); + ChannelPointer_d <= to_slv(2 ** (PORTS - 1), PORTS); elsif (ChannelPointer_en = '1') then - ChannelPointer_d <= ChannelPointer_nxt; + ChannelPointer_d <= ChannelPointer_nxt; end if; end if; end process; - RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(RequestVector); - SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft; - SelectRight <= (unsigned(not RequestVector) + 1) and unsigned(RequestVector); - ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft)); + RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(RequestVector); + SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft; + SelectRight <= (unsigned(not RequestVector) + 1) and unsigned(RequestVector); + ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft)); - ChannelPointer_bin <= onehot2bin(ChannelPointer); - idx <= to_integer(ChannelPointer_bin); + ChannelPointer_bin <= onehot2bin(ChannelPointer); + idx <= to_integer(ChannelPointer_bin); - Out_Data <= get_row(In_Data, idx); - Out_Meta <= get_row(In_Meta, idx); + Out_Data <= get_row(In_Data, idx); + Out_Meta <= get_row(In_Meta, idx); - Out_SOF <= In_SOF(to_integer(ChannelPointer_bin)); - Out_EOF_i <= In_EOF(to_integer(ChannelPointer_bin)); - Out_Valid <= In_Valid(to_integer(ChannelPointer_bin)) and FSM_Dataflow_en; - Out_EOF <= Out_EOF_i; + Out_SOF <= In_SOF(to_integer(ChannelPointer_bin)); + Out_EOF_i <= In_EOF(to_integer(ChannelPointer_bin)); + Out_Valid <= In_Valid(to_integer(ChannelPointer_bin)) and FSM_Dataflow_en; + Out_EOF <= Out_EOF_i; - In_Ack <= (In_Ack 'range => (Out_Ack and FSM_Dataflow_en)) and ChannelPointer; + In_Ack <= (In_Ack 'range => (Out_Ack and FSM_Dataflow_en)) and ChannelPointer; - genMetaReverse_0 : if META_REV_BITS = 0 generate - In_Meta_rev <= (others => (others => '0')); - end generate; - genMetaReverse_1 : if META_REV_BITS > 0 generate - signal Temp_Meta_rev : T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); + genMetaReverse : if META_REV_BITS = 0 generate + In_Meta_rev <= (others => (others => '0')); + + else generate + signal Temp_Meta_rev : T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); begin + genAssign : for i in 0 to PORTS - 1 generate - signal row : std_logic_vector(META_REV_BITS - 1 downto 0); + signal row : std_logic_vector(META_REV_BITS - 1 downto 0); begin - row <= Out_Meta_rev and (row'range => ChannelPointer(i)); + row <= Out_Meta_rev and (row'range => ChannelPointer(i)); assign_row(Temp_Meta_rev, row, i); end generate; - In_Meta_rev <= Temp_Meta_rev; + In_Meta_rev <= Temp_Meta_rev; end generate; end architecture; diff --git a/src/bus/stream/stream_Source.files b/src/bus/stream/stream_Source.files deleted file mode 100644 index 0d9894414..000000000 --- a/src/bus/stream/stream_Source.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.bus.stream -vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package -vhdl PoC "src/bus/stream/stream_Source.vhdl" # Top-Level diff --git a/src/bus/stream/stream_Source.vhdl b/src/bus/stream/stream_Source.vhdl index 70a9c0aeb..ec87a8401 100644 --- a/src/bus/stream/stream_Source.vhdl +++ b/src/bus/stream/stream_Source.vhdl @@ -24,7 +24,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/src/cache/cache_cpu.files b/src/cache/cache_cpu.files deleted file mode 100644 index 947371709..000000000 --- a/src/cache/cache_cpu.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.cache -include "src/cache/cache_par2.files" # Embedded Cache -vhdl poc "src/cache/cache_cpu.vhdl" # Top Level diff --git a/src/cache/cache_mem.files b/src/cache/cache_mem.files deleted file mode 100644 index 092105b0f..000000000 --- a/src/cache/cache_mem.files +++ /dev/null @@ -1,16 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.fifo -include "src/fifo/fifo_stage.files" -include "src/fifo/fifo_cc_got.files" - -# PoC.cache -include "src/cache/cache_cpu.files" # Embedded CPU Cache -vhdl poc "src/cache/cache_mem.vhdl" # Top Level diff --git a/src/cache/cache_par.files b/src/cache/cache_par.files deleted file mode 100644 index f38d63f5a..000000000 --- a/src/cache/cache_par.files +++ /dev/null @@ -1,16 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.sort -include "src/sort/sort_lru_cache.files" # - -# PoC.cache -vhdl poc "src/cache/cache_replacement_policy.vhdl" -vhdl poc "src/cache/cache_tagunit_par.vhdl" -vhdl poc "src/cache/cache_par.vhdl" # Top Level diff --git a/src/cache/cache_par2.files b/src/cache/cache_par2.files deleted file mode 100644 index eaf2fcc2d..000000000 --- a/src/cache/cache_par2.files +++ /dev/null @@ -1,19 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -include "src/mem/ocram/ocram_sp.files" - -# PoC.sort -include "src/sort/sort_lru_cache.files" - -# PoC.cache -vhdl poc "src/cache/cache_replacement_policy.vhdl" -vhdl poc "src/cache/cache_tagunit_par.vhdl" -vhdl poc "src/cache/cache_par2.vhdl" # Top Level diff --git a/src/comm/comm.pro b/src/comm/comm.pro index f0f869a5c..ab766afa1 100644 --- a/src/comm/comm.pro +++ b/src/comm/comm.pro @@ -1,7 +1,26 @@ # ============================================================================= # Authors: -# Guy Eschemann +# Guy Eschemann, Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= analyze ./comm.pkg.vhdl analyze ./comm_crc.vhdl +analyze ./comm_scramble.vhdl +analyze ./remote/remote_terminal_control.vhdl + diff --git a/src/comm/comm_crc.files b/src/comm/comm_crc.files deleted file mode 100644 index d3681a713..000000000 --- a/src/comm/comm_crc.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.comm -vhdl PoC "src/comm/comm.pkg.vhdl" # PoC.bus package -vhdl PoC "src/comm/comm_crc.vhdl" # Top-Level diff --git a/src/comm/comm_crc.vhdl b/src/comm/comm_crc.vhdl index 2995ec60d..86cf85a0a 100644 --- a/src/comm/comm_crc.vhdl +++ b/src/comm/comm_crc.vhdl @@ -2,10 +2,12 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Thomas B. Preusser --- Patrick Lehmann +-- Authors: Thomas B. Preusser +-- Patrick Lehmann +-- Matthias Sund +-- Stefan Unrein -- --- Entity: Computes the Cyclic Redundancy Check (CRC) +-- Entity: Computes the Cyclic Redundancy Check (CRC) -- -- Description: -- ------------------------------------- @@ -17,16 +19,21 @@ -- message bits per step. The generated CRC is independent from the chosen -- processing width. -- +-- With Chunk-Enable you can enable chunks for calculation. Usually used as +-- Byte-Enables if streamed packets are not multiple of CRC-Size or interface +-- width. Using Chunk-Enables has a significant performance hit, use only if +-- necessary. +-- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, @@ -35,7 +42,7 @@ -- limitations under the License. -- ============================================================================= -library IEEE; +library IEEE; use IEEE.std_logic_1164.all; use work.utils.all; @@ -43,64 +50,81 @@ use work.utils.all; entity comm_crc is generic ( - GEN : bit_vector; -- Generator Polynomial - BITS : positive; -- Number of Bits to be processed in parallel + GEN : bit_vector; -- Generator Polynomial + BITS : positive; -- Number of Bits to be processed in parallel + CHUNK_BITS : positive := BITS; -- Bus width for 'en' port - STARTUP_RMD : std_logic_vector := "0"; - OUTPUT_REGS : boolean := true + STARTUP_RMD : std_logic_vector := "0"; + OUTPUT_REGS : boolean := true ); port ( - clk : in std_logic; -- Clock + clk : in std_logic; -- Clock - set : in std_logic; -- Parallel Preload of Remainder - init : in std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- - step : in std_logic; -- Process Input Data (MSB first) - din : in std_logic_vector(BITS-1 downto 0); -- + set : in std_logic; -- Parallel Preload of Remainder + init : in std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- + step : in std_logic; -- Process Input Data (MSB first) + cen : in std_logic_vector(CHUNK_BITS-1 downto 0) := (CHUNK_BITS-1 downto 0 => '1'); -- Chunck Enable + din : in std_logic_vector(BITS-1 downto 0); - rmd : out std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- Remainder - zero : out std_logic -- Remainder is Zero + rmd : out std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- Remainder + zero : out std_logic -- Remainder is Zero ); -end entity comm_crc; +end entity; architecture rtl of comm_crc is ----------------------------------------------------------------------------- -- Normalizes the generator representation: - -- - into a 'downto 0' index range and - -- - truncating it just below the most significant and so hidden '1'. + -- - into a 'downto 0' index range and + -- - truncating it just below the most significant and so hidden '1'. function normalize(G : bit_vector) return bit_vector is variable GN : bit_vector(G'length-1 downto 0); begin GN := G; for i in GN'left downto 1 loop if GN(i) = '1' then - return GN(i-1 downto 0); + return GN(i-1 downto 0); end if; end loop; report "Cannot use absolute constant as generator." severity failure; - return GN; + return GN; end normalize; + function dcr_check(data_bits:positive; chunk_bits:positive) return positive is + begin + assert data_bits >= chunk_bits + report "Generic 'BITS' must be greater or equal to generic 'CHUNK_BITS'." + severity failure; + assert data_bits mod chunk_bits = 0 + report "Generic 'BITS' must be an integer multiple of generic 'CHUNK_BITS'." + severity failure; + return data_bits / chunk_bits; + end function; + -- Normalized Generator constant GN : std_logic_vector := to_stdlogicvector(normalize(GEN)); + -- data-chunk lengths ratio + constant DCR : positive := dcr_check(BITS, CHUNK_BITS); + -- LFSR Value signal lfsr : std_logic_vector(GN'range) := resize(descend(STARTUP_RMD), GN'length); - signal lfsn : std_logic_vector(GN'range); -- Next Value - signal lfso : std_logic_vector(GN'range); -- Output + signal lfsn : std_logic_vector(GN'range); -- Next Value + signal lfso : std_logic_vector(GN'range); -- Output begin -- Compute next combinational Value - process(lfsr, din) + process(all) variable v : std_logic_vector(lfsr'range); begin v := lfsr; for i in BITS-1 downto 0 loop - v := (v(v'left-1 downto 0) & '0') xor - (GN and (GN'range => (din(i) xor v(v'left)))); + if cen(i/DCR) = '1' then + v := (v(v'left-1 downto 0) & '0') xor (GN and (GN'range => (din(i) xor v(v'left)))); + end if; end loop; lfsn <= v; end process; @@ -119,7 +143,7 @@ begin -- Provide Outputs lfso <= lfsr when OUTPUT_REGS else lfsn; - rmd <= lfso; + rmd <= lfso; zero <= '1' when lfso = (lfso'range => '0') else '0'; end architecture; diff --git a/src/comm/comm_scramble.files b/src/comm/comm_scramble.files deleted file mode 100644 index e93121faf..000000000 --- a/src/comm/comm_scramble.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.comm -vhdl PoC "src/comm/comm.pkg.vhdl" # PoC.bus package -vhdl PoC "src/comm/comm_scramble.vhdl" # Top-Level diff --git a/src/comm/comm_scramble.vhdl b/src/comm/comm_scramble.vhdl index 08c8c17ee..5e120d534 100644 --- a/src/comm/comm_scramble.vhdl +++ b/src/comm/comm_scramble.vhdl @@ -2,9 +2,9 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Thomas B. Preusser +-- Authors: Thomas B. Preusser -- --- Entity: Computes XOR masks for stream scrambling from an LFSR generator. +-- Entity: Computes XOR masks for stream scrambling from an LFSR generator. -- -- Description: -- ------------------------------------- @@ -14,14 +14,15 @@ -- -- License: -- ============================================================================= +-- Copyright 2015-2025 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, @@ -30,70 +31,69 @@ -- limitations under the License. -- ============================================================================= -library IEEE; +library IEEE; use IEEE.std_logic_1164.all; entity comm_scramble is - generic ( - GEN : bit_vector; -- Generator Polynomial (little endian) - BITS : positive -- Width of Mask Bits to be computed in parallel in each step - ); - port ( - clk : in std_logic; -- Clock + generic ( + GEN : bit_vector; -- Generator Polynomial (little endian) + BITS : positive -- Width of Mask Bits to be computed in parallel in each step + ); + port ( + clk : in std_logic; -- Clock - set : in std_logic; -- Set LFSR to value provided on din - din : in std_logic_vector(GEN'length-2 downto 0) := (others => '0'); + set : in std_logic; -- Set LFSR to value provided on din + din : in std_logic_vector(GEN'length-2 downto 0) := (others => '0'); - step : in std_logic; -- Compute a Mask Output - mask : out std_logic_vector(BITS-1 downto 0) - ); + step : in std_logic; -- Compute a Mask Output + mask : out std_logic_vector(BITS-1 downto 0) + ); end entity comm_scramble; architecture rtl of comm_scramble is - ----------------------------------------------------------------------------- - -- Normalizes a generator representation: - -- - into a 'downto 0' index range and - -- - truncating it just below the most significant and so hidden '1'. - function normalize(G : bit_vector) return bit_vector is - variable GN : bit_vector(G'length-1 downto 0); - begin - GN := G; - for i in GN'left downto 1 loop - if GN(i) = '1' then - return GN(i-1 downto 0); - end if; - end loop; - report "Cannot use absolute constant as generator." - severity failure; - end normalize; + ----------------------------------------------------------------------------- + -- Normalizes a generator representation: + -- - into a 'downto 0' index range and + -- - truncating it just below the most significant and so hidden '1'. + function normalize(G : bit_vector) return bit_vector is + variable GN : bit_vector(G'length-1 downto 0); + begin + GN := G; + for i in GN'left downto 1 loop + if GN(i) = '1' then + return GN(i-1 downto 0); + end if; + end loop; + report "PoC.comm_scramble:: Cannot use absolute constant as generator." severity failure; + return "0"; + end function; - -- Normalized Generator - constant GN : bit_vector := normalize(GEN); + -- Normalized Generator + constant GN : bit_vector := normalize(GEN); - -- LFSR Value - signal lfsr : std_logic_vector(GN'range); + -- LFSR Value + signal lfsr : std_logic_vector(GN'range); begin - process(clk) - -- Intermediate LFSR Values for single-bit Steps - variable v : std_logic_vector(lfsr'range); - begin - if rising_edge(clk) then - if set = '1' then - lfsr <= din(lfsr'range); - elsif step = '1' then - v := lfsr; - for i in 0 to BITS-1 loop - mask(i) <= v(v'left); - v := (v(v'left-1 downto 0) & '0') xor - (to_stdlogicvector(GN) and (GN'range => v(v'left))); - end loop; - lfsr <= v; - end if; - end if; - end process; + process(clk) + -- Intermediate LFSR Values for single-bit Steps + variable v : std_logic_vector(lfsr'range); + begin + if rising_edge(clk) then + if set = '1' then + lfsr <= din(lfsr'range); + elsif step = '1' then + v := lfsr; + for i in 0 to BITS-1 loop + mask(i) <= v(v'left); + v := (v(v'left-1 downto 0) & '0') xor (to_stdlogicvector(GN) and (GN'range => v(v'left))); + end loop; + lfsr <= v; + end if; + end if; + end process; end architecture; diff --git a/src/comm/remote/remote_terminal_control.vhdl b/src/comm/remote/remote_terminal_control.vhdl index ba0fa8f09..4b99cac0e 100644 --- a/src/comm/remote/remote_terminal_control.vhdl +++ b/src/comm/remote/remote_terminal_control.vhdl @@ -78,41 +78,41 @@ -- limitations under the License. ------------------------------------------------------------------------------- library IEEE; -use IEEE.std_logic_1164.all; +use IEEE.std_logic_1164.all; -use work.functions.all; +use work.utils.all; entity remote_terminal_control is - generic ( - RESET_COUNT : natural; - PULSE_COUNT : natural; - SWITCH_COUNT : natural; - LIGHT_COUNT : natural; - DIGIT_COUNT : natural; - - COUNT_DECIMAL : boolean := true - ); - port ( - -- Global Control - clk : in std_logic; - rst : in std_logic; - - -- UART Connectivity - idat : in std_logic_vector(6 downto 0); - istb : in std_logic; - odat : out std_logic_vector(6 downto 0); - ordy : in std_logic; - oput : out std_logic; - - -- Control Outputs - resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0); - pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0); - switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0); - - -- Monitor Inputs - lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0); - digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0) - ); + generic ( + RESET_COUNT : natural; + PULSE_COUNT : natural; + SWITCH_COUNT : natural; + LIGHT_COUNT : natural; + DIGIT_COUNT : natural; + + COUNT_DECIMAL : boolean := true + ); + port ( + -- Global Control + clk : in std_logic; + rst : in std_logic; + + -- UART Connectivity + idat : in std_logic_vector(6 downto 0); + istb : in std_logic; + odat : out std_logic_vector(6 downto 0); + ordy : in std_logic; + oput : out std_logic; + + -- Control Outputs + resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0); + pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0); + switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0); + + -- Monitor Inputs + lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0); + digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0) + ); end remote_terminal_control; @@ -121,496 +121,478 @@ use IEEE.numeric_std.all; architecture rtl of remote_terminal_control is - type tKind is (KIND_NONE, - KIND_RESET, KIND_PULSE, KIND_SWITCH, - KIND_LIGHT, KIND_DIGIT); - --constant KIND_NONE : natural := 0; - --constant KIND_RESET : natural := 1; - --constant KIND_PULSE : natural := 2; - --constant KIND_SWITCH : natural := 3; - --constant KIND_LIGHT : natural := 4; - --constant KIND_DIGIT : natural := 5; - --subtype tKind is natural range KIND_NONE to KIND_DIGIT; - subtype tActual is tKind range KIND_RESET to KIND_DIGIT; - subtype tInput is tActual range KIND_RESET to KIND_SWITCH; - subtype tOutput is tActual range KIND_LIGHT to KIND_DIGIT; - - ----------------------------------------------------------------------------- - -- Counts - type tCounts is array(tKind range<>) of natural; - constant COUNTS : tCounts := (0, - RESET_COUNT, PULSE_COUNT, SWITCH_COUNT, - LIGHT_COUNT, 4*DIGIT_COUNT); - function max_count(arr : tCounts) return natural is - -- Without this copy of arr, ISE (as of version 14.7) will choke. - variable a : tCounts(arr'range) := (others => 0); - variable res : natural; - begin - a(arr'range) := arr; - res := 0; - for i in a'range loop - if a(i) > res then - res := a(i); - end if; - end loop; - return res; - end max_count; - - constant PAR_BITS : natural := max_count(COUNTS(tInput)); - constant RES_BITS : natural := max_count(COUNTS(tActual)); - constant ECO_BITS : natural := 4*((RES_BITS+3)/4); - - - function log10ceil(x : natural) return positive is - variable scale, res : positive; - begin - scale := 10; - res := 1; - while x >= scale loop - scale := 10*scale; - res := res+1; - end loop; - return res; - end log10ceil; - function makeCntBits return positive is - begin - if COUNT_DECIMAL then - return 4*log10ceil(RES_BITS); - end if; - return log2ceil(RES_BITS); - end makeCntBits; - - constant CNT_BITS : positive := makeCntBits; - - - subtype tOutCount is unsigned(CNT_BITS-1 downto 0); - type tOutCounts is array(tKind range<>) of tOutCount; - function makeOutCounts return tOutCounts is - variable res : tOutCounts(COUNTS'range); - variable ele : tOutCount; - variable rmd : natural; - begin - for i in COUNTS'range loop - if COUNT_DECIMAL then - rmd := COUNTS(i); - for j in 0 to ele'length/4-1 loop - ele(4*j+3 downto 4*j) := to_unsigned(rmd mod 10, 4); - rmd := rmd/10; - end loop; - else - ele := to_unsigned(COUNTS(i), CNT_BITS); - end if; - res(i) := ele; - end loop; - return res; - end; - constant OUT_COUNTS : tOutCounts(COUNTS'range) := makeOutCounts; - - subtype tCode is std_logic_vector(4 downto 0); - type tCodes is array(tKind range<>) of tCode; - constant CODES : tCodes(tActual) := ("10010", "10000", "10011", "01100", "00100"); - - type tStrobes is array(tKind range<>) of boolean; - constant STROBES : tStrobes(tInput) := (true, true, false); - - signal BufVld : std_logic := '0'; - signal BufCmd : std_logic_vector(4 downto 0) := (others => '-'); - signal BufCnt : unsigned(CNT_BITS-1 downto 0) := (others => '-'); - signal BufEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-'); - signal BufAck : std_logic; + type tKind is (KIND_NONE, + KIND_RESET, KIND_PULSE, KIND_SWITCH, + KIND_LIGHT, KIND_DIGIT); + subtype tActual is tKind range KIND_RESET to KIND_DIGIT; + subtype tInput is tActual range KIND_RESET to KIND_SWITCH; + subtype tOutput is tActual range KIND_LIGHT to KIND_DIGIT; + + ----------------------------------------------------------------------------- + -- Counts + type tCounts is array(tKind range<>) of natural; + constant COUNTS : tCounts := (0, + RESET_COUNT, PULSE_COUNT, SWITCH_COUNT, + LIGHT_COUNT, 4*DIGIT_COUNT); + function max_count(arr : tCounts) return natural is + -- Without this copy of arr, ISE (as of version 14.7) will choke. + variable a : tCounts(arr'range) := (others => 0); + variable res : natural; + begin + a(arr'range) := arr; + res := 0; + for i in a'range loop + if a(i) > res then + res := a(i); + end if; + end loop; + return res; + end function; + + constant PAR_BITS : natural := max_count(COUNTS(tInput)); + constant RES_BITS : natural := max_count(COUNTS(tActual)); + constant ECO_BITS : natural := 4*((RES_BITS+3)/4); + + function makeCntBits return positive is + begin + if COUNT_DECIMAL then + return 4*log10ceil(RES_BITS); + end if; + return log2ceil(RES_BITS); + end function; + + constant CNT_BITS : positive := makeCntBits; + + + subtype tOutCount is unsigned(CNT_BITS-1 downto 0); + type tOutCounts is array(tKind range<>) of tOutCount; + + function makeOutCounts return tOutCounts is + variable res : tOutCounts(COUNTS'range); + variable ele : tOutCount; + variable rmd : natural; + begin + for i in COUNTS'range loop + if COUNT_DECIMAL then + rmd := COUNTS(i); + for j in 0 to ele'length/4-1 loop + ele(4*j+3 downto 4*j) := to_unsigned(rmd mod 10, 4); + rmd := rmd/10; + end loop; + else + ele := to_unsigned(COUNTS(i), CNT_BITS); + end if; + res(i) := ele; + end loop; + return res; + end function; + constant OUT_COUNTS : tOutCounts(COUNTS'range) := makeOutCounts; + + subtype tCode is std_logic_vector(4 downto 0); + type tCodes is array(tKind range<>) of tCode; + constant CODES : tCodes(tActual) := ("10010", "10000", "10011", "01100", "00100"); + + type tStrobes is array(tKind range<>) of boolean; + constant STROBES : tStrobes(tInput) := (true, true, false); + + signal BufVld : std_logic := '0'; + signal BufCmd : std_logic_vector(4 downto 0) := (others => '-'); + signal BufCnt : unsigned(CNT_BITS-1 downto 0) := (others => '-'); + signal BufEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-'); + signal BufAck : std_logic; begin - -- Reading the UART input stream - blkReader: block - - type tState is (Idle, Command); - signal State : tState := Idle; - signal NextState : tState; - - signal Cmd : std_logic_vector(4 downto 0) := (others => '-'); - signal Arg : std_logic_vector(PAR_BITS-1 downto 0) := (others => '-'); - signal Sel : tKind := KIND_NONE; - - signal Load : std_logic; - signal Shift : std_logic; - signal Commit : std_logic; - - subtype tEcho is std_logic_vector(0 to ECO_BITS-1); - type tEchos is array(tKind range<>) of tEcho; - signal echos : tEchos(tKind); - - function leftAlignedBCD(x : std_logic_vector) return tEcho is - constant MY_BITS : positive := 4*((x'length+3)/4); - variable res : tEcho; - begin - res := (others => '-'); - res(0 to 3) := x"0"; - res(MY_BITS-x'length to MY_BITS-1) := x; - return res; - end leftAlignedBCD; - - begin - -- State Registers - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - State <= Idle; - Cmd <= (others => '-'); - Arg <= (others => '-'); - else - State <= NextState; - - if Load = '1' then - Cmd <= idat(4 downto 0); - Arg <= (others => '0'); - - Sel <= KIND_NONE; - for i in CODES'range loop - if CODES(i) = idat(4 downto 0) then - Sel <= i; - end if; - end loop; - - elsif Shift = '1' then - Arg <= Arg(Arg'left-4 downto 0) & - std_logic_vector(unsigned(idat(3 downto 0)) + (idat(6)&"00"&idat(6))); - end if; - end if; - end if; - end process; - - -- Common Reader State Machine - process(State, istb, idat) - begin - NextState <= State; - - Load <= '0'; - Shift <= '0'; - Commit <= '0'; - - if istb = '1' then - case State is - when Idle => - if idat(6) = '1' then - Load <= '1'; - NextState <= Command; - end if; - - when Command => - if idat(6) = '1' or (idat(5) = '1' and idat(4) = '1') then - Shift <= '1'; - elsif idat(6) = '0' and idat(5) = '0' and idat(4) = '0' then - Commit <= '1'; - NextState <= Idle; - end if; - - end case; - end if; - end process; - - echos(KIND_NONE) <= (others => '-'); - - -- Generate Control Inputs - genInputs: for i in tInput generate - - -- Control not used - genNone: if COUNTS(i) = 0 generate - genReset: if i = KIND_RESET generate - resets <= "X"; - end generate genReset; - genPulse: if i = KIND_PULSE generate - pulses <= "X"; - end generate genPulse; - genSwitch: if i = KIND_SWITCH generate - switches <= "X"; - end generate genSwitch; - echos(i) <= (others => '-'); - end generate genNone; - - -- Controls available - genAvail: if COUNTS(i) > 0 generate - signal Outputs : std_logic_vector(COUNTS(i)-1 downto 0) := (others => '0'); - signal onxt : std_logic_vector(Outputs'range); - begin - - -- Output Computation: Strobed - genStrobed: if STROBES(i) generate - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - Outputs <= (others => '0'); - else - if Commit = '1' and Sel = i then - Outputs <= onxt; - else - Outputs <= (others => '0'); - end if; - end if; - end if; - end process; - onxt <= Arg(Outputs'range); - end generate genStrobed; - - -- Output Computation: State - genState: if not STROBES(i) generate - process(clk) - begin - if rising_edge(clk) then - if Commit = '1' and Sel = i then - Outputs <= onxt; - end if; - end if; - end process; - onxt <= Outputs xor Arg(Outputs'range); - end generate genState; - echos(i) <= leftAlignedBCD(onxt); - - -- Assign to Output Pins - genReset: if i = KIND_RESET generate - resets <= Outputs; - end generate genReset; - genPulse: if i = KIND_PULSE generate - pulses <= Outputs; - end generate genPulse; - genSwitch: if i = KIND_SWITCH generate - switches <= Outputs; - end generate genSwitch; - end generate genAvail; - - end generate genInputs; - - process(lights, digits) - begin - echos(KIND_LIGHT) <= (others => '-'); - echos(KIND_DIGIT) <= (others => '-'); - if LIGHT_COUNT > 0 then - echos(KIND_LIGHT) <= leftAlignedBCD(lights); - end if; - if DIGIT_COUNT > 0 then - echos(KIND_DIGIT) <= leftAlignedBCD(digits); - end if; - end process; - - -- Build Data Record for Writer - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - BufVld <= '0'; - BufCmd <= (others => '-'); - BufCnt <= (others => '-'); - BufEco <= (others => '-'); - else - if Commit = '1' then - BufVld <= '1'; - BufCmd <= Cmd; - BufCnt <= OUT_COUNTS(Sel); - BufEco <= echos(Sel); - elsif BufAck = '1' then - BufVld <= '0'; - BufCmd <= (others => '-'); - BufCnt <= (others => '-'); - BufEco <= (others => '-'); - end if; - end if; - end if; - end process; - - end block blkReader; - - blkWrite: block - - type tState is (Idle, OutCommand, OutCount, OutTick, OutEcho, OutEOL); - signal State : tState := Idle; - signal NextState : tState; - - signal OutCmd : std_logic_vector(4 downto 0) := (others => '-'); - signal OutCnt : unsigned(4*((BufCnt'length+3)/4)-1 downto 0) := (others => '-'); - signal OutEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-'); - - signal Locked : std_logic := '-'; - signal NextLocked : std_logic; - signal OutCntDone : std_logic; - signal OutCntDecr : unsigned(2 downto 0); - signal NextOutCnt : unsigned(OutCnt'length downto 0); - - signal ShiftCnt : std_logic; - signal ShiftEco : std_logic; - - begin - - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - State <= Idle; - - OutCmd <= (others => '-'); - OutCnt <= (others => '-'); - OutEco <= (others => '-'); - Locked <= '-'; - - else - State <= NextState; - - if BufAck = '1' then - OutCmd <= BufCmd; - OutCnt <= (others => '0'); - OutCnt(BufCnt'length-1 downto 0) <= unsigned(BufCnt); - OutEco <= BufEco; - Locked <= '0'; - else - - -- OutCnt Register - if OutCnt'length > 4 and ShiftCnt = '1' then - OutCnt <= OutCnt(OutCnt'left-4 downto 0) & OutCnt(OutCnt'left downto OutCnt'left-3); - else - OutCnt <= NextOutCnt(OutCnt'range); - end if; - Locked <= NextLocked; - - -- OutEco Register - if ShiftEco = '1' then - OutEco <= OutEco(4 to OutEco'right) & "----"; - end if; - - end if; - end if; - end if; - end process; - NextLocked <= 'X' when Is_x(std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3))) else - '1' when OutCnt(OutCnt'left downto OutCnt'left-3) /= x"0" else - Locked; - - genSingleDig: if OutCnt'length = 4 generate - OutCntDone <= '1'; - end generate; - genMultiDig: if OutCnt'length > 4 generate - signal Cnt : unsigned(log2ceil(OutCnt'length/4)-1 downto 0) := (others => '-'); - begin - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - Cnt <= (others => '-'); - else - if BufAck = '1' then - Cnt <= (others => '0'); - elsif ShiftCnt = '1' then - Cnt <= Cnt + 1; - end if; - end if; - end if; - end process; - OutCntDone <= 'X' when Is_X(std_logic_vector(Cnt)) else - '1' when (Cnt or not to_unsigned(OutCnt'length/4-1, Cnt'length)) = (Cnt'range => '1') else - '0'; - end generate; - - genDec: if COUNT_DECIMAL generate - process(OutCnt, OutCntDecr) - variable sub : unsigned(2 downto 0); - variable d : unsigned(4 downto 0); - begin - sub := OutCntDecr; - for i in 0 to OutCnt'length/4-1 loop - d := ('0'&OutCnt(4*i+3 downto 4*i)) - sub; - if d(4) = '0' then - NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0); - sub := to_unsigned(0, sub'length); - else - NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0) - 6; - sub := to_unsigned(1, sub'length); - end if; - end loop; - NextOutCnt(OutCnt'length) <= sub(0); - end process; - end generate genDec; - genHex: if not COUNT_DECIMAL generate - NextOutCnt <= ('0'&OutCnt) - OutCntDecr; - end generate genHex; - - process(State, ordy, BufVld, OutCmd, OutCnt, OutEco, OutCntDone, NextLocked, NextOutCnt) - begin - - NextState <= State; - - BufAck <= '0'; - ShiftCnt <= '0'; - ShiftEco <= '0'; - OutCntDecr <= (others => '0'); - - odat <= (others => '-'); - oput <= '0'; - - case State is - when Idle => - if BufVld = '1' then - BufAck <= '1'; - NextState <= OutCommand; - end if; - - when OutCommand => - odat <= "10" & OutCmd; - oput <= '1'; - if ordy = '1' then - NextState <= OutCount; - end if; - - when OutCount => - if COUNT_DECIMAL or OutCnt(OutCnt'left downto OutCnt'left-3) < 10 then - odat <= "011" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)); - else - odat <= "100" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)+7); - end if; - oput <= NextLocked; - if ordy = '1' then - ShiftCnt <= '1'; - if OutCntDone = '1' then - if NextLocked = '1' then - NextState <= OutTick; - else - NextState <= OutEOL; - end if; - end if; - end if; - - when OutTick => - odat <= "0100111"; - oput <= '1'; - if ordy = '1' then - OutCntDecr <= to_unsigned(1, OutCntDecr'length); - NextState <= OutEcho; - end if; - - when OutEcho => - if unsigned(OutEco(0 to 3)) < 10 then - odat <= "011" & OutEco(0 to 3); - else - odat <= "100" & std_logic_vector(unsigned(OutEco(0 to 3))+7); - end if; - oput <= '1'; - if ordy = '1' then - ShiftEco <= '1'; - OutCntDecr <= "100"; - if NextOutCnt(OutCnt'length) = '1' then - NextState <= OutEOL; - end if; - end if; - - when OutEOL => - odat <= "0001010"; - oput <= '1'; - if ordy = '1' then - NextState <= Idle; - end if; - - end case; - end process; - - end block blkWrite; - -end rtl; + -- Reading the UART input stream + blkReader: block + + type tState is (Idle, Command); + signal State : tState := Idle; + signal NextState : tState; + + signal Cmd : std_logic_vector(4 downto 0) := (others => '-'); + signal Arg : std_logic_vector(PAR_BITS-1 downto 0) := (others => '-'); + signal Sel : tKind := KIND_NONE; + + signal Load : std_logic; + signal Shift : std_logic; + signal Commit : std_logic; + + subtype tEcho is std_logic_vector(0 to ECO_BITS-1); + type tEchos is array(tKind range<>) of tEcho; + signal echos : tEchos(tKind); + + function leftAlignedBCD(x : std_logic_vector) return tEcho is + constant MY_BITS : positive := 4*((x'length+3)/4); + variable res : tEcho; + begin + res := (others => '-'); + res(0 to 3) := x"0"; + res(MY_BITS-x'length to MY_BITS-1) := x; + return res; + end leftAlignedBCD; + + begin + -- State Registers + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + State <= Idle; + Cmd <= (others => '-'); + Arg <= (others => '-'); + else + State <= NextState; + + if Load = '1' then + Cmd <= idat(4 downto 0); + Arg <= (others => '0'); + + Sel <= KIND_NONE; + for i in CODES'range loop + if CODES(i) = idat(4 downto 0) then + Sel <= i; + end if; + end loop; + + elsif Shift = '1' then + Arg <= Arg(Arg'left-4 downto 0) & + std_logic_vector(unsigned(idat(3 downto 0)) + (idat(6)&"00"&idat(6))); + end if; + end if; + end if; + end process; + + -- Common Reader State Machine + process(State, istb, idat) + begin + NextState <= State; + + Load <= '0'; + Shift <= '0'; + Commit <= '0'; + + if istb = '1' then + case State is + when Idle => + if idat(6) = '1' then + Load <= '1'; + NextState <= Command; + end if; + + when Command => + if idat(6) = '1' or (idat(5) = '1' and idat(4) = '1') then + Shift <= '1'; + elsif idat(6) = '0' and idat(5) = '0' and idat(4) = '0' then + Commit <= '1'; + NextState <= Idle; + end if; + + end case; + end if; + end process; + + echos(KIND_NONE) <= (others => '-'); + + -- Generate Control Inputs + genInputs: for i in tInput generate + + -- Control not used + genNone: if COUNTS(i) = 0 generate + genReset: if i = KIND_RESET generate + resets <= "X"; + end generate genReset; + genPulse: if i = KIND_PULSE generate + pulses <= "X"; + end generate genPulse; + genSwitch: if i = KIND_SWITCH generate + switches <= "X"; + end generate genSwitch; + echos(i) <= (others => '-'); + end generate genNone; + + -- Controls available + genAvail: if COUNTS(i) > 0 generate + signal Outputs : std_logic_vector(COUNTS(i)-1 downto 0) := (others => '0'); + signal onxt : std_logic_vector(Outputs'range); + begin + + -- Output Computation: Strobed + genStrobed: if STROBES(i) generate + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + Outputs <= (others => '0'); + else + if Commit = '1' and Sel = i then + Outputs <= onxt; + else + Outputs <= (others => '0'); + end if; + end if; + end if; + end process; + onxt <= Arg(Outputs'range); + end generate genStrobed; + + -- Output Computation: State + genState: if not STROBES(i) generate + process(clk) + begin + if rising_edge(clk) then + if Commit = '1' and Sel = i then + Outputs <= onxt; + end if; + end if; + end process; + onxt <= Outputs xor Arg(Outputs'range); + end generate genState; + echos(i) <= leftAlignedBCD(onxt); + + -- Assign to Output Pins + genReset: if i = KIND_RESET generate + resets <= Outputs; + end generate genReset; + genPulse: if i = KIND_PULSE generate + pulses <= Outputs; + end generate genPulse; + genSwitch: if i = KIND_SWITCH generate + switches <= Outputs; + end generate genSwitch; + end generate genAvail; + + end generate genInputs; + + process(lights, digits) + begin + echos(KIND_LIGHT) <= (others => '-'); + echos(KIND_DIGIT) <= (others => '-'); + if LIGHT_COUNT > 0 then + echos(KIND_LIGHT) <= leftAlignedBCD(lights); + end if; + if DIGIT_COUNT > 0 then + echos(KIND_DIGIT) <= leftAlignedBCD(digits); + end if; + end process; + + -- Build Data Record for Writer + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + BufVld <= '0'; + BufCmd <= (others => '-'); + BufCnt <= (others => '-'); + BufEco <= (others => '-'); + else + if Commit = '1' then + BufVld <= '1'; + BufCmd <= Cmd; + BufCnt <= OUT_COUNTS(Sel); + BufEco <= echos(Sel); + elsif BufAck = '1' then + BufVld <= '0'; + BufCmd <= (others => '-'); + BufCnt <= (others => '-'); + BufEco <= (others => '-'); + end if; + end if; + end if; + end process; + + end block blkReader; + + blkWrite: block + + type tState is (Idle, OutCommand, OutCount, OutTick, OutEcho, OutEOL); + signal State : tState := Idle; + signal NextState : tState; + + signal OutCmd : std_logic_vector(4 downto 0) := (others => '-'); + signal OutCnt : unsigned(4*((BufCnt'length+3)/4)-1 downto 0) := (others => '-'); + signal OutEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-'); + + signal Locked : std_logic := '-'; + signal NextLocked : std_logic; + signal OutCntDone : std_logic; + signal OutCntDecr : unsigned(2 downto 0); + signal NextOutCnt : unsigned(OutCnt'length downto 0); + + signal ShiftCnt : std_logic; + signal ShiftEco : std_logic; + + begin + + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + State <= Idle; + + OutCmd <= (others => '-'); + OutCnt <= (others => '-'); + OutEco <= (others => '-'); + Locked <= '-'; + + else + State <= NextState; + + if BufAck = '1' then + OutCmd <= BufCmd; + OutCnt <= (others => '0'); + OutCnt(BufCnt'length-1 downto 0) <= unsigned(BufCnt); + OutEco <= BufEco; + Locked <= '0'; + else + + -- OutCnt Register + if OutCnt'length > 4 and ShiftCnt = '1' then + OutCnt <= OutCnt(OutCnt'left-4 downto 0) & OutCnt(OutCnt'left downto OutCnt'left-3); + else + OutCnt <= NextOutCnt(OutCnt'range); + end if; + Locked <= NextLocked; + + -- OutEco Register + if ShiftEco = '1' then + OutEco <= OutEco(4 to OutEco'right) & "----"; + end if; + + end if; + end if; + end if; + end process; + NextLocked <= 'X' when Is_x(std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3))) else + '1' when OutCnt(OutCnt'left downto OutCnt'left-3) /= x"0" else + Locked; + + genSingleDig: if OutCnt'length = 4 generate + OutCntDone <= '1'; + end generate; + genMultiDig: if OutCnt'length > 4 generate + signal Cnt : unsigned(log2ceil(OutCnt'length/4)-1 downto 0) := (others => '-'); + begin + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + Cnt <= (others => '-'); + else + if BufAck = '1' then + Cnt <= (others => '0'); + elsif ShiftCnt = '1' then + Cnt <= Cnt + 1; + end if; + end if; + end if; + end process; + OutCntDone <= 'X' when Is_X(std_logic_vector(Cnt)) else + '1' when (Cnt or not to_unsigned(OutCnt'length/4-1, Cnt'length)) = (Cnt'range => '1') else + '0'; + end generate; + + genDec: if COUNT_DECIMAL generate + process(OutCnt, OutCntDecr) + variable sub : unsigned(2 downto 0); + variable d : unsigned(4 downto 0); + begin + sub := OutCntDecr; + for i in 0 to OutCnt'length/4-1 loop + d := ('0'&OutCnt(4*i+3 downto 4*i)) - sub; + if d(4) = '0' then + NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0); + sub := to_unsigned(0, sub'length); + else + NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0) - 6; + sub := to_unsigned(1, sub'length); + end if; + end loop; + NextOutCnt(OutCnt'length) <= sub(0); + end process; + end generate genDec; + genHex: if not COUNT_DECIMAL generate + NextOutCnt <= ('0'&OutCnt) - OutCntDecr; + end generate genHex; + + process(State, ordy, BufVld, OutCmd, OutCnt, OutEco, OutCntDone, NextLocked, NextOutCnt) + begin + + NextState <= State; + + BufAck <= '0'; + ShiftCnt <= '0'; + ShiftEco <= '0'; + OutCntDecr <= (others => '0'); + + odat <= (others => '-'); + oput <= '0'; + + case State is + when Idle => + if BufVld = '1' then + BufAck <= '1'; + NextState <= OutCommand; + end if; + + when OutCommand => + odat <= "10" & OutCmd; + oput <= '1'; + if ordy = '1' then + NextState <= OutCount; + end if; + + when OutCount => + if COUNT_DECIMAL or OutCnt(OutCnt'left downto OutCnt'left-3) < 10 then + odat <= "011" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)); + else + odat <= "100" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)+7); + end if; + oput <= NextLocked; + if ordy = '1' then + ShiftCnt <= '1'; + if OutCntDone = '1' then + if NextLocked = '1' then + NextState <= OutTick; + else + NextState <= OutEOL; + end if; + end if; + end if; + + when OutTick => + odat <= "0100111"; + oput <= '1'; + if ordy = '1' then + OutCntDecr <= to_unsigned(1, OutCntDecr'length); + NextState <= OutEcho; + end if; + + when OutEcho => + if unsigned(OutEco(0 to 3)) < 10 then + odat <= "011" & OutEco(0 to 3); + else + odat <= "100" & std_logic_vector(unsigned(OutEco(0 to 3))+7); + end if; + oput <= '1'; + if ordy = '1' then + ShiftEco <= '1'; + OutCntDecr <= "100"; + if NextOutCnt(OutCnt'length) = '1' then + NextState <= OutEOL; + end if; + end if; + + when OutEOL => + odat <= "0001010"; + oput <= '1'; + if ordy = '1' then + NextState <= Idle; + end if; + + end case; + end process; + + end block blkWrite; + +end architecture; diff --git a/src/common/common.files b/src/common/common.files deleted file mode 100644 index a49fce70a..000000000 --- a/src/common/common.files +++ /dev/null @@ -1,32 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC config packages -include "tb/common/my_config.files" # board and device configuration - -# PoC core packages -vhdl poc "src/common/utils.vhdl" # PoC utility collection -vhdl poc "src/common/config.vhdl" # PoC device configuration mechanism -vhdl poc "src/common/math.vhdl" # PoC math extension package -vhdl poc "src/common/strings.vhdl" # PoC string package -vhdl poc "src/common/vectors.vhdl" # PoC vector package -vhdl poc "src/common/physical.vhdl" # PoC physical types package -vhdl poc "src/common/components.vhdl" # PoC components - -if (ToolChain not in ["Altera_QuartusII", "Lattice_Diamond"]) then - if (VHDLVersion < 2002) then - vhdl poc "src/common/fileio.v93.vhdl" # - elseif (VHDLVersion <= 2008) then - vhdl poc "src/common/protected.v08.vhdl" # PoC protected type implementations - vhdl poc "src/common/fileio.v08.vhdl" # - else - report "VHDL version not supported." - end if -end if - -if (Environment = "Simulation") then - include "src/sim/sim.files" # Simulation packages -end if diff --git a/src/common/common.pro b/src/common/common.pro index ad33c1308..179f83203 100644 --- a/src/common/common.pro +++ b/src/common/common.pro @@ -1,14 +1,29 @@ # ============================================================================= -# Authors: -# Adrian Weiland +# Authors: Adrian Weiland +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= analyze utils.vhdl analyze config.vhdl analyze strings.vhdl analyze debug.vhdl -# analyze fileio.v08.vhdl -# analyze fileio.v93.vhdl +analyze protected.v08.vhdl analyze math.vhdl analyze vectors.vhdl analyze physical.vhdl diff --git a/src/common/components.vhdl b/src/common/components.vhdl index 15303ec2a..bc227bff0 100644 --- a/src/common/components.vhdl +++ b/src/common/components.vhdl @@ -63,7 +63,7 @@ package components is function upcounter_next( cnt : unsigned; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return unsigned; function upcounter_equal( cnt : unsigned; value : natural) return std_logic; function downcounter_next( cnt : signed; init : unsigned; rst : std_logic := '0'; en : std_logic := '1') return signed; - function downcounter_next( cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed; + function downcounter_next( cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return signed; function downcounter_equal(cnt : signed; value : integer) return std_logic; function downcounter_neg( cnt : signed) return std_logic; @@ -208,8 +208,12 @@ package body components is end if; end function; - function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : integer := 0) return signed is + function downcounter_next(cnt : signed; rst : std_logic := '0'; en : std_logic := '1'; constant INIT : natural := 0) return signed is begin + if INIT > 0 then + assert (log2ceil(INIT) +1) <= (cnt'length -1) report "PoC.components.downcounter_next: INIT overflows the counter sizes!" severity failure; + end if; + if (rst = '1') then return to_signed(INIT, cnt'length); elsif (en = '1') then diff --git a/src/common/fileio.v08.vhdl b/src/common/fileio.v08.vhdl deleted file mode 100644 index 5a353187c..000000000 --- a/src/common/fileio.v08.vhdl +++ /dev/null @@ -1,254 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Package: File I/O-related Functions. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use STD.TextIO.all; - -use work.my_project.all; -use work.utils.all; -use work.strings.all; -use work.ProtectedTypes.all; - - -package FileIO is - subtype T_LOGFILE_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE; - - -- Constant declarations - constant C_LINEBREAK : string; - - -- =========================================================================== - type T_LOGFILE is protected - procedure OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - impure function OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS; - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - impure function IsOpen return boolean; - procedure CloseFile; - - procedure Print(str : string); - procedure PrintLine(str : string := ""); - procedure Flush; - -- procedure WriteLine(LineBuffer : inout LINE); - end protected; - - -- =========================================================================== - type T_FILE is protected - procedure OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE); - impure function OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS; - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE); - impure function IsOpen return boolean; - procedure CloseFile; - - procedure Print(str : string); - procedure PrintLine(str : string := ""); - procedure Flush; - -- procedure WriteLine(LineBuffer : inout LINE); - end protected; - - type T_STDOUT is protected - procedure Print(str : string); - procedure PrintLine(str : string := ""); - procedure Flush; - end protected; -end package; - - -package body FileIO is - constant C_LINEBREAK : string := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF)); - - -- =========================================================================== - file Global_LogFile : TEXT; - -- shared variable LogFile_IsOpen : P_BOOLEAN; - -- shared variable LogFile : T_LOGFILE; - -- shared variable StdOut : T_STDOUT; - -- shared variable LogFile_IsMirrored : P_BOOLEAN; - - -- =========================================================================== - type T_LOGFILE is protected body - variable LineBuffer : LINE; - variable Local_IsOpen : boolean; - variable Local_FileName : string(1 to 256); - - procedure OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is - variable Status : FILE_OPEN_STATUS; - begin - OpenFile(Status, FileName, OpenKind); - end procedure; - - impure function OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is - variable Status : FILE_OPEN_STATUS; - begin - OpenFile(Status, FileName, OpenKind); - return Status; - end function; - - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is - variable Status_i : FILE_OPEN_STATUS; - begin - if not Local_IsOpen then - file_open(Status_i, Global_LogFile, FileName, OpenKind); - Local_IsOpen := Status_i = OPEN_OK; - Local_FileName := resize(FileName, Local_FileName'length); - Status := Status_i; - else - report "Global log file '" & str_trim(Local_FileName) & "' is already open." severity ERROR; - end if; - end procedure; - - impure function IsOpen return boolean is - begin - return Local_IsOpen; - end function; - - procedure CloseFile is - begin - if Local_IsOpen then - file_close(Global_LogFile); - Local_IsOpen := FALSE; - end if; - end procedure; - - procedure WriteLine(LineBuffer : inout LINE) is - begin - if not Local_IsOpen then - writeline(OUTPUT, LineBuffer); - -- elsif (LogFile_IsMirrored.Get = TRUE) then - -- tee(Global_LogFile, LineBuffer); - else - writeline(Global_LogFile, LineBuffer); - end if ; - end procedure; - - procedure Print(str : string) is - begin - write(LineBuffer, str); - end procedure; - - procedure PrintLine(str : string := "") is - begin - write(LineBuffer, str); - WriteLine(LineBuffer); - end procedure; - - procedure Flush is - begin - WriteLine(LineBuffer); - end procedure; - end protected body; - - type T_FILE is protected body - file LocalFile : TEXT; - variable LineBuffer : LINE; - variable Local_IsOpen : boolean; - variable Local_FileName : string(1 to 256); - - procedure OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is - variable Status : FILE_OPEN_STATUS; - begin - OpenFile(Status, FileName, OpenKind); - end procedure; - - impure function OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is - variable Status : FILE_OPEN_STATUS; - begin - OpenFile(Status, FileName, OpenKind); - return Status; - end function; - - impure function IsOpen return boolean is - begin - return Local_IsOpen; - end function; - - procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is - variable Status_i : FILE_OPEN_STATUS; - begin - if not Local_IsOpen then - file_open(Status_i, LocalFile, FileName, OpenKind); - Local_IsOpen := Status_i = OPEN_OK; - Local_FileName := resize(FileName, Local_FileName'length); - Status := Status_i; - else - report "File '" & str_trim(Local_FileName) & "' is already open." severity ERROR; - end if; - end procedure; - - procedure CloseFile is - begin - if Local_IsOpen then - file_close(LocalFile); - Local_IsOpen := FALSE; - end if; - end procedure; - - procedure WriteLine(LineBuffer : inout LINE) is - begin - if not Local_IsOpen then - report "File is not open." severity ERROR; - else - writeline(LocalFile, LineBuffer); - end if ; - end procedure; - - procedure Print(str : string) is - begin - write(LineBuffer, str); - end procedure; - - procedure PrintLine(str : string := "") is - begin - write(LineBuffer, str); - WriteLine(LineBuffer); - end procedure; - - procedure Flush is - begin - WriteLine(LineBuffer); - end procedure; - end protected body; - - type T_STDOUT is protected body - variable LineBuffer : LINE; - - procedure Print(str : string) is - begin - write(LineBuffer, str); - end procedure; - - procedure PrintLine(str : string := "") is - begin - write(LineBuffer, str); - writeline(OUTPUT, LineBuffer); - end procedure; - - procedure Flush is - begin - writeline(OUTPUT, LineBuffer); - end procedure; - end protected body; -end package body; diff --git a/src/common/fileio.v93.vhdl b/src/common/fileio.v93.vhdl deleted file mode 100644 index 38fdf3d97..000000000 --- a/src/common/fileio.v93.vhdl +++ /dev/null @@ -1,143 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- Thomas B. Preusser --- --- Package: File I/O-related Functions. --- --- Description: --- ------------------------------------- --- Exploring the options for providing a more convenient API than std.textio. --- Not yet recommended for adoption as it depends on the VHDL generation and --- still is under discussion. --- --- Open problems: --- - verify that std.textio.write(text, string) is, indeed, specified and --- that it does *not* print a trailing \newline --- -> would help to eliminate line buffering in shared variables --- - move C_LINEBREAK to my_config to keep platform dependency out? --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use STD.TextIO.all; - -use work.my_project.all; -use work.strings.all; -use work.utils.all; - - -package FileIO is - -- Constant declarations - constant C_LINEBREAK : string; - - - -- Log file - -- =========================================================================== - subtype T_LOGFILE_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE; - - procedure LogFile_Open(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - procedure LogFile_Open(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE); - impure function LogFile_IsOpen return boolean; - procedure LogFile_Print(str : string); - procedure LogFile_PrintLine(str : string := ""); - procedure LogFile_Flush; - procedure LogFile_Close; - - -- StdOut - -- =========================================================================== - procedure StdOut_Print(str : string); - procedure StdOut_PrintLine(str : string := ""); - procedure StdOut_Flush; - -end package; - - -package body FileIO is - constant C_LINEBREAK : string := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF)); - - -- =========================================================================== - file LogFile_FileHandle : TEXT; - shared variable LogFile_State_IsOpen : boolean := FALSE; - shared variable LogFile_LineBuffer : LINE; - - procedure LogFile_Open(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is - variable OpenStatus : FILE_OPEN_STATUS; - begin - LogFile_Open(OpenStatus, FileName, OpenKind); - end procedure; - - procedure LogFile_Open(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is - variable OpenStatus : FILE_OPEN_STATUS; - begin - file_open(OpenStatus, LogFile_FileHandle, FileName, OpenKind); - LogFile_State_IsOpen := OpenStatus = OPEN_OK; - Status := OpenStatus; - end procedure; - - impure function LogFile_IsOpen return boolean is - begin - return LogFile_State_IsOpen; - end function; - - procedure LogFile_Print(str : string) is - begin - write(LogFile_LineBuffer, str); - end procedure; - - procedure LogFile_PrintLine(str : string := "") is - begin - write(LogFile_LineBuffer, str); - writeline(LogFile_FileHandle, LogFile_LineBuffer); - end procedure; - - procedure LogFile_Flush is - begin - writeline(LogFile_FileHandle, LogFile_LineBuffer); - end procedure; - - procedure LogFile_Close is - begin - if LogFile_State_IsOpen then - file_close(LogFile_FileHandle); - LogFile_State_IsOpen := FALSE; - end if; - end procedure; - - -- =========================================================================== - shared variable StdOut_LineBuffer : line; - - procedure StdOut_Print(str : string) is - begin - write(StdOut_LineBuffer, str); - end procedure; - - procedure StdOut_PrintLine(str : string := "") is - begin - write(StdOut_LineBuffer, str); - writeline(OUTPUT, StdOut_LineBuffer); - end procedure; - - procedure StdOut_Flush is - begin - writeline(OUTPUT, StdOut_LineBuffer); - end procedure; - -end package body; diff --git a/src/common/math.vhdl b/src/common/math.vhdl index 1e70a5639..bd4891306 100644 --- a/src/common/math.vhdl +++ b/src/common/math.vhdl @@ -14,7 +14,7 @@ -- License: -- ============================================================================= -- Copyright 2025-2025 The PoC-Library Authors --- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -123,6 +123,7 @@ package body math is -- calculate fraction of positive float and give out as vector of integers function fract(F : real; maxDenominator : natural := 1000; maxError : real := 1.0E-6) return T_FRACTIONAL is constant fulls : integer := integer(trunc(F)); + constant divByOne : real := 1.0 / F; constant remainder : real := ite(F >= 0.0, F - trunc(F), -F - trunc(-F)); variable numerator : natural := 0; variable denominator : natural := 1; @@ -131,14 +132,24 @@ package body math is variable result : T_FRACTIONAL := (whole => fulls, denominator => 1, numerator => 0); variable bestError : real := remainder; begin + if fulls = 0 then -- precalculate values to avoid infinite loop errors + numerator := 1; + denominator := integer(divByOne); + newFraction := real(numerator) / real(denominator); + Error := REALMAX(remainder, newFraction) - REALMIN(remainder, newFraction); + bestError := Error; + result.numerator := numerator; + result.denominator := denominator; + end if; + while (Error > maxError) and (denominator < maxDenominator) loop if newFraction > remainder then - denominator := denominator +1; - numerator := numerator -1; + denominator := denominator + 1; + numerator := numerator - 1; elsif (numerator +1) = denominator then - denominator := denominator +1; + denominator := denominator + 1; else - numerator := numerator +1; + numerator := numerator + 1; end if; newFraction := real(numerator) / real(denominator); @@ -149,24 +160,23 @@ package body math is result.denominator := denominator; end if; end loop; - assert (bestError < maxError) report "Didn't find suitable fraction for F=" & real'image(F) & "! Target Error=" & real'image(maxError) & " Actual Error=" & real'image(bestError) & "!" severity failure; - if result.numerator = 0 and result.denominator = 1 then - result.whole := fulls -1; - result.numerator := 1; - result.denominator := 1; - end if; + assert (bestError < maxError) report "Didn't find suitable fraction for F=" & real'image(F) & "! Target Error=" & real'image(maxError) & " Actual Error=" & real'image(bestError) & "!" severity failure; return result; end function; -- calculate time increments to met fraction function fract2timing(numerator : natural; denominator : natural) return T_NATVEC is - constant fractionalInReal: real := real(numerator) / real(denominator); + constant fractionalInReal: real := real(numerator) / real(denominator); + constant zeroes : T_NATVEC(0 to 0) := (others => 0); variable actualNumerator : natural := 1; variable tab : natural := 0; variable increment : real := fractionalInReal; variable remainder : real := fractionalInReal; variable result : T_NATVEC(0 to numerator -1) := (others => 0); begin + if numerator = 0 then + return zeroes; + end if; while actualNumerator <= denominator -1 loop if remainder >= 1.0 then result(tab) := actualNumerator; diff --git a/src/common/my_config.vhdl.template b/src/common/my_config.vhdl.template index 8374c9d02..a125b7ba5 100644 --- a/src/common/my_config.vhdl.template +++ b/src/common/my_config.vhdl.template @@ -7,25 +7,25 @@ -- Martin Zabel -- Patrick Lehmann -- --- Package: Project specific configuration. +-- Package: Project specific configuration. -- -- Description: -- ------------------------------------ --- This is a template file. +-- This is a template file. -- --- The global packages common/config and common/board evaluate the settings --- declared in this file. +-- The global packages common/config and common/board evaluate the settings +-- declared in this file. -- --- USAGE: --- 1) Copy this file into your project's source directory and rename it to --- "my_config.vhdl". --- 2) Add file to library "PoC" in your synthesis tool. --- 3) Change setup appropriately. +-- USAGE: +-- 1) Copy this file into your project's source directory and rename it to +-- "my_config.vhdl". +-- 2) Add file to library "PoC" in your synthesis tool. +-- 3) Change setup appropriately. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, --- Chair for VLSI-Design, Diagnostics and Architecture +-- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. @@ -44,7 +44,7 @@ package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys - constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 + constant MY_DEVICE : string := "CHANGE THIS"; -- e.g. GENERIC, XC5VLX50T-1FF1136, EP2SGX90FF1508C3 -- For internal use only constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures diff --git a/src/dstruct/dstruct_deque.files b/src/dstruct/dstruct_deque.files deleted file mode 100644 index 02d2b1b6a..000000000 --- a/src/dstruct/dstruct_deque.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.ocram -include "src/mem/ocram/ocram_tdp_wf.files" # True dual-port RAM - -# PoC.dstruct -vhdl PoC "src/dstruct/dstruct.pkg.vhdl" # PoC.bus package -vhdl PoC "src/dstruct/dstruct_deque.vhdl" # Top-Level diff --git a/src/dstruct/dstruct_stack.files b/src/dstruct/dstruct_stack.files deleted file mode 100644 index 44cddfcd2..000000000 --- a/src/dstruct/dstruct_stack.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.ocram -include "src/mem/ocram/ocram_sp.files" # Single-port RAM - -# PoC.dstruct -vhdl PoC "src/dstruct/dstruct.pkg.vhdl" # PoC.bus package -vhdl PoC "src/dstruct/dstruct_stack.vhdl" # Top-Level diff --git a/src/fifo/fifo.pro b/src/fifo/fifo.pro index 1deb6ae6f..1b1922a67 100644 --- a/src/fifo/fifo.pro +++ b/src/fifo/fifo.pro @@ -1,12 +1,29 @@ # ============================================================================= -# Authors: -# Adrian Weiland +# Authors: Adrian Weiland +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= analyze fifo.pkg.vhdl analyze fifo_shift.vhdl analyze fifo_stage.vhdl analyze fifo_ic_got.vhdl +analyze fifo_ic_assembly.vhdl analyze fifo_cc_got.vhdl analyze fifo_cc_got_tempgot.vhdl analyze fifo_cc_got_tempput.vhdl diff --git a/src/fifo/fifo_cc_got.files b/src/fifo/fifo_cc_got.files deleted file mode 100644 index d4265df4a..000000000 --- a/src/fifo/fifo_cc_got.files +++ /dev/null @@ -1,17 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -include "src/arith/arith_carrychain_inc.files" # Carry-chain abstraction - -# PoC.mem.orcram -include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM - -# PoC.fifo -vhdl PoC "src/fifo/fifo_cc_got.vhdl" # Top-Level diff --git a/src/fifo/fifo_cc_got_tempgot.files b/src/fifo/fifo_cc_got_tempgot.files deleted file mode 100644 index ff084374a..000000000 --- a/src/fifo/fifo_cc_got_tempgot.files +++ /dev/null @@ -1,17 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -include "src/arith/arith_carrychain_inc.files" # Carry-chain abstraction - -# PoC.mem.orcram -include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM - -# PoC.fifo -vhdl PoC "src/fifo/fifo_cc_got_tempgot.vhdl" # Top-Level diff --git a/src/fifo/fifo_cc_got_tempput.files b/src/fifo/fifo_cc_got_tempput.files deleted file mode 100644 index b4c67d060..000000000 --- a/src/fifo/fifo_cc_got_tempput.files +++ /dev/null @@ -1,17 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -include "src/arith/arith_carrychain_inc.files" # Carry-chain abstraction - -# PoC.mem.orcram -include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM - -# PoC.fifo -vhdl PoC "src/fifo/fifo_cc_got_tempput.vhdl" # Top-Level diff --git a/src/fifo/fifo_ic_assembly.files b/src/fifo/fifo_ic_assembly.files deleted file mode 100644 index 76b420aea..000000000 --- a/src/fifo/fifo_ic_assembly.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.orcram -include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM - -# PoC.fifo -vhdl PoC "src/fifo/fifo_ic_assembly.vhdl" # Top-Level diff --git a/src/fifo/fifo_ic_got.files b/src/fifo/fifo_ic_got.files deleted file mode 100644 index fedefc4df..000000000 --- a/src/fifo/fifo_ic_got.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.orcram -include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM - -# PoC.fifo -vhdl PoC "src/fifo/fifo_ic_got.vhdl" # Top-Level diff --git a/src/fifo/fifo_ic_got.vhdl b/src/fifo/fifo_ic_got.vhdl index e594c9af5..c96efee27 100644 --- a/src/fifo/fifo_ic_got.vhdl +++ b/src/fifo/fifo_ic_got.vhdl @@ -5,6 +5,7 @@ -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel +-- Stefan Unrein -- -- Entity: FIFO, independent clocks (ic), first-word-fall-through mode -- @@ -49,6 +50,7 @@ -- -- License: -- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- @@ -109,20 +111,19 @@ architecture rtl of fifo_ic_got is constant AN : positive := A_BITS + 1; -- Registers, clk_wr domain - signal IP1 : std_logic_vector(AN-1 downto 0); -- IP + 1 - signal IP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Write Pointer IP - signal IPz : std_logic_vector(AN-1 downto 0) := (others => '0'); -- IP delayed by one clock - signal OPs : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Sync stage: OP0 -> OPc - signal OPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of OP - signal Ful : std_logic := '0'; -- RAM full + signal IP1 : std_logic_vector(AN-1 downto 0); -- IP + 1 + signal IP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Write Pointer IP + signal IP0_d : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Write Pointer IP delayed + signal OPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of OP + signal Ful : std_logic := '0'; -- RAM full -- Registers, clk_rd domain - signal OP1 : std_logic_vector(AN-1 downto 0); -- OP + 1 - signal OP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Read Pointer OP - signal IPs : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Sync stage: IPz -> IPc - signal IPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of IP - signal Avl : std_logic := '0'; -- RAM Data available - signal Vld : std_logic := '0'; -- Output Valid + signal OP1 : std_logic_vector(AN-1 downto 0); -- OP + 1 + signal OP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Read Pointer OP + signal OP0_d : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Read Pointer OP delayed + signal IPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of IP + signal Avl : std_logic := '0'; -- RAM Data available + signal Vld : std_logic := '0'; -- Output Valid -- Memory Connectivity signal wa : unsigned(A_BITS-1 downto 0); @@ -162,14 +163,8 @@ begin if rising_edge(clk_wr) then if rst_wr = '1' then IP0 <= (others => '0'); - IPz <= (others => '0'); - OPs <= (others => '0'); - OPc <= (others => '0'); Ful <= '0'; else - IPz <= IP0; - OPs <= OP0; - OPc <= OPs; if puti = '1' then IP0 <= IP1; if IP1(A_BITS-1 downto 0) = OPc(A_BITS-1 downto 0) then @@ -194,6 +189,21 @@ begin di <= din; wa <= unsigned(IP0(A_BITS-1 downto 0)); + -- write pointer needs to be delayed by one CC to asure that data + -- is fully stored before giving it free to the other side. + -- Problem when clk_rd > 2* clk_wr + IP0_d <= IP0 when rising_edge(clk_wr); + Read_pointer_sync : entity work.sync_Bits + generic map( + BITS => AN, + REGISTER_OUTPUT => false + ) + port map( + Clock => clk_rd, + Input => IP0_d, + Output => IPc + ); + ----------------------------------------------------------------------------- -- Read clock domain ----------------------------------------------------------------------------- @@ -218,13 +228,9 @@ begin if rising_edge(clk_rd) then if rst_rd = '1' then OP0 <= (others => '0'); - IPs <= (others => '0'); - IPc <= (others => '0'); Avl <= '0'; Vld <= '0'; else - IPs <= IPz; - IPc <= IPs; if geti = '1' then OP0 <= OP1; if OP1(A_BITS-1 downto 0) = IPc(A_BITS-1 downto 0) then @@ -251,6 +257,21 @@ begin geti <= (not Vld or goti) and Avl; ra <= unsigned(OP0(A_BITS-1 downto 0)); + -- read pointer needs to be delayed by one CC to asure that data + -- is read out before giving it free to the other side + -- Problem when clk_wr > 2* clk_rd + OP0_d <= OP0 when rising_edge(clk_rd); + Write_pointer_sync : entity work.sync_Bits + generic map( + BITS => AN, + REGISTER_OUTPUT => false + ) + port map( + Clock => clk_wr, + Input => OP0_d, + Output => OPc + ); + ----------------------------------------------------------------------------- -- Add register to data output -- @@ -314,7 +335,7 @@ begin -- Memory Instantiation ----------------------------------------------------------------------------- gLarge: if not DATA_REG generate - ram: entity work.ocram_sdp + ram : entity work.ocram_sdp generic map ( A_BITS => A_BITS, D_BITS => D_BITS diff --git a/src/fifo/fifo_shift.vhdl b/src/fifo/fifo_shift.vhdl index 24aa7ae7f..216234763 100644 --- a/src/fifo/fifo_shift.vhdl +++ b/src/fifo/fifo_shift.vhdl @@ -3,6 +3,7 @@ -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser +-- Stefan Unrein -- -- Entity: FIFO, common clock, pipelined interface -- @@ -18,7 +19,8 @@ -- -- License: -- ============================================================================= --- Copyright 2007-2014 Technische Universitaet Dresden - Germany, +-- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +42,7 @@ use IEEE.numeric_std.all; use work.utils.all; + entity fifo_shift is generic ( D_BITS : positive; -- Data Width @@ -47,13 +50,15 @@ entity fifo_shift is ); port ( -- Global Control - clk : in std_logic; - rst : in std_logic; + clk : in std_logic; + rst : in std_logic; + fill : out std_logic_vector(log2ceilnz(MIN_DEPTH) downto 0); -- Fill'left = Empty, Fill'left = no vld + -- If vld='1' then fill(fill'left -1 downto 0) +1 is the number of Words saved -- Writing Interface - put : in std_logic; -- Write Request - din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data - ful : out std_logic; -- Capacity Exhausted + put : in std_logic; -- Write Request + din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data + ful : out std_logic; -- Capacity Exhausted -- Reading Interface got : in std_logic; -- Read Done Strobe @@ -63,34 +68,40 @@ entity fifo_shift is end entity fifo_shift; architecture rtl of fifo_shift is + constant A_BITS : positive := log2ceilnz(MIN_DEPTH); + constant DEPTH : positive := 2**A_BITS; -- Data Register type tData is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0); - signal Dat : tData(0 to MIN_DEPTH-1); - signal Ptr : unsigned(log2ceilnz(MIN_DEPTH) downto 0); + signal Dat : tData(0 to DEPTH-1); + signal Ptr : unsigned(A_BITS downto 0) := (others => '1'); + + signal ful_i : std_logic; + signal vld_i : std_logic; begin -- Data anf Pointer Registers process(clk) begin - if clk'event and clk = '1' then - if put = '1' then - Dat <= din & Dat(0 to MIN_DEPTH-2); + if rising_edge(clk) then + if (put and not ful_i) = '1' then + Dat <= din & Dat(0 to DEPTH-2); end if; end if; end process; + process(clk) begin - if clk'event and clk = '1' then + if rising_edge(clk) then if rst = '1' then - Ptr <= (others => '0'); + Ptr <= (others => '1'); else - if put /= got then - if put = '1' then - Ptr <= Ptr - 1; - else + if (put and not ful_i) /= (got and vld_i) then + if (put and not ful_i) = '1' then Ptr <= Ptr + 1; + else + Ptr <= Ptr - 1; end if; end if; end if; @@ -98,8 +109,11 @@ begin end process; -- Outputs - dout <= Dat(to_integer(not Ptr(Ptr'left-1 downto 0))); - vld <= Ptr(Ptr'left); - ful <= '1' when ((not Ptr(Ptr'left-1 downto 0)) and to_unsigned(MIN_DEPTH-1, Ptr'length-1)) = MIN_DEPTH-1 else '0'; + dout <= Dat(to_integer(Ptr(Ptr'left-1 downto 0))); + vld_i <= not Ptr(Ptr'left); + ful_i <= vld_i when (Ptr(Ptr'left-1 downto 0) and to_unsigned(DEPTH-1, Ptr'length-1)) = DEPTH-1 else '0'; + vld <= vld_i; + ful <= ful_i; + fill <= std_logic_vector(Ptr); end rtl; diff --git a/src/fifo/fifo_stage.files b/src/fifo/fifo_stage.files deleted file mode 100644 index 6e5bf7bbc..000000000 --- a/src/fifo/fifo_stage.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.fifo -vhdl PoC "src/fifo/fifo_stage.vhdl" # Top-Level diff --git a/src/io/ddrio/ddrio_in.files b/src/io/ddrio/ddrio_in.files deleted file mode 100644 index 01348c4b9..000000000 --- a/src/io/ddrio/ddrio_in.files +++ /dev/null @@ -1,25 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io.ddrio -vhdl poc "src/io/ddrio/ddrio.pkg.vhdl" # -if (DeviceVendor = "Altera") then - # Load external vendor libraries - include "lib/Altera.files" # Altera primitives - vhdl poc "src/io/ddrio/ddrio_in_altera.vhdl" # -elseif (DeviceVendor = "Xilinx") then - # Load external vendor libraries - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/io/ddrio/ddrio_in_xilinx.vhdl" # -elseif ((Environment = "Simulation") and (DeviceVendor = "Generic")) then - # use a simple implementation to testing -else - report "Only Altera and Xilinx are supported yet." -end if -vhdl poc "src/io/ddrio/ddrio_in.vhdl" # diff --git a/src/io/ddrio/ddrio_inout.files b/src/io/ddrio/ddrio_inout.files deleted file mode 100644 index ac04ba643..000000000 --- a/src/io/ddrio/ddrio_inout.files +++ /dev/null @@ -1,25 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io.ddrio -vhdl poc "src/io/ddrio/ddrio.pkg.vhdl" # -if (DeviceVendor = "Altera") then - # Load external vendor libraries - include "lib/Altera.files" # Altera primitives - vhdl poc "src/io/ddrio/ddrio_inout_altera.vhdl" # -elseif (DeviceVendor = "Xilinx") then - # Load external vendor libraries - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/io/ddrio/ddrio_inout_xilinx.vhdl" # -elseif ((Environment = "Simulation") and (DeviceVendor = "Generic")) then - # use a simple implementation to testing -else - report "Only Altera and Xilinx are supported yet." -end if -vhdl poc "src/io/ddrio/ddrio_inout.vhdl" # diff --git a/src/io/ddrio/ddrio_out.files b/src/io/ddrio/ddrio_out.files deleted file mode 100644 index dee53e264..000000000 --- a/src/io/ddrio/ddrio_out.files +++ /dev/null @@ -1,25 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io.ddrio -vhdl poc "src/io/ddrio/ddrio.pkg.vhdl" # -if (DeviceVendor = "Altera") then - # Load external vendor libraries - include "lib/Altera.files" # Altera primitives - vhdl poc "src/io/ddrio/ddrio_out_altera.vhdl" # -elseif (DeviceVendor = "Xilinx") then - # Load external vendor libraries - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/io/ddrio/ddrio_out_xilinx.vhdl" # -elseif ((Environment = "Simulation") and (DeviceVendor = "Generic")) then - # use a simple implementation to testing -else - report "Only Altera and Xilinx are supported yet." -end if -vhdl poc "src/io/ddrio/ddrio_out.vhdl" # diff --git a/src/io/iic/iic.pro b/src/io/iic/iic.pro new file mode 100644 index 000000000..4368215ff --- /dev/null +++ b/src/io/iic/iic.pro @@ -0,0 +1,21 @@ +# ============================================================================= +# Authors: Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./iic.pkg.vhdl diff --git a/src/io/io.pro b/src/io/io.pro index 1ac0eb759..ddafc1822 100644 --- a/src/io/io.pro +++ b/src/io/io.pro @@ -1,13 +1,60 @@ # ============================================================================= -# Authors: -# Adrian Weiland +# Authors: Adrian Weiland +# Stefan Unrein +# +# License: # ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./io.pkg.vhdl +analyze ./io_Debounce.vhdl +analyze ./io_FrequencyCounter.vhdl +analyze ./io_TimingCounter.vhdl +analyze ./io_GlitchFilter.vhdl +analyze ./io_PulseWidthModulation.vhdl +analyze ./io_KeyPadScanner.vhdl +analyze ./io_7SegmentMux_BCD.vhdl +analyze ./io_7SegmentMux_HEX.vhdl +analyze ./io_FanControl.vhdl + +analyze ./ddrio/ddrio.pkg.vhdl +analyze ./ddrio/ddrio_in.vhdl +analyze ./ddrio/ddrio_inout.vhdl +analyze ./ddrio/ddrio_out.vhdl + +if { $::poc::vendor eq "Xilinx" } { + analyze ./ddrio/ddrio_in_xilinx.vhdl + analyze ./ddrio/ddrio_inout_xilinx.vhdl + analyze ./ddrio/ddrio_out_xilinx.vhdl -analyze io.pkg.vhdl -analyze io_Debounce.vhdl -analyze io_FrequencyCounter.vhdl -# analyze io_TimingCounter.vhdl -analyze io_GlitchFilter.vhdl -analyze io_PulseWidthModulation.vhdl +} elseif { $::poc::vendor eq "Altera" } { + analyze ./ddrio/ddrio_in_altera.vhdl + analyze ./ddrio/ddrio_inout_altera.vhdl + analyze ./ddrio/ddrio_out_altera.vhdl + +} elseif { $::poc::vendor ne "GENERIC" } { + puts "Unknow vendor '$::poc::vendor' in arith!" + exit 1 +} include ./uart/uart.pro +include ./iic/iic.pro + +analyze ./pmod/pmod.pkg.vhdl +analyze ./pmod/pmod_KYPD.vhdl +analyze ./pmod/pmod_SSD.vhdl +analyze ./pmod/pmod_USBUART.vhdl + diff --git a/src/io/io_7SegmentMux_BCD.files b/src/io/io_7SegmentMux_BCD.files deleted file mode 100644 index 9d2918c85..000000000 --- a/src/io/io_7SegmentMux_BCD.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_7SegmentMux_BCD.vhdl" # Top-Level diff --git a/src/io/io_7SegmentMux_BCD.vhdl b/src/io/io_7SegmentMux_BCD.vhdl index 227f62ba9..1f864d78e 100644 --- a/src/io/io_7SegmentMux_BCD.vhdl +++ b/src/io/io_7SegmentMux_BCD.vhdl @@ -2,9 +2,10 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann +-- Stefan Unrein -- --- Entity: time multiplexed 7 Segment Display Controller for BCD chars +-- Entity: time multiplexed 7 Segment Display Controller for BCD chars -- -- Description: -- ------------------------------------- @@ -15,14 +16,15 @@ -- -- License: -- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, @@ -31,68 +33,74 @@ -- limitations under the License. -- ============================================================================= -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; -use work.utils.all; -use work.physical.all; -use work.components.all; -use work.io.all; +use work.utils.all; +use work.physical.all; +use work.components.all; +use work.io.all; entity io_7SegmentMux_BCD is generic ( - CLOCK_FREQ : FREQ := 100 MHz; - REFRESH_RATE : FREQ := 1 kHz; - DIGITS : positive := 4 + CLOCK_FREQ : FREQ := 100 MHz; + REFRESH_RATE : FREQ := 1 kHz; + DIGITS : positive := 4 ); - port ( - Clock : in std_logic; + port ( + Clock : in std_logic; - BCDDigits : in T_BCD_VECTOR(DIGITS - 1 downto 0); - BCDDots : in std_logic_vector(DIGITS - 1 downto 0); + BCDDigits : in T_BCD_VECTOR(DIGITS - 1 downto 0); + BCDDots : in std_logic_vector(DIGITS - 1 downto 0); - SegmentControl : out std_logic_vector(7 downto 0); - DigitControl : out std_logic_vector(DIGITS - 1 downto 0) + SegmentControl : out std_logic_vector(7 downto 0); + DigitControl : out std_logic_vector(DIGITS - 1 downto 0) ); end entity; architecture rtl of io_7SegmentMux_BCD is - signal DigitCounter_rst : std_logic; - signal DigitCounter_en : std_logic; - signal DigitCounter_us : unsigned(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); + constant Strobe_Cycles : positive := TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ); + constant Strobe_Cycle_Bits : positive := log2ceilnz(Strobe_Cycles + 1); + + signal DigitCounter_rst : std_logic; + signal DigitCounter_en : std_logic; + signal DigitCounter_us : unsigned(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); begin Strobe: entity work.misc_StrobeGenerator - generic map ( - STROBE_PERIOD_CYCLES => TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ), - INITIAL_STROBE => FALSE - ) - port map ( - Clock => Clock, - O => DigitCounter_en - ); + generic map ( + COUNTER_BITS => Strobe_Cycle_Bits, + INITIAL_STROBE => FALSE + ) + port map ( + Clock => Clock, + Reset => '0', + Enable => '1', + Strobe_Period_Cylces => to_unsigned(Strobe_Cycles, Strobe_Cycle_Bits), + Out_Strobe => DigitCounter_en + ); -- - DigitCounter_rst <= upcounter_equal(DigitCounter_us, DIGITS - 1) and DigitCounter_en; - DigitCounter_us <= upcounter_next(DigitCounter_us, DigitCounter_rst, DigitCounter_en) when rising_edge(Clock); - DigitControl <= resize(bin2onehot(std_logic_vector(DigitCounter_us)), DigitControl'length); + DigitCounter_rst <= upcounter_equal(DigitCounter_us, DIGITS - 1) and DigitCounter_en; + DigitCounter_us <= upcounter_next(DigitCounter_us, DigitCounter_rst, DigitCounter_en) when rising_edge(Clock); + DigitControl <= resize(bin2onehot(std_logic_vector(DigitCounter_us)), DigitControl'length); process(BCDDigits, BCDDots, DigitCounter_us) variable BCDDigit : T_BCD; - variable BCDDot : std_logic; + variable BCDDot : std_logic; begin - BCDDigit := BCDDigits(to_index(DigitCounter_us, BCDDigits'length)); - BCDDot := BCDDots(to_index(DigitCounter_us, BCDDigits'length)); + BCDDigit := BCDDigits(to_index(DigitCounter_us, BCDDigits'length)); + BCDDot := BCDDots(to_index(DigitCounter_us, BCDDigits'length)); if BCDDigit < C_BCD_MINUS then - SegmentControl <= io_7SegmentDisplayEncoding(BCDDigit, BCDDot, WITH_DOT => TRUE); + SegmentControl <= io_7SegmentDisplayEncoding(BCDDigit, BCDDot, WITH_DOT => TRUE); elsif BCDDigit = C_BCD_MINUS then - SegmentControl <= BCDDot & "1000000"; + SegmentControl <= BCDDot & "1000000"; else - SegmentControl <= "00000000"; + SegmentControl <= "00000000"; end if; end process; -end; +end architecture; diff --git a/src/io/io_7SegmentMux_HEX.files b/src/io/io_7SegmentMux_HEX.files deleted file mode 100644 index 5b328d157..000000000 --- a/src/io/io_7SegmentMux_HEX.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_7SegmentMux_HEX.vhdl" # Top-Level diff --git a/src/io/io_7SegmentMux_HEX.vhdl b/src/io/io_7SegmentMux_HEX.vhdl index 0b7f826f0..2e92dc3fa 100644 --- a/src/io/io_7SegmentMux_HEX.vhdl +++ b/src/io/io_7SegmentMux_HEX.vhdl @@ -2,9 +2,9 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann -- --- Entity: time multiplexed 7 Segment Display Controller for HEX chars +-- Entity: time multiplexed 7 Segment Display Controller for HEX chars -- -- Description: -- ------------------------------------- @@ -14,14 +14,15 @@ -- -- License: -- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, @@ -30,7 +31,7 @@ -- limitations under the License. -- ============================================================================= -library IEEE; +library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; @@ -43,50 +44,56 @@ use work.io.all; entity io_7SegmentMux_HEX is generic ( - CLOCK_FREQ : FREQ := 100 MHz; - REFRESH_RATE : FREQ := 1 kHz; - DIGITS : positive := 4 + CLOCK_FREQ : FREQ := 100 MHz; + REFRESH_RATE : FREQ := 1 kHz; + DIGITS : positive := 4 ); - port ( - Clock : in std_logic; + port ( + Clock : in std_logic; - HexDigits : in T_SLVV_4(DIGITS - 1 downto 0); - HexDots : in std_logic_vector(DIGITS - 1 downto 0); + HexDigits : in T_SLVV_4(DIGITS - 1 downto 0); + HexDots : in std_logic_vector(DIGITS - 1 downto 0); - SegmentControl : out std_logic_vector(7 downto 0); - DigitControl : out std_logic_vector(DIGITS - 1 downto 0) + SegmentControl : out std_logic_vector(7 downto 0); + DigitControl : out std_logic_vector(DIGITS - 1 downto 0) ); end entity; architecture rtl of io_7SegmentMux_HEX is - signal DigitCounter_rst : std_logic; - signal DigitCounter_en : std_logic; - signal DigitCounter_us : unsigned(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); + constant Strobe_Cycles : positive := TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ); + constant Strobe_Cycle_Bits : positive := log2ceilnz(Strobe_Cycles + 1); + + signal DigitCounter_rst : std_logic; + signal DigitCounter_en : std_logic; + signal DigitCounter_us : unsigned(log2ceilnz(DIGITS) - 1 downto 0) := (others => '0'); begin Strobe: entity work.misc_StrobeGenerator - generic map ( - STROBE_PERIOD_CYCLES => TimingToCycles(to_time(REFRESH_RATE), CLOCK_FREQ), - INITIAL_STROBE => FALSE - ) - port map ( - Clock => Clock, - O => DigitCounter_en - ); + generic map ( + COUNTER_BITS => Strobe_Cycle_Bits, + INITIAL_STROBE => FALSE + ) + port map ( + Clock => Clock, + Reset => '0', + Enable => '1', + Strobe_Period_Cylces => to_unsigned(Strobe_Cycles, Strobe_Cycle_Bits), + Out_Strobe => DigitCounter_en + ); -- - DigitCounter_rst <= upcounter_equal(DigitCounter_us, DIGITS - 1) and DigitCounter_en; - DigitCounter_us <= upcounter_next(DigitCounter_us, DigitCounter_rst, DigitCounter_en) when rising_edge(Clock); - DigitControl <= resize(bin2onehot(std_logic_vector(DigitCounter_us)), DigitControl'length); + DigitCounter_rst <= upcounter_equal(DigitCounter_us, DIGITS - 1) and DigitCounter_en; + DigitCounter_us <= upcounter_next(DigitCounter_us, DigitCounter_rst, DigitCounter_en) when rising_edge(Clock); + DigitControl <= resize(bin2onehot(std_logic_vector(DigitCounter_us)), DigitControl'length); process(HexDigits, HexDots, DigitCounter_us) variable HexDigit : T_SLV_4; - variable HexDot : std_logic; + variable HexDot : std_logic; begin - HexDigit := HexDigits(to_index(DigitCounter_us, HexDigits'length)); - HexDot := HexDots(to_index(DigitCounter_us, HexDigits'length)); + HexDigit := HexDigits(to_index(DigitCounter_us, HexDigits'length)); + HexDot := HexDots(to_index(DigitCounter_us, HexDigits'length)); - SegmentControl <= io_7SegmentDisplayEncoding(HexDigit, HexDot, WITH_DOT => TRUE); + SegmentControl <= io_7SegmentDisplayEncoding(HexDigit, HexDot, WITH_DOT => TRUE); end process; -end; +end architecture; diff --git a/src/io/io_Debounce.files b/src/io/io_Debounce.files deleted file mode 100644 index e075336e0..000000000 --- a/src/io/io_Debounce.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_Debounce.vhdl" # Top-Level diff --git a/src/io/io_FanControl.files b/src/io/io_FanControl.files deleted file mode 100644 index c0220d3b2..000000000 --- a/src/io/io_FanControl.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_FanControl.vhdl" # Top-Level diff --git a/src/io/io_FanControl.vhdl b/src/io/io_FanControl.vhdl index f23e6f0d6..bf1050948 100644 --- a/src/io/io_FanControl.vhdl +++ b/src/io/io_FanControl.vhdl @@ -2,43 +2,43 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann -- --- Entity: Generic Fan Controller +-- Entity: Generic Fan Controller -- -- Description: -- ------------------------------------- -- .. code-block:: none -- --- This module generates a PWM signal for a 3-pin (transistor controlled) or --- 4-pin fan header. The FPGAs temperature is read from device specific system --- monitors (normal, user temperature, over temperature). +-- This module generates a PWM signal for a 3-pin (transistor controlled) or +-- 4-pin fan header. The FPGAs temperature is read from device specific system +-- monitors (normal, user temperature, over temperature). -- --- For example the Xilinx System Monitors are configured as follows: +-- For example the Xilinx System Monitors are configured as follows: -- --- | /-----\ --- Temp_ov on=80 | - - - - - - /-------/ \ --- | / | \ --- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ --- | / | \ --- | / | | \ --- Temp_us on=35 | - /---/ | | \ --- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ --- | / | | | \ --- ----------------|--------|------------|--------------|----------|--------- --- pwm = | min | medium | max | medium | min +-- | /-----\ +-- Temp_ov on=80 | - - - - - - /-------/ \ +-- | / | \ +-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ +-- | / | \ +-- | / | | \ +-- Temp_us on=35 | - /---/ | | \ +-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ +-- | / | | | \ +-- ----------------|--------|------------|--------------|----------|--------- +-- pwm = | min | medium | max | medium | min -- -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, @@ -61,137 +61,137 @@ use work.xil.all; entity io_FanControl is generic ( - CLOCK_FREQ : FREQ; - ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; - ENABLE_TACHO : boolean := FALSE + CLOCK_FREQ : FREQ; + ADD_INPUT_SYNCHRONIZERS : boolean := TRUE; + ENABLE_TACHO : boolean := FALSE ); port ( -- Global Control - Clock : in std_logic; - Reset : in std_logic; + Clock : in std_logic; + Reset : in std_logic; -- Fan Control derived from internal System Health Monitor - Fan_PWM : out std_logic; + Fan_PWM : out std_logic; - -- Decoding of Speed Sensor (Requires ENABLE_TACHO) - Fan_Tacho : in std_logic := 'X'; - TachoFrequency : out std_logic_vector(15 downto 0) - ); + -- Decoding of Speed Sensor (Requires ENABLE_TACHO) + Fan_Tacho : in std_logic := 'X'; + TachoFrequency : out std_logic_vector(15 downto 0) + ); end entity; architecture rtl of io_FanControl is - constant TIME_STARTUP : T_TIME := 500.0e-3; -- StartUp time - constant PWM_RESOLUTION : positive := 4; -- 4 Bit resolution => 0 to 15 steps - constant PWM_FREQ : FREQ := 10 Hz; -- + constant TIME_STARTUP : T_TIME := 500.0e-3; -- StartUp time + constant PWM_RESOLUTION : positive := 4; -- 4 Bit resolution => 0 to 15 steps + constant PWM_FREQ : FREQ := 10 Hz; -- - constant TACHO_RESOLUTION : positive := 8; + constant TACHO_RESOLUTION : positive := 8; - signal PWM_PWMIn : std_logic_vector(PWM_RESOLUTION - 1 downto 0); - signal PWM_PWMOut : std_logic := '0'; + signal PWM_PWMIn : std_logic_vector(PWM_RESOLUTION - 1 downto 0); + signal PWM_PWMOut : std_logic := '0'; begin -- System Monitor and temperature to PWM ratio calculation for Virtex6 -- ========================================================================================================================================================== genXilinx : if VENDOR = VENDOR_XILINX generate - signal OverTemperature_async : std_logic; - signal OverTemperature_sync : std_logic; + signal OverTemperature_async : std_logic; + signal OverTemperature_sync : std_logic; - signal UserTemperature_async : std_logic; - signal UserTemperature_sync : std_logic; + signal UserTemperature_async : std_logic; + signal UserTemperature_sync : std_logic; - signal TC_Timeout : std_logic; - signal StartUp : std_logic; + signal TC_Timeout : std_logic; + signal StartUp : std_logic; begin genXilinxBoard : if str_imatch(BOARD_NAME, "ML605") or str_imatch(BOARD_NAME, "KC705") or - str_imatch(BOARD_NAME, "VC707") or str_imatch(BOARD_NAME, "KCU105") generate + str_imatch(BOARD_NAME, "VC707") or str_imatch(BOARD_NAME, "KCU105") generate SystemMonitor : xil_SystemMonitor - port map ( - Reset => Reset, -- Reset signal for the System Monitor control logic + port map ( + Reset => Reset, -- Reset signal for the System Monitor control logic - Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output - Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output - Alarm => open, -- OR'ed output of all the Alarms - VP => '0', -- Dedicated Analog Input Pair - VN => '0' - ); + Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output + Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output + Alarm => open, -- OR'ed output of all the Alarms + VP => '0', -- Dedicated Analog Input Pair + VN => '0' + ); end generate; - sync: entity work.sync_Bits_Xilinx - generic map ( - BITS => 2 - ) - port map ( - Clock => Clock, - Input(0) => OverTemperature_async, - Input(1) => UserTemperature_async, - Output(0) => OverTemperature_sync, - Output(1) => UserTemperature_sync - ); + sync: entity work.sync_Bits + generic map ( + BITS => 2 + ) + port map ( + Clock => Clock, + Input(0) => OverTemperature_async, + Input(1) => UserTemperature_async, + Output(0) => OverTemperature_sync, + Output(1) => UserTemperature_sync + ); -- timer for warm-up control -- ========================================================================================================================================================== TC: entity work.io_TimingCounter - generic map ( - TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table - ) - port map ( - Clock => Clock, -- clock - Enable => StartUp, -- enable counter - Load => '0', -- load Timing Value from TIMING_TABLE selected by slot - Slot => 0, -- - Timeout => TC_Timeout -- timing reached - ); + generic map ( + TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table + ) + port map ( + Clock => Clock, -- clock + Enable => StartUp, -- enable counter + Load => '0', -- load Timing Value from TIMING_TABLE selected by slot + Slot => 0, -- + Timeout => TC_Timeout -- timing reached + ); - StartUp <= not TC_Timeout; + StartUp <= not TC_Timeout; process(StartUp, UserTemperature_sync, OverTemperature_sync) begin - if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up - elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% - elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% - else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% + if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up + elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% + elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% + else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; genAltera : if VENDOR = VENDOR_ALTERA generate --- signal OverTemperature_async : STD_LOGIC; - signal OverTemperature_sync : std_logic; +-- signal OverTemperature_async : STD_LOGIC; + signal OverTemperature_sync : std_logic; --- signal UserTemperature_async : STD_LOGIC; - signal UserTemperature_sync : std_logic; +-- signal UserTemperature_async : STD_LOGIC; + signal UserTemperature_sync : std_logic; - signal TC_Timeout : std_logic; - signal StartUp : std_logic; + signal TC_Timeout : std_logic; + signal StartUp : std_logic; begin genDE4 : if str_imatch(BOARD_NAME, "DE4") generate - OverTemperature_sync <= '0'; - UserTemperature_sync <= '1'; + OverTemperature_sync <= '0'; + UserTemperature_sync <= '1'; end generate; -- timer for warm-up control -- ========================================================================================================================================================== TC: entity work.io_TimingCounter - generic map ( - TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table - ) - port map ( - Clock => Clock, -- clock - Enable => StartUp, -- enable counter - Load => '0', -- load Timing Value from TIMING_TABLE selected by slot - Slot => 0, -- - Timeout => TC_Timeout -- timing reached - ); + generic map ( + TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table + ) + port map ( + Clock => Clock, -- clock + Enable => StartUp, -- enable counter + Load => '0', -- load Timing Value from TIMING_TABLE selected by slot + Slot => 0, -- + Timeout => TC_Timeout -- timing reached + ); - StartUp <= not TC_Timeout; + StartUp <= not TC_Timeout; process(StartUp, UserTemperature_sync, OverTemperature_sync) begin - if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up - elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% - elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% - else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% + if (StartUp = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100%; start up + elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**PWM_RESOLUTION - 1, PWM_RESOLUTION); -- 100% + elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% + else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; @@ -199,20 +199,20 @@ begin -- PWM signal modulator -- ========================================================================================================================================================== PWM: entity work.io_PulseWidthModulation - generic map ( - CLOCK_FREQ => CLOCK_FREQ, -- - PWM_FREQ => PWM_FREQ, -- - PWM_RESOLUTION => PWM_RESOLUTION -- - ) - port map ( - Clock => Clock, - Reset => Reset, - PWMIn => PWM_PWMIn, - PWMOut => PWM_PWMOut - ); + generic map ( + CLOCK_FREQ => CLOCK_FREQ, -- + PWM_FREQ => PWM_FREQ, -- + PWM_RESOLUTION => PWM_RESOLUTION -- + ) + port map ( + Clock => Clock, + Reset => Reset, + PWMIn => PWM_PWMIn, + PWMOut => PWM_PWMOut + ); -- registered output - Fan_PWM <= PWM_PWMOut when rising_edge(Clock); + Fan_PWM <= PWM_PWMOut when rising_edge(Clock); -- tacho signal interpretation -> convert to RPM -- ========================================================================================================================================================== @@ -220,8 +220,8 @@ begin TachoFrequency <= (TachoFrequency'range => 'X'); end generate; genTacho : if ENABLE_TACHO generate - signal Tacho_sync : std_logic; - signal Tacho_Freq : std_logic_vector(TACHO_RESOLUTION - 1 downto 0); + signal Tacho_sync : std_logic; + signal Tacho_Freq : std_logic_vector(TACHO_RESOLUTION - 1 downto 0); begin -- Input Synchronization genNoSync : if not ADD_INPUT_SYNCHRONIZERS generate @@ -230,26 +230,26 @@ begin genSync : if ADD_INPUT_SYNCHRONIZERS generate sync_i: entity work.sync_Bits port map ( - Clock => Clock, -- Clock to be synchronized to - Input(0) => Fan_Tacho, -- Data to be synchronized - Output(0) => Tacho_sync -- synchronised data + Clock => Clock, -- Clock to be synchronized to + Input(0) => Fan_Tacho, -- Data to be synchronized + Output(0) => Tacho_sync -- synchronised data ); end generate; Tacho: entity work.io_FrequencyCounter - generic map ( - CLOCK_FREQ => CLOCK_FREQ, -- - TIMEBASE => (60.0 / 64.0), -- ca. 1 second - RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM - ) - port map ( - Clock => Clock, - Reset => Reset, - FreqIn => Tacho_sync, - FreqOut => Tacho_Freq - ); + generic map ( + CLOCK_FREQ => CLOCK_FREQ, -- + TIMEBASE => (60.0 / 64.0), -- ca. 1 second + RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM + ) + port map ( + Clock => Clock, + Reset => Reset, + FreqIn => Tacho_sync, + FreqOut => Tacho_Freq + ); -- multiply by 64; divide by 2 for RPMs (2 impulses per revolution) => append 5x '0' - TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit + TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit end generate; end; diff --git a/src/io/io_FrequencyCounter.files b/src/io/io_FrequencyCounter.files deleted file mode 100644 index d78b0f35a..000000000 --- a/src/io/io_FrequencyCounter.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_frequencyCounter.vhdl" # Top-Level diff --git a/src/io/io_GlitchFilter.files b/src/io/io_GlitchFilter.files deleted file mode 100644 index b98cd6243..000000000 --- a/src/io/io_GlitchFilter.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_GlitchFilter.vhdl" # Top-Level diff --git a/src/io/io_KeyPadScanner.files b/src/io/io_KeyPadScanner.files deleted file mode 100644 index 6bfbcb5d6..000000000 --- a/src/io/io_KeyPadScanner.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_KeyPadScanner.vhdl" # Top-Level diff --git a/src/io/io_PulseWidthModulation.files b/src/io/io_PulseWidthModulation.files deleted file mode 100644 index af0925e79..000000000 --- a/src/io/io_PulseWidthModulation.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_PulseWidthModulation.vhdl" # Top-Level diff --git a/src/io/io_TimingCounter.files b/src/io/io_TimingCounter.files deleted file mode 100644 index 10f4ec828..000000000 --- a/src/io/io_TimingCounter.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package -vhdl PoC "src/io/io_TimingCounter.vhdl" # Top-Level diff --git a/src/io/pmod/pmod_KYPD.files b/src/io/pmod/pmod_KYPD.files deleted file mode 100644 index 2f0666900..000000000 --- a/src/io/pmod/pmod_KYPD.files +++ /dev/null @@ -1,16 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io -include "src/io/io_Debounce.files" # -include "src/io/io_KeyPadScanner.files" # - -# PoC.io.pmod -vhdl PoC "src/io/pmod/pmod.pkg.vhdl" # PoC.arith package -vhdl PoC "src/io/pmod/pmod_KYPD.vhdl" # Top-Level diff --git a/src/io/pmod/pmod_SSD.files b/src/io/pmod/pmod_SSD.files deleted file mode 100644 index fa438148d..000000000 --- a/src/io/pmod/pmod_SSD.files +++ /dev/null @@ -1,13 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io.pmod -vhdl PoC "src/io/pmod/pmod.pkg.vhdl" # PoC.arith package -vhdl PoC "src/io/pmod/pmod_SSD.vhdl" # Top-Level - diff --git a/src/io/pmod/pmod_USBUART.files b/src/io/pmod/pmod_USBUART.files deleted file mode 100644 index eaad8804a..000000000 --- a/src/io/pmod/pmod_USBUART.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.io.uart -include "src/io/uart/uart_fifo.files" # UART with FIFO interface - -# PoC.io.pmod -vhdl PoC "src/io/pmod/pmod.pkg.vhdl" # PoC.arith package -vhdl PoC "src/io/pmod/pmod_USBUART.vhdl" # Top-Level diff --git a/src/io/uart/uart.pro b/src/io/uart/uart.pro index 2535b4abd..4e40e64e9 100644 --- a/src/io/uart/uart.pro +++ b/src/io/uart/uart.pro @@ -1,6 +1,27 @@ +# ============================================================================= +# Authors: Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= analyze uart.pkg.vhdl analyze uart_bclk.vhdl analyze uart_rx.vhdl analyze uart_tx.vhdl analyze uart_fifo.vhdl +analyze uart_ft245.vhdl +# analyze uart_axiLite.vhdl diff --git a/src/io/uart/uart_fifo.files b/src/io/uart/uart_fifo.files deleted file mode 100644 index 21d637ad0..000000000 --- a/src/io/uart/uart_fifo.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -include "src/misc/sync/sync_Bits.files" # PoC.misc.sync -include "src/fifo/fifo_cc_got.files" # PoC.fifo.cc_got - -# PoC.io.uart -vhdl poc "src/io/uart/uart.pkg.vhdl" # UART Package -vhdl poc "src/io/uart/uart_bclk.vhdl" # Bit clock generator -vhdl poc "src/io/uart/uart_rx.vhdl" # Receiver -vhdl poc "src/io/uart/uart_tx.vhdl" # Transmitter -vhdl poc "src/io/uart/uart_fifo.vhdl" # Top-Level diff --git a/src/list/list_expire.vhdl b/src/list/list_expire.vhdl new file mode 100644 index 000000000..eb44f5e28 --- /dev/null +++ b/src/list/list_expire.vhdl @@ -0,0 +1,137 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================ +-- Module: list_expire +-- +-- Authors: Patrick Lehmann +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + + +use work.utils.ALL; + +-- list_expire_fixed +-- expire = list of expireable items +-- fixed = insert_time := current_time + fixed interval + +ENTITY list_expire IS + GENERIC ( + CLOCK_CYCLE_TICKS : POSITIVE := 1024; + EXPIRATION_TIME_TICKS : NATURAL := 10; + ELEMENTS : POSITIVE := 32; + KEY_BITS : POSITIVE := 4 + ); + PORT ( + Clock : IN STD_LOGIC; + Reset : IN STD_LOGIC; + + Tick : IN STD_LOGIC; + + Insert : IN STD_LOGIC; + KeyIn : IN STD_LOGIC_VECTOR(KEY_BITS - 1 DOWNTO 0); + + Expired : OUT STD_LOGIC; + KeyOut : OUT STD_LOGIC_VECTOR(KEY_BITS - 1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE rtl OF list_expire IS + ATTRIBUTE KEEP : BOOLEAN; + + CONSTANT CLOCK_BITS : POSITIVE := log2ceilnz(CLOCK_CYCLE_TICKS); + + SIGNAL CurrentTime_us : UNSIGNED(CLOCK_BITS - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL KeyTime_us : UNSIGNED(CLOCK_BITS + KEY_BITS - 1 DOWNTO KEY_BITS); + + SIGNAL FIFO_put : STD_LOGIC; + SIGNAL FIFO_DataIn : STD_LOGIC_VECTOR(CLOCK_BITS + KEY_BITS - 1 DOWNTO 0); + SIGNAL FIFO_Full : STD_LOGIC; + SIGNAL FIFO_got : STD_LOGIC; + SIGNAL FIFO_DataOut : STD_LOGIC_VECTOR(CLOCK_BITS + KEY_BITS - 1 DOWNTO 0); + SIGNAL FIFO_Valid : STD_LOGIC; + + SIGNAL Expired_i : STD_LOGIC; + +BEGIN + + PROCESS(Clock) + BEGIN + IF rising_edge(Clock) THEN + IF (Reset = '1') THEN + CurrentTime_us <= (OTHERS => '0'); + ELSE + IF (Tick = '1') THEN + CurrentTime_us <= CurrentTime_us + 1; + END IF; + END IF; + END IF; + END PROCESS; + + KeyTime_us <= CurrentTime_us + EXPIRATION_TIME_TICKS; + + FIFO_put <= Insert; + FIFO_DataIn(KeyIn'range) <= KeyIn; + FIFO_DataIn(KeyTime_us'range) <= std_logic_vector(KeyTime_us); + + FIFO : entity work.fifo_cc_got + GENERIC MAP ( + D_BITS => CLOCK_BITS + KEY_BITS, -- Data Width + MIN_DEPTH => ELEMENTS, -- Minimum FIFO Depth + DATA_REG => TRUE, -- Store Data Content in Registers + STATE_REG => TRUE, -- Registered Full/Empty Indicators + OUTPUT_REG => FALSE, -- Registered FIFO Output + ESTATE_WR_BITS => 0, -- Empty State Bits + FSTATE_RD_BITS => 0 -- Full State Bits + ) + PORT MAP ( + -- Global Reset and Clock + clk => Clock, + rst => Reset, + + -- Writing Interface + put => FIFO_put, + din => FIFO_DataIn, + full => OPEN,--FIFO_Full, + estate_wr => OPEN, + + -- Reading Interface + got => FIFO_got, + dout => FIFO_DataOut, + valid => FIFO_Valid, + fstate_rd => OPEN + ); + + FIFO_got <= Expired_i; + + Expired_i <= to_sl(FIFO_DataOut(KeyTime_us'range) = std_logic_vector(CurrentTime_us)) AND FIFO_Valid; + + Expired <= Expired_i; + KeyOut <= FIFO_DataOut(KeyIn'range); +END ARCHITECTURE; diff --git a/src/mem/ddr2/README.md b/src/mem/ddr2/README.md deleted file mode 100644 index 53c002176..000000000 --- a/src/mem/ddr2/README.md +++ /dev/null @@ -1,8 +0,0 @@ -# Namespace `PoC.mem.ddr2` - -The namespace `PoC.mem.ddr2` is designated for own implementations of -DDR2 memory controllers as well as for adapters for vendor-specific -implementations. At the top-level, all controllers and adapters -provide the same simple memory interface to the user application. - -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ddr2/index.html). diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files deleted file mode 100644 index 2bfa30d01..000000000 --- a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files +++ /dev/null @@ -1,10 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -vhdl poc "src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl" diff --git a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl b/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl deleted file mode 100644 index 04328d972..000000000 --- a/src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl +++ /dev/null @@ -1,130 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================= --- Authors: Martin Zabel --- --- Module: Adapter for the Xilinx MIG IP core on Spartan-6 FPGAs. --- --- Description: --- ------------------------------------ --- Adapter between the :ref:`PoC.Mem ` --- interface and the User Interface of the Xilinx MIG IP core for the --- Spartan-6 FPGA Memory Controller Block (MCB). The MCB can be configured to --- have multiple ports. One instance of this adapter is required for every --- port. The control signals for one port of the MIG IP core are prefixed by --- "cX_pY", meaning port Y on controller X. --- --- Simplifies the User Interface ("user") of the Xilinx MIG IP core (UG388). --- The PoC.Mem interface provides single-cycle fully pipelined read/write access --- to the memory. All accesses are word-aligned. Always all bytes of a word are --- written to the memory. More details can be found --- :ref:`here `. --- --- Generic parameters: --- --- * D_BITS: Data bus width of the PoC.Mem and MIG / MCBinterface. Also size of --- one word in bits. --- --- * MEM_A_BITS: Address bus width of the PoC.Mem interface. --- --- * APP_A_BTIS: Address bus width of the MIG / MCB interface. --- --- Containts only combinational logic. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.utils.all; - -entity ddr2_mem2mig_adapter_Spartan6 is - - generic ( - D_BITS : positive; - MEM_A_BITS : positive; - APP_A_BITS : positive - ); - - port ( - -- PoC.Mem interface - mem_req : in std_logic; - mem_write : in std_logic; - mem_addr : in unsigned(MEM_A_BITS-1 downto 0); - mem_wdata : in std_logic_vector(D_BITS-1 downto 0); - mem_wmask : in std_logic_vector(D_BITS/8-1 downto 0) := (others => '0'); - mem_rdy : out std_logic; - mem_rstb : out std_logic; - mem_rdata : out std_logic_vector(D_BITS-1 downto 0); - - -- Xilinx MIG IP Core interface - mig_calib_done : in std_logic; - mig_cmd_full : in std_logic; - mig_wr_full : in std_logic; - mig_rd_empty : in std_logic; - mig_rd_data : in std_logic_vector((D_BITS)-1 downto 0); - mig_cmd_instr : out std_logic_vector(2 downto 0); - mig_cmd_en : out std_logic; - mig_cmd_bl : out std_logic_vector(5 downto 0); - mig_cmd_byte_addr : out std_logic_vector(APP_A_BITS-1 downto 0); - mig_wr_data : out std_logic_vector((D_BITS)-1 downto 0); - mig_wr_mask : out std_logic_vector((D_BITS)/8-1 downto 0); - mig_wr_en : out std_logic; - mig_rd_en : out std_logic - ); - -end entity ddr2_mem2mig_adapter_Spartan6; - -architecture rtl of ddr2_mem2mig_adapter_Spartan6 is - -- The number of bits addressing the byte within the MIG address. - constant BYTE_ADDR_BITS : positive := log2ceil(D_BITS/8); - - signal mem_rdy_i : std_logic; - -begin -- architecture rtl - - -- command & FIFO control - mem_rdy_i <= mig_calib_done and (not mig_cmd_full) and (not mig_wr_full); - mem_rdy <= mem_rdy_i; - - mig_cmd_en <= mem_rdy_i and mem_req; - mig_wr_en <= mem_rdy_i and mem_req and mem_write; - mig_cmd_instr <= "00" & (not mem_write); -- with-out auto precharge - mig_cmd_bl <= "000000"; -- 1 word of D_BITS - - -- address - process (mem_addr) is - begin -- process - mig_cmd_byte_addr <= (others => '0'); - mig_cmd_byte_addr(MEM_A_BITS+BYTE_ADDR_BITS-1 downto BYTE_ADDR_BITS) <= std_logic_vector(mem_addr); - end process; - - -- write data & mask - mig_wr_data <= mem_wdata; - mig_wr_mask <= mem_wmask; - - -- read reply - mig_rd_en <= not mig_rd_empty; - mem_rstb <= not mig_rd_empty; - mem_rdata <= mig_rd_data; - -end architecture rtl; diff --git a/src/mem/ddr3/README.md b/src/mem/ddr3/README.md deleted file mode 100644 index 3676a3c51..000000000 --- a/src/mem/ddr3/README.md +++ /dev/null @@ -1,8 +0,0 @@ -# Namespace `PoC.mem.ddr3` - -The namespace `PoC.mem.ddr3` is designated for own implementations of -DDR3 memory controllers as well as for adapters for vendor-specific -implementations. At the top-level, all controllers and adapters -provide the same simple memory interface to the user application. - -Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ddr3/index.html). diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files deleted file mode 100644 index 35d104f3e..000000000 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files +++ /dev/null @@ -1,10 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -vhdl poc "src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl" diff --git a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl b/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl deleted file mode 100644 index c3aeaeb22..000000000 --- a/src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl +++ /dev/null @@ -1,132 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================= --- Authors: Martin Zabel --- --- Module: Adapter for the Xilinx MIG IP core on 7-Series FPGAs. --- --- Description: --- ------------------------------------ --- Adapter between the :ref:`PoC.Mem ` interface and the --- application interface ("app") of the Xilinx MIG IP core for 7-Series FPGAs. --- --- Simplifies the application interface ("app") of the Xilinx MIG IP core. --- The PoC.Mem interface provides single-cycle fully pipelined read/write access --- to the memory. All accesses are word-aligned. Always all bytes of a word are --- written to the memory. More details can be found --- :ref:`here `. --- --- Generic parameters: --- --- * D_BITS: Data bus width of the PoC.Mem and "app" interface. Also size of one --- word in bits. --- --- * DQ_BITS: Size of data bus between memory controller and external memory --- (DIMM, SoDIMM). --- --- * MEM_A_BITS: Address bus width of the PoC.Mem interface. --- --- * APP_A_BTIS: Address bus width of the "app" interface. --- --- Containts only combinational logic. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.utils.all; - -entity ddr3_mem2mig_adapter_Series7 is - - generic ( - D_BITS : positive; - DQ_BITS : positive; - MEM_A_BITS : positive; - APP_A_BITS : positive - ); - - port ( - -- PoC.Mem interface - mem_req : in std_logic; - mem_write : in std_logic; - mem_addr : in unsigned(MEM_A_BITS-1 downto 0); - mem_wdata : in std_logic_vector(D_BITS-1 downto 0); - mem_wmask : in std_logic_vector(D_BITS/8-1 downto 0) := (others => '0'); - mem_rdy : out std_logic; - mem_rstb : out std_logic; - mem_rdata : out std_logic_vector(D_BITS-1 downto 0); - - -- Xilinx MIG IP Core interface - init_calib_complete : in std_logic; - app_rd_data : in std_logic_vector((D_BITS)-1 downto 0); - app_rd_data_end : in std_logic; - app_rd_data_valid : in std_logic; - app_rdy : in std_logic; - app_wdf_rdy : in std_logic; - app_addr : out std_logic_vector(APP_A_BITS-1 downto 0); - app_cmd : out std_logic_vector(2 downto 0); - app_en : out std_logic; - app_wdf_data : out std_logic_vector((D_BITS)-1 downto 0); - app_wdf_end : out std_logic; - app_wdf_mask : out std_logic_vector((D_BITS)/8-1 downto 0); - app_wdf_wren : out std_logic - ); - -end entity ddr3_mem2mig_adapter_Series7; - -architecture rtl of ddr3_mem2mig_adapter_Series7 is - -- The smallest addressable unit of the "app" interface has DQ_BITS bits. - -- The smallest addressable unit of the "mem" interface has D_BITS bits. - -- The burst length is then D_BITS / DQ_BITS. - constant BL : positive := D_BITS / DQ_BITS; - constant BL_BITS : natural := log2ceil(BL); - - signal mem_rdy_i : std_logic; - -begin -- architecture rtl - - -- command & FIFO control - mem_rdy_i <= init_calib_complete and app_rdy and app_wdf_rdy; - mem_rdy <= mem_rdy_i; - - app_en <= mem_rdy_i and mem_req; - app_wdf_wren <= mem_rdy_i and mem_req and mem_write; - app_wdf_end <= mem_rdy_i and mem_req and mem_write; -- 1 "mem" word / burst - app_cmd <= "00" & (not mem_write); - - -- address - process (mem_addr) is - begin -- process - app_addr <= (others => '0'); - app_addr(MEM_A_BITS+BL_BITS-1 downto BL_BITS) <= std_logic_vector(mem_addr); - end process; - - -- write data & mask - app_wdf_data <= mem_wdata; - app_wdf_mask <= mem_wmask; - - -- read reply - mem_rstb <= app_rd_data_valid; - mem_rdata <= app_rd_data; - -end architecture rtl; diff --git a/src/mem/lut/lut_Sine.files b/src/mem/lut/lut_Sine.files deleted file mode 100644 index ad245bb86..000000000 --- a/src/mem/lut/lut_Sine.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.lut -vhdl poc "src/mem/lut/lut_Sine.vhdl" # Top-Level diff --git a/src/mem/mem.pro b/src/mem/mem.pro index 5620a0268..4d373be98 100644 --- a/src/mem/mem.pro +++ b/src/mem/mem.pro @@ -1,9 +1,25 @@ # ============================================================================= -# Authors: -# Adrian Weiland +# Authors: Adrian Weiland +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= -analyze mem.pkg.vhdl +analyze ./mem.pkg.vhdl analyze ./ocram/ocram.pkg.vhdl analyze ./ocram/ocram_tdp_sim.vhdl analyze ./ocram/ocram_tdp.vhdl @@ -13,3 +29,38 @@ analyze ./ocram/ocram_sdp_optimized.vhdl analyze ./ocram/ocram_sdp_wf.vhdl analyze ./ocram/ocram_sp.vhdl analyze ./ocram/ocram_tdp_wf.vhdl + +if { $::poc::vendor eq "Xilinx" } { + puts "No files for Xilinx." + +} elseif { $::poc::vendor eq "Altera" } { + analyze ./ocram/altera/ocram_sp_altera.vhdl + analyze ./ocram/altera/ocram_tdp_altera.vhdl + +} elseif { $::poc::vendor ne "GENERIC" } { + puts "Unknow vendor '$::poc::vendor' in arith!" + exit 1 +} + +analyze ./ocrom/ocrom.pkg.vhdl +analyze ./ocrom/ocrom_dp.vhdl +analyze ./ocrom/ocrom_sp.vhdl + +analyze ./sdram/sdram_ctrl_fsm.vhdl + +if { $::poc::vendor eq "Xilinx" } { + analyze ./sdram/sdram_ctrl_phy_s3esk.vhdl + analyze ./sdram/sdram_ctrl_s3esk.vhdl + +} elseif { $::poc::vendor eq "Altera" } { + analyze ./sdram/sdram_ctrl_phy_de0.vhdl + analyze ./sdram/sdram_ctrl_de0.vhdl + +} elseif { $::poc::vendor ne "GENERIC" } { + puts "Unknow vendor '$::poc::vendor' in arith!" + exit 1 +} + +analyze ./mem_GitVersionRegister.pkg.vhdl + +analyze ./lut/lut_Sine.vhdl diff --git a/src/mem/mem_GitVersionRegister.pkg.vhdl b/src/mem/mem_GitVersionRegister.pkg.vhdl new file mode 100644 index 000000000..046856354 --- /dev/null +++ b/src/mem/mem_GitVersionRegister.pkg.vhdl @@ -0,0 +1,411 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Stefan Unrein +-- Max Kraft-Kugler +-- Patrick Lehmann +-- Iqbal Asif +-- +-- Package: mem_GitVersionRegister +-- +-- Description: +-- ------------------------------------- +-- This package defines the Functions, Strings and Records necessary for +-- the AXI4Lite_GitVersionRegister module. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use STD.TextIO.all; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.utils.all; +use work.config.all; +use work.vectors.all; +use work.strings.all; +use work.axi4lite.all; + + +package mem_GitVersionRegister is + -------Define AXI Register structure------------- + constant Version_of_VersionReg : std_logic_vector(7 downto 0) := x"02"; + + constant Address_Width : natural := 32; + constant Data_Width : natural := 32; + + type T_Version_Register_Common is record + BuildDate_Day : std_logic_vector(7 downto 0); + BuildDate_Month : std_logic_vector(7 downto 0); + BuildDate_Year : std_logic_vector(15 downto 0); + + NumberModule : std_logic_vector(23 downto 0); + VersionOfVersionReg : std_logic_vector(7 downto 0); + + VivadoVersion_Year : std_logic_vector(15 downto 0); + VivadoVersion_Release : std_logic_vector(7 downto 0); + VivadoVersion_SubRelease : std_logic_vector(7 downto 0); + + ProjektName : std_logic_vector(159 downto 0); + end record; + + type T_Version_Register_Top is record + Version_Major : std_logic_vector(7 downto 0); + Version_Minor : std_logic_vector(7 downto 0); + Version_Release : std_logic_vector(7 downto 0); + Version_Flags : std_logic_vector(7 downto 0); + + GitHash : std_logic_vector(159 downto 0); + + GitDate_Day : std_logic_vector(7 downto 0); + GitDate_Month : std_logic_vector(7 downto 0); + GitDate_Year : std_logic_vector(15 downto 0); + + GitTime_Hour : std_logic_vector(7 downto 0); + GitTime_Min : std_logic_vector(7 downto 0); + GitTime_Sec : std_logic_vector(7 downto 0); + GitTime_Zone : std_logic_vector(7 downto 0); + + BranchName_Tag : std_logic_vector(511 downto 0); + + GitURL : std_logic_vector(1023 downto 0); + end record; + + type T_Version_Register_UID is record + UID : std_logic_vector(127 downto 0); + User_eFuse : std_logic_vector(31 downto 0); + User_ID : std_logic_vector(95 downto 0); + end record; + + constant C_VERSION_REGISTER_UID_INIT : T_Version_Register_UID := ( + UID => (others => '0'), + User_eFuse => (others => '0'), + User_ID => (others => '0') + ); + + constant C_Num_reg_UID_vec : T_NATVEC := ( + 0 => C_VERSION_REGISTER_UID_INIT.UID'length / 32, + 1 => C_VERSION_REGISTER_UID_INIT.User_eFuse'length / 32, + 2 => C_VERSION_REGISTER_UID_INIT.User_ID'length / 32 + ); + + constant C_Num_Reg_Common : natural := 8; + constant C_Num_Reg_Top : natural := 56; + constant C_Num_Reg_UID : natural := isum(C_Num_reg_UID_vec); + + + constant C_Num_Version_Header : natural := C_Num_Reg_Common + C_Num_Reg_Top; + constant C_Num_Version_Register : natural := C_Num_Version_Header + C_Num_Reg_UID; + + function to_SLVV_32_Common (data : T_Version_Register_Common) return T_SLVV_32; + function to_SLVV_32_Top (data : T_Version_Register_Top) return T_SLVV_32; + function get_Dummy_Descriptor(len : natural) return T_AXI4_Register_Vector; + + function get_Version_Descriptor return T_AXI4_Register_Vector; + + impure function read_Version_from_mem(FileName : string) return T_SLVV_32; +end package; + + +package body mem_GitVersionRegister is + + function get_Version_Descriptor return T_AXI4_Register_Vector is + variable temp : T_AXI4_Register_Vector(0 to 127); + variable pos : natural := 0; + variable addr : natural := 0; + begin + temp(pos) := to_AXI4_Register(Name => "Common.BuildDate", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + temp(pos) := to_AXI4_Register(Name => "Common.NumberModule_VersionOfVersionReg", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + temp(pos) := to_AXI4_Register(Name => "Common.VivadoVersion", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + for i in 0 to 4 loop + temp(pos) := to_AXI4_Register(Name => "Common.ProjektName(" & integer'image(i) & ")", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + end loop; + + + temp(pos) := to_AXI4_Register(Name => "Top.Version", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + for i in 0 to 4 loop + temp(pos) := to_AXI4_Register(Name => "Top.GitHash(" & integer'image(i) & ")" , Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + end loop; + temp(pos) := to_AXI4_Register(Name => "Top.GitDate", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + temp(pos) := to_AXI4_Register(Name => "Top.GitTime", Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + for i in 0 to 15 loop + temp(pos) := to_AXI4_Register(Name => "Top.BranchName_Tag(" & integer'image(i) & ")" , Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + end loop; + for i in 0 to 31 loop + temp(pos) := to_AXI4_Register(Name => "Top.GitURL(" & integer'image(i) & ")" , Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + end loop; + + for i in 0 to C_Num_reg_UID_vec(0) -1 loop + temp(pos) := to_AXI4_Register(Name => "UID.UID(" & integer'image(i) & ")" , Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + end loop; + temp(pos) := to_AXI4_Register(Name => "UID.User_eFuse" , Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + for i in 0 to C_Num_reg_UID_vec(2) -1 loop + temp(pos) := to_AXI4_Register(Name => "UID.User_ID(" & integer'image(i) & ")" , Address => to_unsigned(addr, 32), RegisterMode => ReadOnly_NotRegistered); + addr := addr +4; pos := pos +1; + end loop; + + return temp(0 to pos -1); + end function; + + + function get_Dummy_Descriptor(len : natural) return T_AXI4_Register_Vector is + variable descriptor : T_AXI4_Register_Vector(0 to len -1); + begin + for i in descriptor'range loop + descriptor(i) := to_AXI4_Register( + Name => "Dummy(" & integer'image(i) & ")", + Address => to_unsigned(i *4,Address_Width), + RegisterMode => ReadOnly_NotRegistered); + end loop; + return descriptor; + end function; + + + function to_SLVV_32_Common(data : T_Version_Register_Common) return T_SLVV_32 is + variable temp : T_SLVV_32(0 to 7) := (others => (others => '0')); + variable name : T_SLVV_32(4 downto 0) := to_slvv_32(data.ProjektName); + begin + temp(0) := data.BuildDate_Day & data.BuildDate_Month & data.BuildDate_Year; + temp(1) := data.NumberModule & data.VersionOfVersionReg; + temp(2) := data.VivadoVersion_Year & data.VivadoVersion_Release & data.VivadoVersion_SubRelease; + for i in name'reverse_range loop + temp(i +3) := name(i); + end loop; + + return temp; + end function; + + function to_SLVV_32_Top(data : T_Version_Register_Top) return T_SLVV_32 is + variable temp : T_SLVV_32(0 to 55) := (others => (others => '0')); + + variable hash : T_SLVV_32(4 downto 0) := to_slvv_32(data.GitHash); + variable name : T_SLVV_32(15 downto 0) := to_slvv_32(data.BranchName_Tag); + variable url : T_SLVV_32(31 downto 0) := to_slvv_32(data.GitURL); + + variable idx : natural := 0; + begin + temp(0) := data.Version_Major & data.Version_Minor & data.Version_Release & data.Version_Flags; + idx := idx +1; + + for i in hash'reverse_range loop + temp(i +1) := hash(i); + idx := idx +1; + end loop; + + temp(idx) := data.GitDate_Day & data.GitDate_Month & data.GitDate_Year; + idx := idx +1; + temp(idx) := data.GitTime_Hour & data.GitTime_Min & data.GitTime_Sec & data.GitTime_Zone; + idx := idx +1; + + for i in name'reverse_range loop + temp(idx) := name(i); + idx := idx +1; + end loop; + + for i in url'reverse_range loop + temp(idx) := url(i); + idx := idx +1; + end loop; + + return temp; + end function; + + impure function read_Version_from_mem(FileName : string) return T_SLVV_32 is + constant Verbose : boolean := POC_VERBOSE; + constant MemoryLines : positive := C_Num_Version_Header; + variable HW_BUILD_VERSION_COMMON : T_Version_Register_Common; + variable HW_BUILD_VERSION_TOP : T_Version_Register_Top; + + file FileHandle : TEXT open READ_MODE is FileName; + variable CurrentLine : LINE; + variable TempWord : string(1 to 3); + variable Good : boolean; + variable Len : natural; + + constant Init : string(1 to 128) := (others => NUL); + variable result_s : string(1 to 128) := Init; + variable result_h : std_logic_vector(159 downto 0); + + variable temp_signed : signed(7 downto 0); + variable temp : T_SLVV_32(0 to MemoryLines -1) := (others => (others => '0')); + + begin + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.BuildDate_Day := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.BuildDate_Month := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.BuildDate_Year := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 16)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.NumberModule := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 24)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.VersionOfVersionReg := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.VivadoVersion_Year := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 16)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.VivadoVersion_Release := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_COMMON.VivadoVersion_SubRelease := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report result_s(1 to Len) severity note; + HW_BUILD_VERSION_COMMON.ProjektName := to_slv(to_RawString(resize(result_s(1 to Len), 20, NUL))); + + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.Version_Major := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.Version_Minor := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.Version_Release := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.Version_Flags(7 downto 2) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 6)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.Version_Flags(1 downto 1) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 1)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.Version_Flags(0 downto 0) := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 1)); + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + hread(CurrentLine, result_h(Len * 4 -1 downto 0), Good); + assert not Verbose report "get_slv_h: " & integer'image(Len) severity NOTE; + HW_BUILD_VERSION_TOP.GitHash := result_h(Len * 4 -1 downto 0); + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.GitDate_Day := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.GitDate_Month := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.GitDate_Year := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 16)); + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.GitTime_Hour := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.GitTime_Min := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report "get_slv_d(): " & result_s(1 to Len) severity Note; + HW_BUILD_VERSION_TOP.GitTime_Sec := std_logic_vector(to_unsigned(to_natural_dec(result_s(1 to Len)), 8)); + + readline(FileHandle, CurrentLine); + read(CurrentLine, TempWord, Good); + assert not Verbose report result_s(1 to Len) severity note; + if not Good then + report "Error while reading memory file '" & FileName & "'." severity FAILURE; + return temp; + end if; + if TempWord(1) = '-' then + temp_signed := to_signed(-1* to_natural_dec(TempWord(2 to TempWord'high)),8); + else + temp_signed := to_signed(to_natural_dec(TempWord(2 to TempWord'high)),8); + end if; + HW_BUILD_VERSION_TOP.GitTime_Zone := std_logic_vector(temp_signed); + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report result_s(1 to Len) severity note; + HW_BUILD_VERSION_TOP.BranchName_Tag := to_slv(to_RawString(resize(result_s(1 to Len), 64, NUL))); + + readline(FileHandle, CurrentLine); + Len := CurrentLine'length; + read(CurrentLine, result_s(1 to Len), Good); + assert not Verbose report result_s(1 to Len) severity note; + HW_BUILD_VERSION_TOP.GitURL := to_slv(to_RawString(resize(result_s(1 to Len), 128, NUL))); + + temp(0 to C_Num_Reg_Common - 1) := to_SLVV_32_Common(HW_BUILD_VERSION_COMMON); + temp(C_Num_Reg_Common to C_Num_Version_Header - 1) := to_SLVV_32_Top(HW_BUILD_VERSION_TOP); + + return temp; + end function; +end package body; diff --git a/src/mem/ocram/ocram_esdp.files b/src/mem/ocram/ocram_esdp.files deleted file mode 100644 index 9313e3119..000000000 --- a/src/mem/ocram/ocram_esdp.files +++ /dev/null @@ -1,23 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -vhdl poc "src/mem/mem.pkg.vhdl" # Memory package - -# PoC.mem.ocram -vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM -if (DeviceVendor = "Altera") then - include "lib/Altera.files" - vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific extended simple dual-port RAM -end if -if (Environment = "Simulation") then - vhdl poc "src/mem/ocram/ocram_tdp_sim.vhdl" # Simulation model -end if -vhdl poc "src/mem/ocram/ocram_tdp.vhdl" # True dual-port RAM -vhdl poc "src/mem/ocram/ocram_esdp.vhdl" # Extended simple dual-port RAM diff --git a/src/mem/ocram/ocram_sdp.files b/src/mem/ocram/ocram_sdp.files deleted file mode 100644 index abb4b4b1f..000000000 --- a/src/mem/ocram/ocram_sdp.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -vhdl poc "src/mem/mem.pkg.vhdl" # Memory package - -# PoC.mem.ocram -vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM -if (Environment = "Simulation") then - vhdl poc "src/mem/ocram/ocram_tdp_sim.vhdl" # Simulation model -end if -vhdl poc "src/mem/ocram/ocram_sdp.vhdl" # Simple dual-port RAM diff --git a/src/mem/ocram/ocram_sdp_wf.files b/src/mem/ocram/ocram_sdp_wf.files deleted file mode 100644 index 06b94eb39..000000000 --- a/src/mem/ocram/ocram_sdp_wf.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" - -# PoC.mem.ocram -include "src/mem/ocram/ocram_sdp.files" -vhdl poc "src/mem/ocram/ocram_sdp_wf.vhdl" diff --git a/src/mem/ocram/ocram_sp.files b/src/mem/ocram/ocram_sp.files deleted file mode 100644 index d7cd9dc1f..000000000 --- a/src/mem/ocram/ocram_sp.files +++ /dev/null @@ -1,19 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -vhdl poc "src/mem/mem.pkg.vhdl" # Memory package - -# PoC.mem.ocram -vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM -if (DeviceVendor = "Altera") then - include "lib/Altera.files" - vhdl poc "src/mem/ocram/altera/ocram_sp_altera.vhdl" # Altera specific single-port RAM -end if -vhdl poc "src/mem/ocram/ocram_sp.vhdl" # Single-port RAM diff --git a/src/mem/ocram/ocram_tdp.files b/src/mem/ocram/ocram_tdp.files deleted file mode 100644 index 2f5ac3c90..000000000 --- a/src/mem/ocram/ocram_tdp.files +++ /dev/null @@ -1,22 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -vhdl poc "src/mem/mem.pkg.vhdl" # Memory package - -# PoC.mem.ocram -vhdl poc "src/mem/ocram/ocram.pkg.vhdl" # On-Chip-RAM -if (DeviceVendor = "Altera") then - include "lib/Altera.files" - vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific true dual-port RAM -end if -if (Environment = "Simulation") then - vhdl poc "src/mem/ocram/ocram_tdp_sim.vhdl" # Simulation model -end if -vhdl poc "src/mem/ocram/ocram_tdp.vhdl" # True dual-port RAM diff --git a/src/mem/ocram/ocram_tdp_wf.files b/src/mem/ocram/ocram_tdp_wf.files deleted file mode 100644 index 34a7c4b92..000000000 --- a/src/mem/ocram/ocram_tdp_wf.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" - -# PoC.mem.ocram -include "src/mem/ocram/ocram_tdp.files" -vhdl poc "src/mem/ocram/ocram_tdp_wf.vhdl" diff --git a/src/mem/ocrom/ocrom_dp.files b/src/mem/ocrom/ocrom_dp.files deleted file mode 100644 index c04e201fb..000000000 --- a/src/mem/ocrom/ocrom_dp.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -vhdl poc "src/mem/mem.pkg.vhdl" # Memory package - -# PoC.mem.ocram -vhdl poc "src/mem/ocram/ocrom.pkg.vhdl" # On-Chip-RAM -if (DeviceVendor = "Altera") then - vhdl poc "src/mem/ocram/altera/ocram_tdp_altera.vhdl" # Altera specific true dual-port RAM -end if -vhdl poc "src/mem/ocram/ocrom_dp.vhdl" # Dual-port RAM diff --git a/src/mem/ocrom/ocrom_sp.files b/src/mem/ocrom/ocrom_sp.files deleted file mode 100644 index d284efe75..000000000 --- a/src/mem/ocrom/ocrom_sp.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem -vhdl poc "src/mem/mem.pkg.vhdl" # Memory package - -# PoC.mem.ocram -vhdl poc "src/mem/ocram/ocrom.pkg.vhdl" # On-Chip-RAM -if (DeviceVendor = "Altera") then - vhdl poc "src/mem/ocram/altera/ocram_sp_altera.vhdl" # Altera specific single-port RAM -end if -vhdl poc "src/mem/ocram/ocrom_sp.vhdl" # Single-port RAM diff --git a/src/mem/sdram/sdram_ctrl_de0.files b/src/mem/sdram/sdram_ctrl_de0.files deleted file mode 100644 index c8abdbf56..000000000 --- a/src/mem/sdram/sdram_ctrl_de0.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.sdram -if (DeviceVendor = "Altera") then - include "lib/Altera.files" # Altera primitives - vhdl poc "src/mem/sdram/sdram_ctrl_phy_de0.vhdl" # Physical layer abstraction for the Terrasic DE0 board - vhdl poc "src/mem/sdram/sdram_ctrl_fsm.vhdl" # SDR/DDR SDRAM controller FSM - vhdl poc "src/mem/sdram/sdram_ctrl_de0.vhdl" # Top-Level -else - report "This SDRAM controller supports only the 'DE0' board." -end if diff --git a/src/mem/sdram/sdram_ctrl_s3esk.files b/src/mem/sdram/sdram_ctrl_s3esk.files deleted file mode 100644 index a83489a2c..000000000 --- a/src/mem/sdram/sdram_ctrl_s3esk.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.mem.sdram -if (DeviceVendor = "Xilinx") then - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/mem/sdram/sdram_ctrl_phy_s3esk.vhdl" # Physical layer abstraction for the Spartan-3E Starter Kit board - vhdl poc "src/mem/sdram/sdram_ctrl_fsm.vhdl" # SDR/DDR SDRAM controller FSM - vhdl poc "src/mem/sdram/sdram_ctrl_s3esk.vhdl" # Top-Level -else - report "This SDRAM controller supports only the 'Spartan-3E Starter Kit' board." -end if diff --git a/src/misc/filter/filter_and.files b/src/misc/filter/filter_and.files deleted file mode 100644 index 8a3a43aa8..000000000 --- a/src/misc/filter/filter_and.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.filter -vhdl poc "src/misc/filter/filter_and.vhdl" # Top-Level diff --git a/src/misc/filter/filter_mean.files b/src/misc/filter/filter_mean.files deleted file mode 100644 index 51571044e..000000000 --- a/src/misc/filter/filter_mean.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.filter -vhdl poc "src/misc/filter/filter_mean.vhdl" # Top-Level diff --git a/src/misc/filter/filter_or.files b/src/misc/filter/filter_or.files deleted file mode 100644 index fcc297a1b..000000000 --- a/src/misc/filter/filter_or.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.filter -vhdl poc "src/misc/filter/filter_or.vhdl" # Top-Level diff --git a/src/misc/gearbox/gearbox.pro b/src/misc/gearbox/gearbox.pro index 46a83b858..822dd06c8 100644 --- a/src/misc/gearbox/gearbox.pro +++ b/src/misc/gearbox/gearbox.pro @@ -1,5 +1,24 @@ +# ============================================================================= +# Authors: Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= analyze ./gearbox_down_cc.vhdl -# analyze ./gearbox_down_dc.vhdl +analyze ./gearbox_down_dc.vhdl analyze ./gearbox_up_cc.vhdl -# analyze ./gearbox_up_dc.vhdl +analyze ./gearbox_up_dc.vhdl diff --git a/src/misc/gearbox/gearbox_down_cc.files b/src/misc/gearbox/gearbox_down_cc.files deleted file mode 100644 index 07be40d34..000000000 --- a/src/misc/gearbox/gearbox_down_cc.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.gearbox -vhdl poc "src/misc/gearbox/gearbox_down_cc.vhdl" # Top-Level diff --git a/src/misc/gearbox/gearbox_down_dc.files b/src/misc/gearbox/gearbox_down_dc.files deleted file mode 100644 index dbf03a701..000000000 --- a/src/misc/gearbox/gearbox_down_dc.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.gearbox -vhdl poc "src/misc/gearbox/gearbox_down_dc.vhdl" # Top-Level diff --git a/src/misc/gearbox/gearbox_up_cc.files b/src/misc/gearbox/gearbox_up_cc.files deleted file mode 100644 index d80fcb988..000000000 --- a/src/misc/gearbox/gearbox_up_cc.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.gearbox -vhdl poc "src/misc/gearbox/gearbox_up_cc.vhdl" # Top-Level diff --git a/src/misc/gearbox/gearbox_up_dc.files b/src/misc/gearbox/gearbox_up_dc.files deleted file mode 100644 index 2666d5c62..000000000 --- a/src/misc/gearbox/gearbox_up_dc.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.gearbox -vhdl poc "src/misc/gearbox/gearbox_up_dc.vhdl" # Top-Level diff --git a/src/misc/misc.pro b/src/misc/misc.pro index 8bdcd6a3c..d961e1e14 100644 --- a/src/misc/misc.pro +++ b/src/misc/misc.pro @@ -1,14 +1,34 @@ # ============================================================================= -# Authors: -# Adrian Weiland +# Authors: Adrian Weiland +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= analyze ./misc_Delay.vhdl +analyze ./misc_Sequencer.vhdl +analyze ./misc_StrobeGenerator.vhdl +analyze ./misc_StrobeLimiter.vhdl +analyze ./misc_StrobeStretcher.vhdl analyze ./misc_FrequencyMeasurement.vhdl - -# analyze ./stat/stat.pkg.vhdl +analyze ./misc_bit_lz.vhdl include ./filter/filter.pro +include ./stat/stat.pro # Included in PoC.pro for cross-dependency -# include ./gearbox/gearbox.pro +include ./gearbox/gearbox.pro diff --git a/src/misc/misc_Delay.files b/src/misc/misc_Delay.files deleted file mode 100644 index 0f86dee77..000000000 --- a/src/misc/misc_Delay.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc -vhdl poc "src/misc/misc_Delay.vhdl" # Top-Level diff --git a/src/misc/misc_FrequencyMeasurement.files b/src/misc/misc_FrequencyMeasurement.files deleted file mode 100644 index 12531b218..000000000 --- a/src/misc/misc_FrequencyMeasurement.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc -vhdl poc "src/misc/misc_FrequencyMeasurement.vhdl" # Top-Level diff --git a/src/misc/misc_Sequencer.vhdl b/src/misc/misc_Sequencer.vhdl new file mode 100644 index 000000000..c2b9acfb2 --- /dev/null +++ b/src/misc/misc_Sequencer.vhdl @@ -0,0 +1,114 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================ +-- Module: misc_Sequencer +-- +-- Authors: Patrick Lehmann +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +use work.utils.ALL; + +ENTITY misc_Sequencer IS + GENERIC ( + INPUT_BITS : POSITIVE := 32; + OUTPUT_BITS : POSITIVE := 8; + REGISTERED : BOOLEAN := FALSE + ); + PORT ( + Clock : IN STD_LOGIC; + Reset : IN STD_LOGIC; + + Input : IN STD_LOGIC_VECTOR(INPUT_BITS - 1 DOWNTO 0); + rst : IN STD_LOGIC; + rev : IN STD_LOGIC; + nxt : IN STD_LOGIC; + Output : OUT STD_LOGIC_VECTOR(OUTPUT_BITS - 1 DOWNTO 0) + ); +END; + + +ARCHITECTURE rtl OF misc_Sequencer IS + CONSTANT CHUNKS : POSITIVE := div_ceil(INPUT_BITS, OUTPUT_BITS); + CONSTANT COUNTER_BITS : POSITIVE := log2ceilnz(CHUNKS); + + SUBTYPE T_CHUNK IS STD_LOGIC_VECTOR(OUTPUT_BITS - 1 DOWNTO 0); + TYPE T_MUX IS ARRAY (NATURAL RANGE <>) OF T_CHUNK; + + SIGNAL Mux_Data : T_MUX(CHUNKS - 1 DOWNTO 0); + SIGNAL Mux_Data_d : T_MUX(CHUNKS - 1 DOWNTO 0); + SIGNAL Mux_sel_us : UNSIGNED(COUNTER_BITS - 1 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL rev_l : STD_LOGIC := '0'; + +BEGIN + genMuxData : FOR I IN 0 TO CHUNKS - 1 generate + Mux_Data(I) <= Input(((I + 1) * OUTPUT_BITS) - 1 DOWNTO I * OUTPUT_BITS); + END generate; + + genRegistered : IF (REGISTERED = TRUE) generate + PROCESS(Clock) + BEGIN + IF rising_edge(Clock) THEN + IF (Reset = '1') THEN + Mux_Data_d <= (OTHERS => (OTHERS => '0')); + ELSE + Mux_Data_d <= Mux_Data; + END IF; + END IF; + END PROCESS; + else generate + Mux_Data_d <= Mux_Data; + end generate; + + PROCESS(Clock) + BEGIN + IF rising_edge(Clock) THEN + IF ((Reset OR rst) = '1') THEN + rev_l <= rev; + + IF (rev = '0') THEN + Mux_sel_us <= to_unsigned(0, Mux_sel_us'length); + ELSE + Mux_sel_us <= to_unsigned((CHUNKS - 1), Mux_sel_us'length); + END IF; + ELSE + IF (nxt = '1') THEN + IF (rev_l = '0') THEN + Mux_sel_us <= Mux_sel_us + 1; + ELSE + Mux_sel_us <= Mux_sel_us - 1; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + Output <= Mux_Data_d(ite((SIMULATION = TRUE), imin(to_integer(Mux_sel_us), CHUNKS - 1), to_integer(Mux_sel_us))); +END ARCHITECTURE; diff --git a/src/misc/misc_StrobeGenerator.vhdl b/src/misc/misc_StrobeGenerator.vhdl new file mode 100644 index 000000000..b36d4ac6d --- /dev/null +++ b/src/misc/misc_StrobeGenerator.vhdl @@ -0,0 +1,74 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Stefan Unrein +-- +-- Entity: misc_StrobeGenerator +-- +-- Description: +-- ------------------------------------- +-- .. TODO:: No documentation available. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + + +use work.utils.all; +use work.components.all; + + +entity misc_StrobeGenerator is + generic ( + COUNTER_BITS : positive := 16; + INITIAL_STROBE : boolean := TRUE + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + Enable : in std_logic; + Strobe_Period_Cylces : in unsigned(COUNTER_BITS -1 downto 0); + Out_Strobe : out std_logic + ); +end entity; + + +architecture rtl of misc_StrobeGenerator is + signal Counter_s : signed(COUNTER_BITS downto 0) := ite(INITIAL_STROBE, (COUNTER_BITS downto 0 => '0'), ('0' & (COUNTER_BITS -1 downto 0 => '1'))); + signal Counter_neg : std_logic; + +begin + + process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' and INITIAL_STROBE then + Counter_s <= (others => '0'); + else + Counter_s <= downcounter_next(cnt => Counter_s, rst => (Counter_neg or Reset), en => Enable, init => (Strobe_Period_Cylces -2)); + end if; + end if; + end process; + + Counter_neg <= downcounter_neg(cnt => Counter_s); + Out_Strobe <= Counter_neg; +end architecture; diff --git a/src/misc/misc_StrobeLimiter.vhdl b/src/misc/misc_StrobeLimiter.vhdl new file mode 100644 index 000000000..599200e55 --- /dev/null +++ b/src/misc/misc_StrobeLimiter.vhdl @@ -0,0 +1,151 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Stefan Unrein +-- +-- Entity: misc_StrobeLimiter +-- +-- Description: +-- ------------------------------------- +-- .. TODO:: No documentation available. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + + +use work.utils.all; + + +entity misc_StrobeLimiter is + generic ( + MIN_STROBE_PERIOD_CYCLES : positive := 16; + INITIAL_LOCKED : boolean := FALSE; + INITIAL_STROBE : boolean := TRUE + ); + port ( + Clock : in std_logic; + Input_Strobe : in std_logic; + Output_Strobe : out std_logic + ); +end entity; + + +architecture rtl of misc_StrobeLimiter is + constant COUNTER_INIT_VALUE : positive := MIN_STROBE_PERIOD_CYCLES - 2; + constant COUNTER_BITS : natural := log2ceilnz(COUNTER_INIT_VALUE); + + type T_STATE is (ST_IDLE, ST_LOCKED, ST_LOCKED2); + + function InitialState(InitialLocked : boolean; InitialStrobe : boolean) return T_STATE is + begin + if InitialLocked then + if InitialStrobe then + return ST_LOCKED2; + else + return ST_LOCKED; + end if; + else + return ST_IDLE; + end if; + end; + + signal State : T_STATE := InitialState(INITIAL_LOCKED, INITIAL_STROBE); + signal NextState : T_STATE; + + signal Counter_en : std_logic; + signal Counter_s : signed(COUNTER_BITS downto 0) := to_signed(COUNTER_INIT_VALUE, COUNTER_BITS + 1); + signal Counter_ov : std_logic; + +begin + + process(Clock) + begin + if rising_edge(Clock) then + State <= NextState; + end if; + end process; + + process(all) + begin + NextState <= State; + + Counter_en <= '0'; + Output_Strobe <= '0'; + + case State is + when ST_IDLE => + if (Input_Strobe = '1') then + Output_Strobe <= '1'; + + NextState <= ST_LOCKED; + end if; + + when ST_LOCKED => + Counter_en <= '1'; + + if (Input_Strobe = '1') then + if (Counter_ov = '1') then + Counter_en <= '0'; + Output_Strobe <= '1'; + else + NextState <= ST_LOCKED2; + end if; + else + if (Counter_ov = '1') then + NextState <= ST_IDLE; + end if; + end if; + + when ST_LOCKED2 => + Counter_en <= '1'; + + if (Input_Strobe = '1') then + if (Counter_ov = '1') then + Counter_en <= '0'; + Output_Strobe <= '1'; + end if; + else + if (Counter_ov = '1') then + Output_Strobe <= '1'; + NextState <= ST_IDLE; + end if; + end if; + + end case; + end process; + + -- counter + process(Clock) + begin + if rising_edge(Clock) then + if (Counter_en = '0') then + Counter_s <= to_signed(COUNTER_INIT_VALUE, Counter_s'length); + else + Counter_s <= Counter_s - 1; + end if; + end if; + end process; + + Counter_ov <= Counter_s(Counter_s'high); + +end; diff --git a/src/misc/misc_StrobeStretcher.vhdl b/src/misc/misc_StrobeStretcher.vhdl new file mode 100644 index 000000000..a2fe8f788 --- /dev/null +++ b/src/misc/misc_StrobeStretcher.vhdl @@ -0,0 +1,81 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Stefan Unrein +-- +-- Entity: Module to stretch an incoming strobe impulse +-- +-- Description: +-- ------------------------------------- +-- This module stretches an incoming strobe impulse to a long output pulse that +-- is asserted for ``OUTPUT_CYCLES`` to high. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + + +use work.utils.all; +use work.components.all; + + +entity misc_StrobeStretcher is + generic ( + BITS : positive := 1; + OUTPUT_CYCLES : positive + ); + port ( + Clock : in std_logic; + Input : in std_logic_vector(BITS -1 downto 0); + Output : out std_logic_vector(BITS -1 downto 0) := (others => '0') + ); +end entity; + + +architecture rtl of misc_StrobeStretcher is + constant COUNTER_INIT_VALUE : positive := OUTPUT_CYCLES - 2; + constant COUNTER_BITS : natural := log2ceilnz(COUNTER_INIT_VALUE + 1); + +begin + Bit_gen : for i in Input'range generate + + signal Counter_s : signed(COUNTER_BITS downto 0) := to_signed(-1, COUNTER_BITS + 1); + signal Counter_ov : std_logic; + + begin + -- counter + process(Clock) + begin + if rising_edge(Clock) then + if (Input(i) = '1') then + Counter_s <= to_signed(COUNTER_INIT_VALUE, Counter_s'length); + elsif (Counter_ov = '0') then + Counter_s <= Counter_s - 1; + end if; + end if; + end process; + + Counter_ov <= Counter_s(Counter_s'high); + + Output(i) <= ffsr(q => Output(i), rst => Counter_ov, set => Input(i)) when rising_edge(Clock); + end generate; +end architecture; diff --git a/src/misc/stat/stat.pro b/src/misc/stat/stat.pro new file mode 100644 index 000000000..751931132 --- /dev/null +++ b/src/misc/stat/stat.pro @@ -0,0 +1,24 @@ +# ============================================================================= +# Authors: Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./stat_Average.vhdl +analyze ./stat_Histogram.vhdl +analyze ./stat_Maximum.vhdl +analyze ./stat_Minimum.vhdl diff --git a/src/misc/stat/stat_Average.files b/src/misc/stat/stat_Average.files deleted file mode 100644 index 3acf08f1f..000000000 --- a/src/misc/stat/stat_Average.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -include "src/arith/arith_div.files" # pipelined division - -# PoC.misc.stat -vhdl poc "src/misc/stat/stat_Average.vhdl" # Top-Level diff --git a/src/misc/stat/stat_Histogram.files b/src/misc/stat/stat_Histogram.files deleted file mode 100644 index a4fa02d8c..000000000 --- a/src/misc/stat/stat_Histogram.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.stat -vhdl poc "src/misc/stat/stat_Histogram.vhdl" # Top-Level diff --git a/src/misc/stat/stat_Maximum.files b/src/misc/stat/stat_Maximum.files deleted file mode 100644 index 284d7339f..000000000 --- a/src/misc/stat/stat_Maximum.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.stat -vhdl poc "src/misc/stat/stat_Maximum.vhdl" # Top-Level diff --git a/src/misc/stat/stat_Minimum.files b/src/misc/stat/stat_Minimum.files deleted file mode 100644 index 260050dd6..000000000 --- a/src/misc/stat/stat_Minimum.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.stat -vhdl poc "src/misc/stat/stat_Minimum.vhdl" # Top-Level diff --git a/src/net/arp/arp.pro b/src/net/arp/arp.pro new file mode 100644 index 000000000..280b72d31 --- /dev/null +++ b/src/net/arp/arp.pro @@ -0,0 +1,28 @@ +# ============================================================================= +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./arp_IPPool.vhdl +analyze ./arp_BroadCast_Receiver.vhdl +analyze ./arp_BroadCast_Requester.vhdl +analyze ./arp_Cache.vhdl +analyze ./arp_UniCast_Receiver.vhdl +analyze ./arp_UniCast_Responder.vhdl +analyze ./arp_Wrapper.vhdl diff --git a/src/net/icmpv4/icmpv4.pro b/src/net/icmpv4/icmpv4.pro new file mode 100644 index 000000000..7b0107bf3 --- /dev/null +++ b/src/net/icmpv4/icmpv4.pro @@ -0,0 +1,24 @@ +# ============================================================================= +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./icmpv4_RX.vhdl +analyze ./icmpv4_TX.vhdl +analyze ./icmpv4_Wrapper.vhdl diff --git a/src/net/ipv4/ipv4.pro b/src/net/ipv4/ipv4.pro new file mode 100644 index 000000000..9d766a742 --- /dev/null +++ b/src/net/ipv4/ipv4.pro @@ -0,0 +1,25 @@ +# ============================================================================= +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./ipv4_FrameLoopback.vhdl +analyze ./ipv4_RX.vhdl +analyze ./ipv4_TX.vhdl +analyze ./ipv4_Wrapper.vhdl diff --git a/src/net/ipv6/ipv6.pro b/src/net/ipv6/ipv6.pro new file mode 100644 index 000000000..3b0cf205e --- /dev/null +++ b/src/net/ipv6/ipv6.pro @@ -0,0 +1,25 @@ +# ============================================================================= +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./ipv6_FrameLoopback.vhdl +analyze ./ipv6_RX.vhdl +analyze ./ipv6_TX.vhdl +analyze ./ipv6_Wrapper.vhdl diff --git a/src/net/mac/mac.pro b/src/net/mac/mac.pro new file mode 100644 index 000000000..ad92b39a7 --- /dev/null +++ b/src/net/mac/mac.pro @@ -0,0 +1,30 @@ +# ============================================================================= +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./mac_TX_Type_Prepender.vhdl +analyze ./mac_FrameLoopback.vhdl +analyze ./mac_RX_DestMAC_Switch.vhdl +analyze ./mac_RX_SrcMAC_Filter.vhdl +analyze ./mac_RX_Type_Switch.vhdl +analyze ./mac_TX_DestMAC_Prepender.vhdl +analyze ./mac_TX_SrcMAC_Prepender.vhdl +analyze ./mac_Wrapper.vhdl + diff --git a/src/net/mac/mac_TX_Type_Prepender.vhdl b/src/net/mac/mac_TX_Type_Prepender.vhdl new file mode 100644 index 000000000..1a3165d8e --- /dev/null +++ b/src/net/mac/mac_TX_Type_Prepender.vhdl @@ -0,0 +1,225 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Entity: mac_TX_Type_Prepender +-- +-- Description: +-- ------------------------------------- +-- .. TODO:: No documentation available. +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + + +use work.config.all; +use work.utils.all; +use work.vectors.all; +use work.net.all; + + +entity mac_TX_Type_Prepender is + generic ( + DEBUG : boolean := FALSE; + ETHERNET_TYPES : T_NET_MAC_ETHERNETTYPE_VECTOR := (0 => to_net_mac_ethernettype(x"0000")) + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + + In_Valid : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + In_Data : in T_SLVV_8(ETHERNET_TYPES'length - 1 downto 0); + In_SOF : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + In_EOF : in std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + In_Ack : out std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + In_Meta_rst : out std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + In_Meta_DestMACAddress_nxt : out std_logic_vector(ETHERNET_TYPES'length - 1 downto 0); + In_Meta_DestMACAddress_Data : in T_SLVV_8(ETHERNET_TYPES'length - 1 downto 0); + + Out_Valid : out std_logic; + Out_Data : out T_SLV_8; + Out_SOF : out std_logic; + Out_EOF : out std_logic; + Out_Ack : in std_logic; + Out_Meta_rst : in std_logic; + Out_Meta_DestMACAddress_nxt : in std_logic; + Out_Meta_DestMACAddress_Data : out T_SLV_8 + ); +end entity; + + +architecture rtl of mac_TX_Type_Prepender is + attribute FSM_ENCODING : string; + + constant PORTS : positive := ETHERNET_TYPES'length; + + constant META_RST_BIT : natural := 0; + constant META_DEST_NXT_BIT : natural := 1; + + constant META_BITS : positive := 24; + constant META_REV_BITS : positive := 2; + + type T_STATE is ( + ST_IDLE, + ST_PREPEND_TYPE_1, + ST_PAYLOAD + ); + + signal State : T_STATE := ST_IDLE; + signal NextState : T_STATE; + attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", ite((VENDOR = VENDOR_XILINX), "auto", "default")); + + signal LLMux_In_Valid : std_logic_vector(PORTS - 1 downto 0); + signal LLMux_In_Data : T_SLM(PORTS - 1 downto 0, T_SLV_8'range) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) + signal LLMux_In_Meta : T_SLM(PORTS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) + signal LLMux_In_Meta_rev : T_SLM(PORTS - 1 downto 0, META_REV_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) + signal LLMux_In_SOF : std_logic_vector(PORTS - 1 downto 0); + signal LLMux_In_EOF : std_logic_vector(PORTS - 1 downto 0); + signal LLMux_In_Ack : std_logic_vector(PORTS - 1 downto 0); + + signal LLMux_Out_Valid : std_logic; + signal LLMux_Out_Data : T_SLV_8; + signal LLMux_Out_Meta : std_logic_vector(META_BITS - 1 downto 0); + signal LLMux_Out_Meta_rev : std_logic_vector(META_REV_BITS - 1 downto 0); + signal LLMux_Out_SOF : std_logic; + signal LLMux_Out_EOF : std_logic; + signal LLMux_Out_Ack : std_logic; + + signal Is_DataFlow : std_logic; + signal Is_SOF : std_logic; + signal Is_EOF : std_logic; + +begin + + LLMux_In_Valid <= In_Valid; + LLMux_In_Data <= to_slm(In_Data); + LLMux_In_SOF <= In_SOF; + LLMux_In_EOF <= In_EOF; + In_Ack <= LLMux_In_Ack; + + genLLMuxIn : for i in 0 to PORTS - 1 generate + signal Meta : std_logic_vector(META_BITS - 1 downto 0); + begin + Meta (15 downto 0) <= to_slv(ETHERNET_TYPES(i)); + Meta (23 downto 16) <= In_Meta_DestMACAddress_Data(i); + + assign_row(LLMux_In_Meta, Meta, i); + end generate; + + In_Meta_rst <= get_col(LLMux_In_Meta_rev, META_RST_BIT); + In_Meta_DestMACAddress_nxt <= get_col(LLMux_In_Meta_rev, META_DEST_NXT_BIT); + + LLMux : entity work.stream_Mux + generic map ( + PORTS => PORTS, + DATA_BITS => LLMux_Out_Data'length, + META_BITS => LLMux_Out_Meta'length, + META_REV_BITS => LLMux_Out_Meta_rev'length + ) + port map( + Clock => Clock, + Reset => Reset, + + In_Valid => LLMux_In_Valid, + In_Data => LLMux_In_Data, + In_Meta => LLMux_In_Meta, + In_Meta_rev => LLMux_In_Meta_rev, + In_SOF => LLMux_In_SOF, + In_EOF => LLMux_In_EOF, + In_Ack => LLMux_In_Ack, + + Out_Valid => LLMux_Out_Valid, + Out_Data => LLMux_Out_Data, + Out_Meta => LLMux_Out_Meta, + Out_Meta_rev => LLMux_Out_Meta_rev, + Out_SOF => LLMux_Out_SOF, + Out_EOF => LLMux_Out_EOF, + Out_Ack => LLMux_Out_Ack + ); + + LLMux_Out_Meta_rev(META_RST_BIT) <= Out_Meta_rst; + LLMux_Out_Meta_rev(META_DEST_NXT_BIT) <= Out_Meta_DestMACAddress_nxt; + + Is_DataFlow <= LLMux_Out_Valid and Out_Ack; + Is_SOF <= LLMux_Out_Valid and LLMux_Out_SOF; + Is_EOF <= LLMux_Out_Valid and LLMux_Out_EOF; + + process(Clock) + begin + if rising_edge(Clock) then + if (Reset = '1') then + State <= ST_IDLE; + else + State <= NextState; + end if; + end if; + end process; + + process(all) + begin + NextState <= State; + + Out_Valid <= '0'; + Out_Data <= LLMux_Out_Data; + Out_SOF <= '0'; + Out_EOF <= '0'; + + LLMux_Out_Ack <= '0'; + + case State is + when ST_IDLE => + if (Is_SOF = '1') then + Out_Valid <= '1'; + Out_SOF <= '1'; + Out_Data <= LLMux_Out_Meta(15 downto 8); + + if (Out_Ack = '1') then + NextState <= ST_PREPEND_TYPE_1; + end if; + end if; + + when ST_PREPEND_TYPE_1 => + Out_Valid <= '1'; + Out_Data <= LLMux_Out_Meta(7 downto 0); + + if (Out_Ack = '1') then + NextState <= ST_PAYLOAD; + end if; + + when ST_PAYLOAD => + Out_Valid <= LLMux_Out_Valid; + Out_EOF <= LLMux_Out_EOF; + LLMux_Out_Ack <= Out_Ack; + + if ((Is_DataFlow and Is_EOF) = '1') then + NextState <= ST_IDLE; + end if; + + end case; + end process; + + Out_Meta_DestMACAddress_Data <= LLMux_Out_Meta(23 downto 16); + +end architecture; diff --git a/src/net/net.pro b/src/net/net.pro index 6a08f4fab..93bd70584 100644 --- a/src/net/net.pro +++ b/src/net/net.pro @@ -1,11 +1,30 @@ # ============================================================================= -# Authors: -# Guy Eschemann +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= analyze ./net.pkg.vhdl -# analyze ./eth/eth_GEMAC_RX.vhdl -# analyze ./eth/eth_GEMAC_TX.vhdl -# analyze ./eth/eth_GEMAC_GMII.vhdl +analyze ./net_FrameChecksum.vhdl -analyze ./arp/arp_IPPool.vhdl +include ./arp/arp.pro +include ./icmpv4/icmpv4.pro +include ./ipv4/ipv4.pro +include ./ipv6/ipv6.pro +include ./mac/mac.pro +include ./udp/udp.pro diff --git a/src/net/net_FrameLoopback.vhdl b/src/net/net_FrameLoopback.vhdl deleted file mode 100644 index 3ba954e15..000000000 --- a/src/net/net_FrameLoopback.vhdl +++ /dev/null @@ -1,147 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Entity: TODO --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.NUMERIC_STD.all; - -use work.config.all; -use work.utils.all; -use work.vectors.all; - - -entity FrameLoopback is - generic ( - DATA_BW : positive := 8; - META_BW : natural := 0 - ); - port ( - Clock : in std_logic; - Reset : in std_logic; - - In_Valid : in std_logic; - In_Data : in std_logic_vector(DATA_BW - 1 downto 0); - In_Meta : in std_logic_vector(META_BW - 1 downto 0); - In_SOF : in std_logic; - In_EOF : in std_logic; - In_Ack : out std_logic; - - - Out_Valid : out std_logic; - Out_Data : out std_logic_vector(DATA_BW - 1 downto 0); - Out_Meta : out std_logic_vector(META_BW - 1 downto 0); - Out_SOF : out std_logic; - Out_EOF : out std_logic; - Out_Ack : in std_logic - ); -end entity; - - -architecture rtl of FrameLoopback is - constant META_STREAMID_SRC : natural := 0; - constant META_STREAMID_DEST : natural := 1; - constant META_STREAMID_type : natural := 2; - constant META_STREAMS : positive := 3; -- Source, Destination, Type - - signal Meta_rst : std_logic; - signal Meta_nxt : std_logic_vector(META_STREAMS - 1 downto 0); - - signal Pipe_DataOut : T_SLV_8; - signal Pipe_MetaIn : T_SLM(META_STREAMS - 1 downto 0, 31 downto 0) := (others => (others => 'Z')); - signal Pipe_MetaOut : T_SLM(META_STREAMS - 1 downto 0, 31 downto 0); - signal Pipe_Meta_rst : std_logic; - signal Pipe_Meta_nxt : std_logic_vector(META_STREAMS - 1 downto 0); - - signal Pipe_Meta_SrcMACAddress_Data : std_logic_vector(TX_Funnel_SrcIPv6Address_Data'range); - signal Pipe_Meta_DestMACAddress_Data : std_logic_vector(TX_Funnel_DestIPv6Address_Data'range); - signal Pipe_Meta_EthType : std_logic_vector(TX_Funnel_Payload_Type'range); - - -begin - assign_row(Pipe_MetaIn, TX_Meta_SrcIPv6Address_Data(I), META_STREAMID_SRC, 0, '0'); - assign_row(Pipe_MetaIn, TX_Meta_DestIPv6Address_Data(I), META_STREAMID_DEST, 0, '0'); - assign_row(Pipe_MetaIn, TX_Meta_Length(I), META_STREAMID_LEN); - - TX_Meta_rst(I) <= Meta_rst; - TX_Meta_SrcIPv6Address_nxt(I) <= Meta_nxt(META_STREAMID_SRC); - TX_Meta_DestIPv6Address_nxt(I) <= Meta_nxt(META_STREAMID_DEST); - - Pipe: entity work.stream_FIFO - generic map ( - FRAMES => 2, - DATA_BITS => 8, - DATA_FIFO_DEPTH => 16, - META_BITS => (META_STREAMID_SRC => 8, META_STREAMID_DEST => 8, META_STREAMID_LEN => 16), - META_FIFO_DEPTH => (META_STREAMID_SRC => 16, META_STREAMID_DEST => 16, META_STREAMID_LEN => 1) - ) - port map ( - Clock => Clock, - Reset => Reset, - - In_Valid => TX_Valid(I), - In_Data => TX_Data(I), - In_SOF => TX_SOF(I), - In_EOF => TX_EOF(I), - In_Ack => TX_Ack (I), - In_Meta_rst => Meta_rst, - In_Meta_nxt => Meta_nxt, - In_Meta_Data => Pipe_MetaIn, - - Out_Valid => Funnel_In_Valid(I), - Out_Data => Pipe_DataOut, - Out_SOF => Funnel_In_SOF(I), - Out_EOF => Funnel_In_EOF(I), - Out_Ack => Funnel_In_Ack (I), - Out_Meta_rst => Pipe_Meta_rst, - Out_Meta_nxt => Pipe_Meta_nxt, - Out_Meta_Data => Pipe_MetaOut - ); - - -- unpack pipe metadata to signals - Pipe_Meta_SrcIPv6Address_Data <= get_row(Pipe_MetaOut, META_STREAMID_SRC, 8); - Pipe_Meta_DestIPv6Address_Data <= get_row(Pipe_MetaOut, META_STREAMID_DEST, 8); - Pipe_Meta_Length <= get_row(Pipe_MetaOut, META_STREAMID_LEN); - - Pipe_Meta_rst <= Funnel_In_Meta_rev(I, META_RST_BIT); - Pipe_Meta_nxt(META_STREAMID_SRC) <= Funnel_In_Meta_rev(I, META_SRC_NXT_BIT); - Pipe_Meta_nxt(META_STREAMID_DEST) <= Funnel_In_Meta_rev(I, META_DEST_NXT_BIT); - Pipe_Meta_nxt(META_STREAMID_LEN) <= '0'; - - -- pack metadata into 1 dim vector - Funnel_MetaIn(Pipe_Meta_SrcIPv6Address_Data'range) <= Pipe_Meta_SrcIPv6Address_Data; - Funnel_MetaIn(Pipe_Meta_DestIPv6Address_Data'range) <= Pipe_Meta_DestIPv6Address_Data; - Funnel_MetaIn(Pipe_Meta_Length'range) <= Pipe_Meta_Length; - Funnel_MetaIn(Pipe_Meta_Payload_Type'range) <= PACKET_typeS(I); - - -- assign vectors to matrix - assign_row(Funnel_In_Data, Pipe_DataOut, I); - assign_row(Funnel_In_Meta, Funnel_MetaIn, I); - -end architecture; diff --git a/src/net/udp/udp.pro b/src/net/udp/udp.pro new file mode 100644 index 000000000..6d697c324 --- /dev/null +++ b/src/net/udp/udp.pro @@ -0,0 +1,25 @@ +# ============================================================================= +# Authors: Guy Eschemann +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./udp_FrameLoopback.vhdl +analyze ./udp_RX.vhdl +analyze ./udp_TX.vhdl +analyze ./udp_Wrapper.vhdl diff --git a/src/sim/sim.files b/src/sim/sim.files deleted file mode 100644 index 713c705b5..000000000 --- a/src/sim/sim.files +++ /dev/null @@ -1,24 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC simulation packages -if (ToolChain != "Cocotb") then - vhdl poc "src/sim/sim_types.vhdl" # PoC simulation helper - if (VHDLVersion < 2002) then - vhdl poc "src/sim/sim_random.v93.vhdl" # PoC simulation helper - vhdl poc "src/sim/sim_global.v93.vhdl" # PoC simulation helper - vhdl poc "src/sim/sim_unprotected.v93.vhdl" # PoC simulation helper - vhdl poc "src/sim/sim_simulation.v93.vhdl" # PoC simulation helper - elseif (VHDLVersion <= 2008) then - vhdl poc "src/sim/sim_random.v08.vhdl" # PoC simulation helper - vhdl poc "src/sim/sim_protected.v08.vhdl" # PoC simulation helper - vhdl poc "src/sim/sim_global.v08.vhdl" # PoC simulation helper - vhdl poc "src/sim/sim_simulation.v08.vhdl" # PoC simulation helper - else - report "VHDL version not supported." - end if - vhdl poc "src/sim/sim_waveform.vhdl" # PoC simulation helper -end if diff --git a/src/sim/sim.pro b/src/sim/sim.pro new file mode 100644 index 000000000..dead02a9c --- /dev/null +++ b/src/sim/sim.pro @@ -0,0 +1,23 @@ +# ============================================================================= +# Authors: Adrian Weiland +# Jonas Schreiner +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./sim_VCDParser.vhdl diff --git a/src/sim/sim_global.v08.vhdl b/src/sim/sim_global.v08.vhdl deleted file mode 100644 index 86ec329c8..000000000 --- a/src/sim/sim_global.v08.vhdl +++ /dev/null @@ -1,41 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Package: Global simulation constants and shared varibales. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.FileIO.all; -use work.sim_protected.all; - - -package sim_global is - -- The default global status objects. - -- =========================================================================== - shared variable globalSimulationStatus : T_SIM_STATUS; - shared variable globalLogFile : T_LOGFILE; - shared variable globalStdOut : T_STDOUT; -end package; diff --git a/src/sim/sim_global.v93.vhdl b/src/sim/sim_global.v93.vhdl deleted file mode 100644 index ea11c1972..000000000 --- a/src/sim/sim_global.v93.vhdl +++ /dev/null @@ -1,64 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Package: Global simulation constants and shared varibales. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.utils.all; -use work.sim_types.all; - - -package sim_global is - -- The default global status objects. - -- =========================================================================== - shared variable globalSim_StateIsInitialized : boolean := FALSE; - shared variable globalSim_StateIsFinalized : boolean := FALSE; - - shared variable globalSim_MaxAssertFailures : natural := natural'high; - shared variable globalSim_MaxSimulationRuntime : time := time'high; - - -- Internal state variable to log a failure condition for final reporting. - -- Once de-asserted, this variable will never return to a value of true. - shared variable globalSim_Passed : boolean := TRUE; - shared variable globalSim_AssertCount : natural := 0; - shared variable globalSim_FailedAssertCount : natural := 0; - - -- Clock Management - shared variable globalSim_MainProcessEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); - shared variable globalSim_MainClockEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); - - -- Process Management - shared variable globalSim_ProcessCount : natural := 0; - shared variable globalSim_ActiveProcessCount : natural := 0; - shared variable globalSim_Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID); - - -- Test Management - shared variable globalSim_TestCount : natural := 0; - shared variable globalSim_ActiveTestCount : natural := 0; - shared variable globalSim_Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID); - -end package; diff --git a/src/sim/sim_protected.v08.vhdl b/src/sim/sim_protected.v08.vhdl deleted file mode 100644 index 3c27ed035..000000000 --- a/src/sim/sim_protected.v08.vhdl +++ /dev/null @@ -1,488 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- Thomas B. Preusser --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use STD.TextIO.all; - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -use work.utils.all; -use work.strings.all; -use work.vectors.all; -use work.physical.all; - -use work.sim_types.all; - - -package sim_protected is - -- Simulation Task and Status Management - -- =========================================================================== - type T_SIM_STATUS is protected - -- Initializer and Finalizer - procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); - procedure finalize; - - -- Assertions - procedure fail(Message : string := ""); - procedure assertion(Condition : boolean; Message : string := ""); - procedure writeMessage(Message : string); - procedure writeReport; - - -- Process Management - impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; - procedure deactivateProcess(procID : T_SIM_PROCESS_ID; SkipLowPriority : boolean := FALSE); - procedure stopAllProcesses; - procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); - - -- Test Management - procedure createDefaultTest; - impure function createTest(Name : string) return T_SIM_TEST_ID; - procedure activateDefaultTest; - procedure finalizeTest; - procedure finalizeTest(TestID : T_SIM_TEST_ID); - - -- Run Management - procedure stopAllClocks; - procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); - - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; - impure function isAllFinalized return boolean; - end protected; -end package; - - -package body sim_protected is - -- Simulation process and Status Management - -- =========================================================================== - type T_SIM_STATUS_STATE is record - IsInitialized : boolean; - IsFinalized : boolean; - end record; - - type T_SIM_STATUS is protected body - -- status - variable State : T_SIM_STATUS_STATE := (FALSE, FALSE); - - variable Max_AssertFailures : natural := natural'high; - variable Max_SimulationRuntime : time := time'high; - - -- Internal state variable to log a failure condition for final reporting. - -- Once de-asserted, this variable will never return to a value of true. - variable Passed : boolean := TRUE; - variable AssertCount : natural := 0; - variable FailedAssertCount : natural := 0; - - -- Clock Management - variable MainProcessEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); - variable MainClockEnables : T_SIM_BOOLVEC(T_SIM_TEST_ID) := (others => TRUE); - - -- Process Management - variable ProcessCount : natural := 0; - variable ActiveProcessCount : natural := 0; - variable Processes : T_SIM_PROCESS_VECTOR(T_SIM_PROCESS_ID); - - -- Test Management - variable TestCount : natural := 0; - variable ActiveTestCount : natural := 0; - variable Tests : T_SIM_TEST_VECTOR(T_SIM_TEST_ID); - - -- Initializer - procedure init is - begin - if (State.IsInitialized = FALSE) then - if C_SIM_VERBOSE then report "init:" severity NOTE; end if; - State.IsInitialized := TRUE; - createDefaultTest; - end if; - end procedure; - - procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is - begin - if C_SIM_VERBOSE then report "initialize:" severity NOTE; end if; - init; - Max_AssertFailures := MaxAssertFailures; - Max_SimulationRuntime := MaxSimulationRuntime; - end procedure; - - procedure finalize is - begin - if (State.IsFinalized = FALSE) then - if C_SIM_VERBOSE then report "finalize: " severity NOTE; end if; - State.IsFinalized := TRUE; - for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop - finalizeTest(i); - end loop; - writeReport; - end if; - end procedure; - - procedure writeReport_Header is - variable LineBuffer : LINE; - begin - write(LineBuffer, ( string'("========================================"))); - write(LineBuffer, (LF & string'("POC TESTBENCH REPORT"))); - write(LineBuffer, (LF & string'("========================================"))); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_TestReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - if (Tests(C_SIM_DEFAULT_TEST_ID).Status /= SIM_TEST_STATUS_CREATED) then - write(LineBuffer, Prefix & "Tests " & integer'image(TestCount + 1)); - write(LineBuffer, LF & Prefix & " " & str_ralign("-1", log10ceilnz(TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME); - else - write(LineBuffer, Prefix & "Tests " & integer'image(TestCount)); - end if; - for i in 0 to TestCount - 1 loop - write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(TestCount)) & ": " & str_trim(Tests(i).Name)); - end loop; - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_AssertReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - write(LineBuffer, Prefix & "Assertions " & integer'image(AssertCount)); - write(LineBuffer, LF & Prefix & " failed " & integer'image(FailedAssertCount) & ite((FailedAssertCount >= Max_AssertFailures), " Too many failed asserts!", "")); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_ProcessReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - write(LineBuffer, Prefix & "Processes " & integer'image(ProcessCount)); - write(LineBuffer, LF & Prefix & " active " & integer'image(ActiveProcessCount)); - -- report killed processes - for i in 0 to ProcessCount - 1 loop - if ((Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) and (Processes(i).IsLowPriority = FALSE)) then - write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(ProcessCount)) & ": " & str_trim(Processes(i).Name)); - end if; - end loop; - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_RuntimeReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - write(LineBuffer, Prefix & "Runtime " & to_string(now, 1)); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_SimulationResult is - variable LineBuffer : LINE; - begin - write(LineBuffer, ( string'("========================================"))); - if not Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = FAILED"))); - elsif AssertCount = 0 then write(LineBuffer, (LF & string'("SIMULATION RESULT = NO ASSERTS"))); - elsif Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = PASSED"))); - end if; - write(LineBuffer, (LF & string'("========================================"))); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport is - variable LineBuffer : LINE; - begin - writeReport_Header; - writeReport_TestReport(""); - write(LineBuffer, LF & "Overall"); - writeline(output, LineBuffer); - writeReport_AssertReport(" "); - writeReport_ProcessReport(" "); - writeReport_RuntimeReport(" "); - writeReport_SimulationResult; - end procedure; - - procedure assertion(condition : boolean; Message : string := "") is - begin - AssertCount := AssertCount + 1; - if not condition then - fail(Message); - FailedAssertCount := FailedAssertCount + 1; - if (FailedAssertCount >= Max_AssertFailures) then - stopAllProcesses; - end if; - end if; - end procedure; - - procedure fail(Message : string := "") is - begin - if (Message'length > 0) then - report Message severity ERROR; - end if; - Passed := FALSE; - end procedure; - - procedure writeMessage(Message : string) is - variable LineBuffer : LINE; - begin - write(LineBuffer, Message); - writeline(output, LineBuffer); - end procedure; - - procedure createDefaultTest is - variable Test : T_SIM_TEST; - begin - if (State.IsInitialized = FALSE) then - init; - end if; - if C_SIM_VERBOSE then report "createDefaultTest(" & C_SIM_DEFAULT_TEST_NAME & "):" severity NOTE; end if; - Test.ID := C_SIM_DEFAULT_TEST_ID; - Test.Name := resize(C_SIM_DEFAULT_TEST_NAME, T_SIM_TEST_NAME'length); - Test.Status := SIM_TEST_STATUS_CREATED; - Test.ProcessIDs := (others => 0); - Test.ProcessCount := 0; - Test.ActiveProcessCount := 0; - -- add to the internal structure - Tests(Test.ID) := Test; - end procedure; - - impure function createTest(Name : string) return T_SIM_TEST_ID is - variable Test : T_SIM_TEST; - begin - if (State.IsInitialized = FALSE) then - init; - end if; - if C_SIM_VERBOSE then report "createTest(" & Name & "): => " & T_SIM_TEST_ID'image(TestCount) severity NOTE; end if; - Test.ID := TestCount; - Test.Name := resize(Name, T_SIM_TEST_NAME'length); - Test.Status := SIM_TEST_STATUS_ACTIVE; - Test.ProcessIDs := (others => 0); - Test.ProcessCount := 0; - Test.ActiveProcessCount := 0; - -- add to the internal structure - Tests(Test.ID) := Test; - TestCount := TestCount + 1; - ActiveTestCount := ActiveTestCount + 1; - -- return TestID for finalizeTest - return Test.ID; - end function; - - procedure activateDefaultTest is - begin - if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then - Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ACTIVE; - ActiveTestCount := ActiveTestCount + 1; - end if; - end procedure; - - procedure finalizeTest is - begin - finalizeTest(C_SIM_DEFAULT_TEST_ID); - end procedure; - - procedure finalizeTest(TestID : T_SIM_TEST_ID) is - begin - if (TestID >= TestCount) then - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - return; - end if; - - if TestID = C_SIM_DEFAULT_TEST_ID then - if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then - if C_SIM_VERBOSE then report "finalizeTest(" & integer'image(C_SIM_DEFAULT_TEST_ID) & "): inactive" severity NOTE; end if; - Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; - stopProcesses(C_SIM_DEFAULT_TEST_ID); - return; - elsif (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then - if ActiveTestCount > 1 then - for ProcIdx in 0 to Tests(C_SIM_DEFAULT_TEST_ID).ProcessCount - 1 loop - deactivateProcess(Tests(C_SIM_DEFAULT_TEST_ID).ProcessIDs(ProcIdx), TRUE); - end loop; - Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ZOMBI; - return; - else - if C_SIM_VERBOSE then report "finalizeTest(" & integer'image(C_SIM_DEFAULT_TEST_ID) & "): active" severity NOTE; end if; - Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; - ActiveTestCount := ActiveTestCount - 1; - stopProcesses(C_SIM_DEFAULT_TEST_ID); - end if; - end if; - elsif (Tests(TestID).Status /= SIM_TEST_STATUS_ENDED) then - if C_SIM_VERBOSE then report "finalizeTest(TestID=" & T_SIM_TEST_ID'image(TestID) & "): " severity NOTE; end if; - Tests(TestID).Status := SIM_TEST_STATUS_ENDED; - ActiveTestCount := ActiveTestCount - 1; - - if (Tests(TestID).ActiveProcessCount > 0) then - fail("Test " & integer'image(TestID) & " '" & str_trim(Tests(TestID).Name) & "' has still active process while finalizing:"); - for ProcIdx in 0 to Tests(TestID).ProcessCount - 1 loop - if (Processes(Tests(TestID).ProcessIDs(ProcIdx)).Status = SIM_PROCESS_STATUS_ACTIVE) then - report " " & Processes(Tests(TestID).ProcessIDs(ProcIdx)).Name severity WARNING; - end if; - end loop; - end if; - stopProcesses(TestID); - end if; - - if ActiveTestCount = 0 then - finalize; - elsif ActiveTestCount = 1 then - if (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then - finalizeTest(C_SIM_DEFAULT_TEST_ID); - elsif (Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ZOMBI) then - stopProcesses(C_SIM_DEFAULT_TEST_ID); - else - return; - end if; - finalize; - end if; - end procedure; - - impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is - begin - return registerProcess(C_SIM_DEFAULT_TEST_ID, Name, IsLowPriority); - end function; - - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is - variable Proc : T_SIM_PROCESS; - variable TestProcID : T_SIM_TEST_ID; - begin - if (State.IsInitialized = FALSE) then - init; - end if; - if TestID = C_SIM_DEFAULT_TEST_ID then - activateDefaultTest; - end if; - - if (TestID >= TestCount) then - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - return T_SIM_PROCESS_ID'high; - end if; - - if C_SIM_VERBOSE then report "registerProcess(TestID=" & T_SIM_TEST_ID'image(TestID) & ", " & Name & "): => " & T_SIM_PROCESS_ID'image(ProcessCount) severity NOTE; end if; - Proc.ID := ProcessCount; - Proc.TestID := TestID; - Proc.Name := resize(Name, T_SIM_PROCESS_NAME'length); - Proc.Status := SIM_PROCESS_STATUS_ACTIVE; - Proc.IsLowPriority := IsLowPriority; - - -- add process to list - Processes(Proc.ID) := Proc; - ProcessCount := ProcessCount + 1; - ActiveProcessCount := inc_if(not IsLowPriority, ActiveProcessCount); - -- add process to test - TestProcID := Tests(TestID).ProcessCount; - Tests(TestID).ProcessIDs(TestProcID) := Proc.ID; - Tests(TestID).ProcessCount := TestProcID + 1; - Tests(TestID).ActiveProcessCount := inc_if(not IsLowPriority, Tests(TestID).ActiveProcessCount); - -- return the process ID - return Proc.ID; - end function; - - procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID; SkipLowPriority : boolean := FALSE) is - variable TestID : T_SIM_TEST_ID; - begin - if (ProcID >= ProcessCount) then - report "ProcID (" & T_SIM_PROCESS_ID'image(ProcID) & ") is unknown." severity FAILURE; - return; - elsif (Processes(ProcID).IsLowPriority and SkipLowPriority) then - return; - end if; - - TestID := Processes(ProcID).TestID; - -- deactivate process - if (Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then - if C_SIM_VERBOSE then report "deactivateProcess(ProcID=" & T_SIM_PROCESS_ID'image(ProcID) & "): TestID=" & T_SIM_TEST_ID'image(TestID) & " Name=" & str_trim(Processes(ProcID).Name) severity NOTE; end if; - Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED; - ActiveProcessCount := dec_if(not Processes(ProcID).IsLowPriority, ActiveProcessCount); - Tests(TestID).ActiveProcessCount := dec_if(not Processes(ProcID).IsLowPriority, Tests(TestID).ActiveProcessCount); - if (Tests(TestID).ActiveProcessCount = 0) then - finalizeTest(TestID); - end if; - end if; - end procedure; - - procedure stopAllProcesses is - begin - if C_SIM_VERBOSE then report "stopAllProcesses:" severity NOTE; end if; - for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop - stopProcesses(i); - end loop; - end procedure; - - procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is - begin - if (TestID >= TestCount) then - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - return; - end if; - - if C_SIM_VERBOSE then report "stopProcesses(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(Tests(TestID).Name) severity NOTE; end if; - MainProcessEnables(TestID) := FALSE; - stopClocks(TestID); - end procedure; - - procedure stopAllClocks is - begin - if C_SIM_VERBOSE then report "stopAllClocks:" severity NOTE; end if; - for i in C_SIM_DEFAULT_TEST_ID to TestCount - 1 loop - stopClocks(i); - end loop; - end procedure; - - procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is - begin - if (TestID >= TestCount) then - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - return; - end if; - - if C_SIM_VERBOSE then report "stopClocks(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(Tests(TestID).Name) severity NOTE; end if; - MainClockEnables(TestID) := FALSE; - end procedure; - - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is - begin - return not MainClockEnables(TestID); - end function; - - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is - begin - return (Tests(TestID).Status = SIM_TEST_STATUS_ENDED); - end function; - - impure function isAllFinalized return boolean is - begin - if (State.IsFinalized = TRUE) then - if ActiveTestCount = 0 then - return TRUE; - end if; - report "isAllFinalized: " severity ERROR; - return FALSE; - else - return FALSE; - end if; - end function; - end protected body; -end package body; diff --git a/src/sim/sim_random.v08.vhdl b/src/sim/sim_random.v08.vhdl deleted file mode 100644 index d3d8941dc..000000000 --- a/src/sim/sim_random.v08.vhdl +++ /dev/null @@ -1,264 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IEEE.math_real.all; - -use work.utils.all; --- use work.strings.all; -use work.vectors.all; --- use work.physical.all; -use work.sim_types.all; - - -package sim_random is - -- Random Numbers - -- =========================================================================== - alias T_SIM_SEED is T_SIM_RAND_SEED; - - -- procedural interface - -- procedure randomInitializeSeed(Seed : inout T_SIM_SEED); - - -- procedure randomUniformDistibutedValue(Seed : inout T_SIM_SEED; Value : out REAL; Minimum : in REAL; Maximum : in REAL); - - -- procedure randomNormalDistributedValue(Seed : inout T_SIM_SEED; Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0); - -- procedure randomNormalDistributedValue(Seed : inout T_SIM_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - - -- procedure randomPoissonDistributedValue(Seed : inout T_SIM_SEED; Value : out REAL; Mean : in REAL); - -- procedure randomPoissonDistributedValue(Seed : inout T_SIM_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - - -- protected type interface - type T_RANDOM is protected - procedure SetSeed; - procedure SetSeed(Seed1 : integer; Seed2 : integer); - procedure SetSeed(SeedValue : T_SIM_SEED); - procedure SetSeed(SeedVector : T_INTVEC); - procedure SetSeed(SeedVector : string); - impure function GetSeed return T_SIM_SEED; - - procedure GetUniformDistributedValue(Value : out REAL); - procedure GetUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer); - procedure GetUniformDistributedValue(Value : out REAL; Minimum : in REAL; Maximum : in REAL); - impure function GetUniformDistributedValue return REAL; - impure function GetUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer; - impure function GetUniformDistributedValue(Minimum : in REAL; Maximum : in REAL) return REAL; - - procedure GetNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0); - procedure GetNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); - procedure GetNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - impure function GetNormalDistributedValue(StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) return REAL; - impure function GetNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; - impure function GetNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; - - procedure GetPoissonDistributedValue(Value : out REAL; Mean : in REAL); - procedure GetPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); - procedure GetPoissonDistributedValue(Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - impure function GetPoissonDistributedValue(Mean : in REAL) return REAL; - impure function GetPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; - impure function GetPoissonDistributedValue(Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; - end protected; -end package; - - -package body sim_random is - type T_RANDOM is protected body - variable Local_Seed : T_SIM_SEED := randInitializeSeed; - - -- Seed value handling - procedure SetSeed is - begin - Local_Seed := randInitializeSeed; - end procedure; - - procedure SetSeed(Seed1 : integer; Seed2 : integer) is - begin - Local_Seed := randInitializeSeed(T_SIM_RAND_SEED'(Seed1, Seed2)); - end procedure; - - procedure SetSeed(SeedValue : T_SIM_SEED) is - begin - Local_Seed := randInitializeSeed(SeedValue); - end procedure; - - procedure SetSeed(SeedVector : T_INTVEC) is - begin - Local_Seed := randInitializeSeed(SeedVector); - end procedure; - - procedure SetSeed(SeedVector : string) is - begin - Local_Seed := randInitializeSeed(SeedVector); - end procedure; - - impure function GetSeed return T_SIM_SEED is - begin - return Local_Seed; - end function; - - -- Uniform distribution - impure function GetUniformDistributedValue return REAL is - variable Result : REAL; - begin - randUniformDistributedValue(Local_Seed, Result); - return Result; - end function; - - procedure getUniformDistributedValue(Value : out REAL) is - begin - randUniformDistributedValue(Local_Seed, Value); - end procedure; - - impure function GetUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer is - variable Result : integer; - begin - randUniformDistributedValue(Local_Seed, Result, Minimum, Maximum); - return Result; - end function; - - procedure getUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer) is - begin - randUniformDistributedValue(Local_Seed, Value, Minimum, Maximum); - end procedure; - - impure function GetUniformDistributedValue(Minimum : in REAL; Maximum : in REAL) return REAL is - variable Result : REAL; - begin - randUniformDistributedValue(Local_Seed, Result, Minimum, Maximum); - return Result; - end function; - - procedure getUniformDistributedValue(Value : out REAL; Minimum : in REAL; Maximum : in REAL) is - begin - randUniformDistributedValue(Local_Seed, Value, Minimum, Maximum); - end procedure; - - -- Normal distribution - impure function getNormalDistributedValue(StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) return REAL is - variable Result : REAL; - begin - randNormalDistributedValue(Local_Seed, Result, StandardDeviation, Mean); - return Result; - end function; - - procedure getNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is - begin - randNormalDistributedValue(Local_Seed, Value, StandardDeviation, Mean); - end procedure; - - impure function getNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is - variable Result : integer; - begin - randNormalDistributedValue(Local_Seed, Result, StandardDeviation, Mean, Minimum, Maximum); - return Result; - end function; - - procedure getNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is - begin - randNormalDistributedValue(Local_Seed, Value, StandardDeviation, Mean, Minimum, Maximum); - end procedure; - - impure function getNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL is - variable Result : REAL; - begin - randNormalDistributedValue(Local_Seed, Result, StandardDeviation, Mean, Minimum, Maximum); - return Result; - end function; - - procedure getNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - begin - randNormalDistributedValue(Local_Seed, Value, StandardDeviation, Mean, Minimum, Maximum); - end procedure; - - -- Poisson distribution - impure function getPoissonDistributedValue(Mean : in REAL) return REAL is - variable Result : REAL; - begin - randPoissonDistributedValue(Local_Seed, Result, Mean); - return Result; - end function; - - procedure getPoissonDistributedValue(Value : out REAL; Mean : in REAL) is - begin - randPoissonDistributedValue(Local_Seed, Value, Mean); - end procedure; - - impure function getPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is - variable Result : integer; - begin - randPoissonDistributedValue(Local_Seed, Result, Mean, Minimum, Maximum); - return Result; - end function; - - procedure getPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is - begin - randPoissonDistributedValue(Local_Seed, Value, Mean, Minimum, Maximum); - end procedure; - - impure function getPoissonDistributedValue(Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL is - variable Result : REAL; - begin - randPoissonDistributedValue(Local_Seed, Result, Mean, Minimum, Maximum); - return Result; - end function; - - procedure getPoissonDistributedValue(Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - begin - randPoissonDistributedValue(Local_Seed, Value, Mean, Minimum, Maximum); - end procedure; - end protected body; - - - -- procedure randomUniformDistibutedValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL) is - -- begin - -- randUniformDistibutedValue(Seed, Value, Minimum, Maximum); - -- end procedure ; - - -- procedure randomNormalDistibutedValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is - -- begin - -- randNormalDistibutedValue(Seed, Value, StandardDeviation, Mean); - -- end procedure; - - -- procedure randomNormalDistibutedValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - -- begin - -- randNormalDistibutedValue(Seed, Value, StandardDeviation, Mean, Minimum, Maximum); - -- end procedure; - - -- procedure randomPoissonDistibutedValue(Seed : inout T_SIM_SEED; Value : inout REAL; Mean : in REAL) is - -- begin - -- randPoissonDistibutedValue(Seed, Value, Mean); - -- end procedure; - - -- procedure randomPoissonDistibutedValue(Seed : inout T_SIM_SEED; Value : inout REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - -- begin - -- randPoissonDistibutedValue(Seed, Value, Mean, Minimum, Maximum); - -- end procedure; -end package body; diff --git a/src/sim/sim_random.v93.vhdl b/src/sim/sim_random.v93.vhdl deleted file mode 100644 index 0dce7aff9..000000000 --- a/src/sim/sim_random.v93.vhdl +++ /dev/null @@ -1,231 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IEEE.math_real.all; - -use work.utils.all; --- use work.strings.all; -use work.vectors.all; --- use work.physical.all; -use work.sim_types.all; - - -package sim_random is - -- Random Numbers - -- =========================================================================== - alias T_SIM_SEED is T_SIM_RAND_SEED; - - -- procedural interface - procedure randomInitializeSeed; - procedure randomInitializeSeed(Seed : T_SIM_SEED); - procedure randomInitializeSeed(Seed1 : integer; Seed2 : integer); - procedure randomInitializeSeed(SeedVector : T_INTVEC); - procedure randomInitializeSeed(SeedVector : string); - - -- Uniform distributed random values - -- =========================================================================== - procedure randomUniformDistributedValue(Value : out REAL); - procedure randomUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer); - procedure randomUniformDistributedValue(Value : out REAL; Minimum : in REAL; Maximum : in REAL); - - impure function randomUniformDistributedValue return REAL; - impure function randomUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer; - impure function randomUniformDistributedValue(Minimum : in REAL; Maximum : in REAL) return REAL; - - -- Normal / Gaussian distributed random values - -- =========================================================================== - procedure randomNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0); - procedure randomNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); - procedure randomNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - - impure function randomNormalDistributedValue(StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) return REAL; - impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; - impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; - - -- Poisson distributed random values - -- =========================================================================== - procedure randomPoissonDistributedValue(Value : out REAL; Mean : in REAL); - procedure randomPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); - procedure randomPoissonDistributedValue(Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - - impure function randomPoissonDistributedValue(Mean : in REAL) return REAL; - impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer; - impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL; -end package; - - -package body sim_random is - shared variable SeedValue : T_SIM_SEED := randInitializeSeed; - - procedure randomInitializeSeed is - begin - randInitializeSeed(SeedValue); - end procedure; - - procedure randomInitializeSeed(Seed : T_SIM_SEED) is - begin - randInitializeSeed(SeedValue, Seed); - end procedure; - - procedure randomInitializeSeed(Seed1 : integer; Seed2 : integer) is - begin - randInitializeSeed(SeedValue, T_SIM_RAND_SEED'(Seed1, Seed2)); - end procedure; - - procedure randomInitializeSeed(SeedVector : T_INTVEC) is - begin - randInitializeSeed(SeedValue, SeedVector); - end procedure; - - procedure randomInitializeSeed(SeedVector : string) is - begin - randInitializeSeed(SeedValue, SeedVector); - end procedure; - - -- =========================================================================== - -- Uniform distributed random values - -- =========================================================================== - procedure randomUniformDistributedValue(Value : out REAL) is - begin - randUniformDistributedValue(SeedValue, Value); - end procedure; - - procedure randomUniformDistributedValue(Value : out integer; Minimum : in integer; Maximum : in integer) is - begin - randUniformDistributedValue(SeedValue, Value, Minimum, Maximum); - end procedure; - - procedure randomUniformDistributedValue(Value : out REAL; Minimum : in REAL; Maximum : in REAL) is - begin - randUniformDistributedValue(SeedValue, Value, Minimum, Maximum); - end procedure; - - impure function randomUniformDistributedValue return REAL is - variable Result : REAL; - begin - randUniformDistributedValue(SeedValue, Result); - return Result; - end function; - - impure function randomUniformDistributedValue(Minimum : in integer; Maximum : in integer) return integer is - variable Result : integer; - begin - randUniformDistributedValue(SeedValue, Result, Minimum, Maximum); - return Result; - end function; - - impure function randomUniformDistributedValue(Minimum : in REAL; Maximum : in REAL) return REAL is - variable Result : REAL; - begin - randUniformDistributedValue(SeedValue, Result, Minimum, Maximum); - return Result; - end function; - - -- =========================================================================== - -- Normal / Gaussian distributed random values - -- =========================================================================== - procedure randomNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is - begin - randNormalDistributedValue(SeedValue, Value, StandardDeviation, Mean); - end procedure; - - procedure randomNormalDistributedValue(Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is - begin - randNormalDistributedValue(SeedValue, Value, StandardDeviation, Mean, Minimum, Maximum); - end procedure; - - procedure randomNormalDistributedValue(Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - begin - randNormalDistributedValue(SeedValue, Value, StandardDeviation, Mean, Minimum, Maximum); - end procedure; - - impure function randomNormalDistributedValue(StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) return REAL is - variable Result : REAL; - begin - randNormalDistributedValue(SeedValue, Result, StandardDeviation, Mean); - return Result; - end function; - - impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is - variable Result : integer; - begin - randNormalDistributedValue(SeedValue, Result, StandardDeviation, Mean, Minimum, Maximum); - return Result; - end function; - - impure function randomNormalDistributedValue(StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL is - variable Result : REAL; - begin - randNormalDistributedValue(SeedValue, Result, StandardDeviation, Mean, Minimum, Maximum); - return Result; - end function; - - -- =========================================================================== - -- Poisson distributed random values - -- =========================================================================== - procedure randomPoissonDistributedValue(Value : out REAL; Mean : in REAL) is - begin - randPoissonDistributedValue(SeedValue, Value, Mean); - end procedure; - - procedure randomPoissonDistributedValue(Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is - begin - randPoissonDistributedValue(SeedValue, Value, Mean, Minimum, Maximum); - end procedure; - - procedure randomPoissonDistributedValue(Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - begin - randPoissonDistributedValue(SeedValue, Value, Mean, Minimum, Maximum); - end procedure; - - impure function randomPoissonDistributedValue(Mean : in REAL) return REAL is - variable Result : REAL; - begin - randPoissonDistributedValue(SeedValue, Result, Mean); - return Result; - end function; - - impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in integer; Maximum : in integer) return integer is - variable Result : integer; - begin - randPoissonDistributedValue(SeedValue, Result, Mean, Minimum, Maximum); - return Result; - end function; - - impure function randomPoissonDistributedValue(Mean : in REAL; Minimum : in REAL; Maximum : in REAL) return REAL is - variable Result : REAL; - begin - randPoissonDistributedValue(SeedValue,Result, Mean, Minimum, Maximum); - return Result; - end function; -end package body; diff --git a/src/sim/sim_simulation.v08.vhdl b/src/sim/sim_simulation.v08.vhdl deleted file mode 100644 index d223c14ce..000000000 --- a/src/sim/sim_simulation.v08.vhdl +++ /dev/null @@ -1,172 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- Thomas B. Preusser --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IEEE.math_real.all; - -use work.utils.all; --- use work.strings.all; -use work.vectors.all; -use work.physical.all; - -use work.sim_global.all; -use work.sim_types.all; -use work.sim_protected.all; - - -package simulation is - -- Legacy interface for pre VHDL-2002 - -- =========================================================================== - -- prepared aliases, if GHDL gets the aliases fixed. Reported on 08.02.2015 as Issue #38 - -- alias simmInitialize is globalSimulationStatus.initialize[NATURAL, TIME]; - -- alias simmFinalize is globalSimulationStatus.finalize[]; - - -- alias simmCreateTest is globalSimulationStatus.createTest[STRING return T_SIM_TEST_ID]; - -- alias simmFinalizeTest is globalSimulationStatus.finalizeTest[T_SIM_TEST_ID]; - -- alias simmRegisterProcess is globalSimulationStatus.registerProcess[T_SIM_TEST_ID, STRING, BOOLEAN return T_SIM_PROCESS_ID]; - -- alias simmRegisterProcess is globalSimulationStatus.registerProcess[STRING, BOOLEAN return T_SIM_PROCESS_ID]; - -- alias simmDeactivateProcess is globalSimulationStatus.deactivateProcess[T_SIM_PROCESS_ID]; - - -- alias simmIsStopped is globalSimulationStatus.isStopped[T_SIM_TEST_ID return BOOLEAN]; - -- alias simmIsFinalized is globalSimulationStatus.isFinalized[T_SIM_TEST_ID return BOOLEAN]; - -- alias simmIsAllFinalized is globalSimulationStatus.isAllFinalized [return BOOLEAN]; - - -- alias simmAssertion is globalSimulationStatus.assertion[BOOLEAN, STRING]; - -- alias simmFail is globalSimulationStatus.fail[STRING]; - -- alias simmWriteMessage is globalSimulationStatus.writeMessage[STRING]; - - procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); - procedure simFinalize; - - impure function simCreateTest(Name : string) return T_SIM_TEST_ID; - procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID); - impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; - impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; - procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID); - - impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; - impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; - impure function simIsAllFinalized return boolean; - - procedure simAssertion(cond : in boolean; Message : in string := ""); - procedure simFail(Message : in string := ""); - procedure simWriteMessage(Message : in string := ""); - - -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here - - -- checksum functions - -- =========================================================================== - -- TODO: move checksum functions here -end package; - - -package body simulation is - -- legacy procedures - -- =========================================================================== - -- TODO: undocumented group - procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is - begin - globalSimulationStatus.initialize(MaxAssertFailures, MaxSimulationRuntime); - if C_SIM_VERBOSE then report "simInitialize:" severity NOTE; end if; - if (MaxSimulationRuntime /= time'high) then - wait for MaxSimulationRuntime; - report "simInitialize: TIMEOUT" severity ERROR; - globalSimulationStatus.finalize; - end if; - end procedure; - - procedure simFinalize is - begin - globalSimulationStatus.finalize; - end procedure; - - impure function simCreateTest(Name : string) return T_SIM_TEST_ID is - begin - return globalSimulationStatus.createTest(Name); - end function; - - procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID) is - begin - globalSimulationStatus.finalizeTest(TestID); - end procedure; - - impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is - begin - return globalSimulationStatus.registerProcess(Name, IsLowPriority); - end function; - - impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is - begin - return globalSimulationStatus.registerProcess(TestID, Name, IsLowPriority); - end function; - - procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is - begin - globalSimulationStatus.deactivateProcess(ProcID); - end procedure; - - impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is - begin - return globalSimulationStatus.isStopped(TestID); - end function; - - impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is - begin - return globalSimulationStatus.isFinalized(TestID); - end function; - - impure function simIsAllFinalized return boolean is - begin - return globalSimulationStatus.isAllFinalized; - end function; - - -- TODO: undocumented group - procedure simWriteMessage(Message : in string := "") is - begin - globalSimulationStatus.writeMessage(Message); - end procedure; - - procedure simFail(Message : in string := "") is - begin - globalSimulationStatus.fail(Message); - end procedure; - - procedure simAssertion(cond : in boolean; Message : in string := "") is - begin - globalSimulationStatus.assertion(cond, Message); - end procedure; - - -- checksum functions - -- =========================================================================== - -- TODO: move checksum functions here -end package body; diff --git a/src/sim/sim_simulation.v93.vhdl b/src/sim/sim_simulation.v93.vhdl deleted file mode 100644 index ffa03b397..000000000 --- a/src/sim/sim_simulation.v93.vhdl +++ /dev/null @@ -1,88 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- Thomas B. Preusser --- Martin Zabel --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.sim_types.all; -use work.sim_unprotected.all; - - -package simulation is - -- mimic definition of VHDL-2008 - type TIME_VECTOR is array(natural range<>) of time; - - -- Testbench Status Management - -- =========================================================================== - -- alias simInitialize is work.sim_unprotected.initialize[NATURAL, TIME]; - procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); - alias simFinalize is work.sim_unprotected.finalize[]; - - alias simCreateTest is work.sim_unprotected.createTest[string return T_SIM_TEST_ID]; - alias simFinalizeTest is work.sim_unprotected.finalizeTest[T_SIM_TEST_ID]; - alias simRegisterProcess is work.sim_unprotected.registerProcess[T_SIM_TEST_ID, string, boolean return T_SIM_PROCESS_ID]; - alias simRegisterProcess is work.sim_unprotected.registerProcess[string, boolean return T_SIM_PROCESS_ID]; - alias simDeactivateProcess is work.sim_unprotected.deactivateProcess[T_SIM_PROCESS_ID]; - - procedure simStopAllClocks; - --alias simStopAllClocks is work.sim_unprotected.stopAllClocks[]; - alias simIsStopped is work.sim_unprotected.isStopped[T_SIM_TEST_ID return boolean]; - alias simIsFinalized is work.sim_unprotected.isFinalized[T_SIM_TEST_ID return boolean]; - alias simIsAllFinalized is work.sim_unprotected.isAllFinalized [return boolean]; - - alias simAssertion is work.sim_unprotected.assertion[boolean, string]; - alias simFail is work.sim_unprotected.fail[string]; - alias simWriteMessage is work.sim_unprotected.writeMessage[string]; - - -- checksum functions - -- =========================================================================== - -- TODO: move checksum functions here -end package; - -package body simulation is - procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is - begin - work.sim_unprotected.initialize(MaxAssertFailures, MaxSimulationRuntime); - if C_SIM_VERBOSE then report "simInitialize:" severity NOTE; end if; - if (MaxSimulationRuntime /= time'high) then - wait for MaxSimulationRuntime; - report "simInitialize: TIMEOUT" severity ERROR; - work.sim_unprotected.finalize; - end if; - end procedure; - - procedure simStopAllClocks is - begin - work.sim_unprotected.stopAllClocks; - end procedure; -end package body; diff --git a/src/sim/sim_types.vhdl b/src/sim/sim_types.vhdl deleted file mode 100644 index 9266b19f3..000000000 --- a/src/sim/sim_types.vhdl +++ /dev/null @@ -1,375 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- Thomas B. Preusser --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IEEE.math_real.all; - -use work.utils.all; --- use work.strings.all; -use work.vectors.all; --- use work.physical.all; - - -package sim_types is - - constant C_SIM_VERBOSE : boolean := FALSE; -- POC_VERBOSE - - -- =========================================================================== - -- Simulation Task and Status Management - -- =========================================================================== - type T_SIM_BOOLVEC is array(integer range <>) of boolean; - - subtype T_SIM_TEST_ID is integer range -1 to 1023; - subtype T_SIM_TEST_NAME is string(1 to 256); - subtype T_SIM_PROCESS_ID is natural range 0 to 1023; - subtype T_SIM_PROCESS_NAME is string(1 to 64); - subtype T_SIM_PROCESS_INSTNAME is string(1 to 256); - type T_SIM_PROCESS_ID_VECTOR is array(natural range <>) of T_SIM_PROCESS_ID; - - type T_SIM_TEST_STATUS is ( - SIM_TEST_STATUS_CREATED, - SIM_TEST_STATUS_ACTIVE, - SIM_TEST_STATUS_ENDED, - SIM_TEST_STATUS_ZOMBI - ); - - type T_SIM_PROCESS_STATUS is ( - SIM_PROCESS_STATUS_ACTIVE, - SIM_PROCESS_STATUS_ENDED - ); - - type T_SIM_TEST is record - ID : T_SIM_TEST_ID; - Name : T_SIM_TEST_NAME; - Status : T_SIM_TEST_STATUS; - ProcessIDs : T_SIM_PROCESS_ID_VECTOR(T_SIM_PROCESS_ID); - ProcessCount : T_SIM_PROCESS_ID; - ActiveProcessCount : T_SIM_PROCESS_ID; - end record; - type T_SIM_TEST_VECTOR is array(integer range <>) of T_SIM_TEST; - - type T_SIM_PROCESS is record - ID : T_SIM_PROCESS_ID; - TestID : T_SIM_TEST_ID; - Name : T_SIM_PROCESS_NAME; - Status : T_SIM_PROCESS_STATUS; - IsLowPriority : boolean; - end record; - type T_SIM_PROCESS_VECTOR is array(natural range <>) of T_SIM_PROCESS; - - constant C_SIM_DEFAULT_TEST_ID : T_SIM_TEST_ID := -1; - constant C_SIM_DEFAULT_TEST_NAME : string := "Default test"; - - -- =========================================================================== - -- Random Numbers - -- =========================================================================== - type T_SIM_RAND_SEED is record - Seed1 : integer; - Seed2 : integer; - end record; - - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED); - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED); - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC); - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string); - function randInitializeSeed return T_SIM_RAND_SEED; - function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED; - function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED; - function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED; - - - -- Uniform distributed random values - -- =========================================================================== - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL); - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer); - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL); - - -- Normal / Gaussian distributed random values - -- =========================================================================== - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0); - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer); - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - - -- Poisson distributed random values - -- =========================================================================== - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL); - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer); - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL); - - -- =========================================================================== - -- Clock Generation - -- =========================================================================== - -- type T_PERCENT is INTEGER'range units - type T_PERCENT is range integer'low to INTEGER'high units - ppb; - ppm = 1000 ppb; - permil = 1000 ppm; - percent = 10 permil; - one = 100 percent; - end units; - subtype T_WANDER is T_PERCENT range -1 one to 1 one; - subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one; - - type T_DEGREE is range integer'low to INTEGER'high units - second; - minute = 60 second; - deg = 60 minute; - end units; - subtype T_PHASE is T_DEGREE range -360 deg to 360 deg; - - function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE; -end package; - - -package body sim_types is - function ite(cond : boolean; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is - begin - if cond then - return value1; - else - return value2; - end if; - end function; - - -- =========================================================================== - -- Random Numbers - -- =========================================================================== - constant MAX_SEED1_VALUE : positive := 2147483562; - constant MAX_SEED2_VALUE : positive := 2147483398; - - function randGenerateInitialSeed return T_SIM_RAND_SEED is - begin - return ( - Seed1 => 5, - Seed2 => 3423 - ); - end function; - - function randBoundSeed(SeedValue : in T_SIM_RAND_SEED) return T_SIM_RAND_SEED is - begin - return ( - Seed1 => (SeedValue.Seed1 - 1 mod MAX_SEED1_VALUE) + 1, - Seed2 => (SeedValue.Seed2 - 1 mod MAX_SEED2_VALUE) + 1 - ); - end function; - - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED) is - begin - Seed := randGenerateInitialSeed; - end procedure; - - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedValue : in T_SIM_RAND_SEED) is - begin - Seed := randBoundSeed(SeedValue); - end procedure; - - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in T_INTVEC) is - begin - if (SeedVector'length = 0) then - Seed := randGenerateInitialSeed; - elsif (SeedVector'length = 1) then - Seed := randBoundSeed(T_SIM_RAND_SEED'( - Seed1 => SeedVector(0), - Seed2 => 92346 - )); - elsif (SeedVector'length = 2) then - Seed := randBoundSeed(T_SIM_RAND_SEED'( - Seed1 => SeedVector(0), - Seed2 => SeedVector(1) - )); - else - -- FIXME: - -- Seed.Seed1 := SeedVector(0); - -- Seed.Seed2 := SeedVector(1); - end if; - end procedure; - - procedure randInitializeSeed(Seed : inout T_SIM_RAND_SEED; SeedVector : in string) is - begin - if (SeedVector'length = 0) then - Seed := randGenerateInitialSeed; - elsif (SeedVector'length = 1) then - Seed := T_SIM_RAND_SEED'( - Seed1 => character'pos(SeedVector(1)), - Seed2 => 39834 - ); - elsif (SeedVector'length = 2) then - Seed := T_SIM_RAND_SEED'( - Seed1 => character'pos(SeedVector(1)), - Seed2 => character'pos(SeedVector(2)) - ); - else - -- FIXME: - -- Seed.Seed1 := CHARACTER'pos(SeedVector(0)); - -- Seed.Seed2 := CHARACTER'pos(SeedVector(1)); - end if; - end procedure; - - function randInitializeSeed return T_SIM_RAND_SEED is - begin - return randGenerateInitialSeed; - end function; - - function randInitializeSeed(SeedValue : T_SIM_RAND_SEED) return T_SIM_RAND_SEED is - begin - return randBoundSeed(SeedValue); - end function; - - function randInitializeSeed(SeedVector : T_INTVEC) return T_SIM_RAND_SEED is - variable Result : T_SIM_RAND_SEED; - begin - randInitializeSeed(Result, SeedVector); - return Result; - end function; - - function randInitializeSeed(SeedVector : string) return T_SIM_RAND_SEED is - variable Result : T_SIM_RAND_SEED; - begin - randInitializeSeed(Result, SeedVector); - return Result; - end function; - - -- =========================================================================== - -- Uniform distributed random values - -- =========================================================================== - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL) is - begin - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, Value); - end procedure; - - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Minimum : integer; Maximum : integer) is - variable rand : REAL; - begin - if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); - Value := scale(rand, Minimum, Maximum); - end procedure; - - procedure randUniformDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Minimum : REAL; Maximum : REAL) is - variable rand : REAL; - begin - if Maximum < Minimum then report "randUniformDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); - Value := scale(rand, Minimum, Maximum); - end procedure; - - -- =========================================================================== - -- Normal / Gaussian distributed random values - -- =========================================================================== - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : REAL := 1.0; Mean : REAL := 0.0) is - variable rand1 : REAL; - variable rand2 : REAL; - begin - if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; - -- Box Muller transformation - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1); - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2); - -- standard normal distribution: mean 0, variance 1 - Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean; - end procedure; - - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; StandardDeviation : in REAL; Mean : in REAL; Minimum : in integer; Maximum : in integer) is - variable rand_real : REAL; - variable rand_int : integer; - begin - if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; - while TRUE loop - randNormalDistributedValue(Seed, rand_real, StandardDeviation, Mean); - rand_int := integer(round(rand_real)); - exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); - end loop; - Value := rand_int; - end procedure; - - procedure randNormalDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - variable rand : REAL; - begin - if Maximum < Minimum then report "randNormalDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - if StandardDeviation < 0.0 then report "randNormalDistributedValue: Standard deviation must be >= 0.0" severity FAILURE; end if; - while TRUE loop - randNormalDistributedValue(Seed, rand, StandardDeviation, Mean); - exit when ((Minimum <= rand) and (rand <= Maximum)); - end loop; - Value := rand; - end procedure; - - -- =========================================================================== - -- Poisson distributed random values - -- =========================================================================== - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL) is - variable Product : Real; - variable Bound : Real; - variable rand : Real; - variable Result : Real; - begin - Product := 1.0; - Result := 0.0; - Bound := exp(-1.0 * Mean); - if ((Mean <= 0.0) or (Bound <= 0.0)) then - report "randPoissonDistributedValue: Mean must be greater than 0.0." severity FAILURE; - return; - end if; - - while (Product >= Bound) loop - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); - Product := Product * rand; - Result := Result + 1.0; - end loop; - Value := Result; - end procedure; - - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out integer; Mean : in REAL; Minimum : in integer; Maximum : in integer) is - variable rand_real : REAL; - variable rand_int : integer; - begin - if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - while TRUE loop - randPoissonDistributedValue(Seed, rand_real, Mean); - rand_int := integer(round(rand_real)); - exit when ((Minimum <= rand_int) and (rand_int <= Maximum)); - end loop; - Value := rand_int; - end procedure; - - procedure randPoissonDistributedValue(Seed : inout T_SIM_RAND_SEED; Value : out REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is - variable rand : REAL; - begin - if Maximum < Minimum then report "randPoissonDistributedValue: Maximum must be greater than Minimum." severity FAILURE; end if; - while TRUE loop - randPoissonDistributedValue(Seed, rand, Mean); - exit when ((Minimum <= rand) and (rand <= Maximum)); - end loop; - Value := rand; - end procedure; -end package body; diff --git a/src/sim/sim_unprotected.v93.vhdl b/src/sim/sim_unprotected.v93.vhdl deleted file mode 100644 index 45cea2d08..000000000 --- a/src/sim/sim_unprotected.v93.vhdl +++ /dev/null @@ -1,433 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use STD.TextIO.all; - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -use work.utils.all; -use work.strings.all; -use work.vectors.all; -use work.physical.all; - -use work.sim_types.all; -use work.sim_global.all; - - -package sim_unprotected is - -- Simulation Task and Status Management - -- =========================================================================== - -- Initializer and Finalizer - procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); - procedure finalize; - - -- Assertions - procedure fail(Message : string := ""); - procedure assertion(Condition : boolean; Message : string := ""); - procedure writeMessage(Message : string); - procedure writeReport; - - -- Process Management - impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; - procedure deactivateProcess(procID : T_SIM_PROCESS_ID); - procedure stopAllProcesses; - procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); - - -- Test Management - procedure createDefaultTest; - impure function createTest(Name : string) return T_SIM_TEST_ID; - procedure activateDefaultTest; - impure function finalizeDefaultTest return boolean; - procedure finalizeTest(TestID : T_SIM_TEST_ID); - - -- Clock Management - procedure stopAllClocks; - procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID); - - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; - impure function isAllFinalized return boolean; -end package; - - -package body sim_unprotected is - - -- Simulation process and Status Management - -- =========================================================================== - procedure init is - begin - if not globalSim_StateIsInitialized then - if C_SIM_VERBOSE then report "init:" severity NOTE; end if; - globalSim_StateIsInitialized := TRUE; - createDefaultTest; - end if; - end procedure; - - procedure initialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is - begin - if C_SIM_VERBOSE then report "initialize:" severity NOTE; end if; - init; - globalSim_MaxAssertFailures := MaxAssertFailures; - globalSim_MaxSimulationRuntime := MaxSimulationRuntime; - -- if (MaxSimulationRuntime /= TIME'high) then - -- wait until (globalSim_StateIsFinalized = TRUE) for MaxSimulationRuntime; - -- report "initialize: TIMEOUT" severity ERROR; - -- finalize; - -- end if; - end procedure; - - procedure finalize is - variable Dummy : boolean; - begin - if not globalSim_StateIsFinalized then - if C_SIM_VERBOSE then report "finalize: " severity NOTE; end if; - globalSim_StateIsFinalized := TRUE; - for i in 0 to globalSim_TestCount - 1 loop - finalizeTest(i); - end loop; - Dummy := finalizeDefaultTest; - writeReport; - end if; - end procedure; - - procedure writeReport_Header is - variable LineBuffer : LINE; - begin - write(LineBuffer, ( string'("========================================"))); - write(LineBuffer, (LF & string'("POC TESTBENCH REPORT"))); - write(LineBuffer, (LF & string'("========================================"))); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_TestReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - if (globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status /= SIM_TEST_STATUS_CREATED) then - write(LineBuffer, Prefix & "Tests " & integer'image(globalSim_TestCount + 1)); - write(LineBuffer, LF & Prefix & " " & str_ralign("-1", log10ceilnz(globalSim_TestCount + 1) + 1) & ": " & C_SIM_DEFAULT_TEST_NAME); - else - write(LineBuffer, Prefix & "Tests " & integer'image(globalSim_TestCount)); - end if; - for i in 0 to globalSim_TestCount - 1 loop - write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(globalSim_TestCount)) & ": " & str_trim(globalSim_Tests(i).Name)); - end loop; - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_AssertReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - write(LineBuffer, Prefix & "Assertions " & integer'image(globalSim_AssertCount)); - write(LineBuffer, LF & Prefix & " failed " & integer'image(globalSim_FailedAssertCount) & ite((globalSim_FailedAssertCount >= globalSim_MaxAssertFailures), " Too many failed asserts!", "")); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_ProcessReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - write(LineBuffer, Prefix & "Processes " & integer'image(globalSim_ProcessCount)); - write(LineBuffer, LF & Prefix & " active " & integer'image(globalSim_ActiveProcessCount)); - -- report killed processes - for i in 0 to globalSim_ProcessCount - 1 loop - if ((globalSim_Processes(i).Status = SIM_PROCESS_STATUS_ACTIVE) and (globalSim_Processes(i).IsLowPriority = FALSE)) then - write(LineBuffer, LF & Prefix & " " & str_ralign(integer'image(i), log10ceilnz(globalSim_ProcessCount)) & ": " & str_trim(globalSim_Processes(i).Name)); - end if; - end loop; - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_RuntimeReport(Prefix : string := "") is - variable LineBuffer : LINE; - begin - write(LineBuffer, Prefix & "Runtime " & to_string(now, 1)); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport_SimulationResult is - variable LineBuffer : LINE; - begin - write(LineBuffer, ( string'("========================================"))); - if globalSim_AssertCount = 0 then write(LineBuffer, (LF & string'("SIMULATION RESULT = NO ASSERTS"))); - elsif globalSim_Passed then write(LineBuffer, (LF & string'("SIMULATION RESULT = PASSED"))); - else write(LineBuffer, (LF & string'("SIMULATION RESULT = FAILED"))); - end if; - write(LineBuffer, (LF & string'("========================================"))); - writeline(output, LineBuffer); - end procedure; - - procedure writeReport is - variable LineBuffer : LINE; - begin - writeReport_Header; - writeReport_TestReport(""); - write(LineBuffer, LF & "Overall"); - writeline(output, LineBuffer); - writeReport_AssertReport(" "); - writeReport_ProcessReport(" "); - writeReport_RuntimeReport(" "); - writeReport_SimulationResult; - end procedure; - - procedure assertion(condition : boolean; Message : string := "") is - begin - globalSim_AssertCount := globalSim_AssertCount + 1; - if not condition then - fail(Message); - globalSim_FailedAssertCount := globalSim_FailedAssertCount + 1; - if (globalSim_FailedAssertCount >= globalSim_MaxAssertFailures) then - stopAllProcesses; - end if; - end if; - end procedure; - - procedure fail(Message : string := "") is - begin - if (Message'length > 0) then - report Message severity ERROR; - end if; - globalSim_Passed := FALSE; - end procedure; - - procedure writeMessage(Message : string) is - variable LineBuffer : LINE; - begin - write(LineBuffer, Message); - writeline(output, LineBuffer); - end procedure; - - procedure createDefaultTest is - variable Test : T_SIM_TEST; - begin - if not globalSim_StateIsInitialized then - init; - end if; - if C_SIM_VERBOSE then report "createDefaultTest(" & C_SIM_DEFAULT_TEST_NAME & "): => " & T_SIM_TEST_ID'image(C_SIM_DEFAULT_TEST_ID) severity NOTE; end if; - Test.ID := C_SIM_DEFAULT_TEST_ID; - Test.Name := resize(C_SIM_DEFAULT_TEST_NAME, T_SIM_TEST_NAME'length); - Test.Status := SIM_TEST_STATUS_CREATED; - Test.ProcessIDs := (others => 0); - Test.ProcessCount := 0; - Test.ActiveProcessCount := 0; - -- add to the internal structure - globalSim_Tests(Test.ID) := Test; - end procedure; - - impure function createTest(Name : string) return T_SIM_TEST_ID is - variable Test : T_SIM_TEST; - begin - if not globalSim_StateIsInitialized then - init; - end if; - if C_SIM_VERBOSE then report "createTest(" & Name & "): => " & T_SIM_TEST_ID'image(globalSim_TestCount) severity NOTE; end if; - Test.ID := globalSim_TestCount; - Test.Name := resize(Name, T_SIM_TEST_NAME'length); - Test.Status := SIM_TEST_STATUS_ACTIVE; - Test.ProcessIDs := (others => 0); - Test.ProcessCount := 0; - Test.ActiveProcessCount := 0; - -- add to the internal structure - globalSim_Tests(Test.ID) := Test; - globalSim_TestCount := globalSim_TestCount + 1; - globalSim_ActiveTestCount := globalSim_ActiveTestCount + 1; - -- return TestID for finalizeTest - return Test.ID; - end function; - - procedure activateDefaultTest is - begin - if (globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then - globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ACTIVE; - globalSim_ActiveTestCount := globalSim_ActiveTestCount + 1; - end if; - end procedure; - - impure function finalizeDefaultTest return boolean is - begin - if (globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_CREATED) then - if C_SIM_VERBOSE then report "finalizeDefaultTest: inactive" severity NOTE; end if; - globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; - stopProcesses(C_SIM_DEFAULT_TEST_ID); - return TRUE; - elsif (globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status = SIM_TEST_STATUS_ACTIVE) then - if C_SIM_VERBOSE then report "finalizeDefaultTest: active" severity NOTE; end if; - globalSim_Tests(C_SIM_DEFAULT_TEST_ID).Status := SIM_TEST_STATUS_ENDED; - globalSim_ActiveTestCount := globalSim_ActiveTestCount - 1; - stopProcesses(C_SIM_DEFAULT_TEST_ID); - if globalSim_ActiveTestCount = 0 then - finalize; - end if; - return TRUE; - end if; - return FALSE; - end function; - - procedure finalizeTest(TestID : T_SIM_TEST_ID) is - variable Dummy : boolean; - begin - if TestID = C_SIM_DEFAULT_TEST_ID then - if globalSim_ActiveTestCount = 1 then - if finalizeDefaultTest then - finalize; - end if; - end if; - elsif TestID < globalSim_TestCount then - if (globalSim_Tests(TestID).Status /= SIM_TEST_STATUS_ENDED) then - if C_SIM_VERBOSE then report "finalizeTest(TestID=" & T_SIM_TEST_ID'image(TestID) & "): " severity NOTE; end if; - globalSim_Tests(TestID).Status := SIM_TEST_STATUS_ENDED; - globalSim_ActiveTestCount := globalSim_ActiveTestCount - 1; - stopProcesses(TestID); - - if globalSim_ActiveTestCount = 0 then - finalize; - elsif globalSim_ActiveTestCount = 1 then - if finalizeDefaultTest then - finalize; - end if; - end if; - end if; - else - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - end if; - end procedure; - - impure function registerProcess(Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is - begin - return registerProcess(C_SIM_DEFAULT_TEST_ID, Name, IsLowPriority); - end function; - - impure function registerProcess(TestID : T_SIM_TEST_ID; Name : string; IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is - variable Proc : T_SIM_PROCESS; - variable TestProcID : T_SIM_TEST_ID; - begin - if not globalSim_StateIsInitialized then - init; - end if; - if TestID = C_SIM_DEFAULT_TEST_ID then - activateDefaultTest; - end if; - if TestID < globalSim_TestCount then - if C_SIM_VERBOSE then report "registerProcess(TestID=" & T_SIM_TEST_ID'image(TestID) & ", " & Name & "): => " & T_SIM_PROCESS_ID'image(globalSim_ProcessCount) severity NOTE; end if; - Proc.ID := globalSim_ProcessCount; - Proc.TestID := TestID; - Proc.Name := resize(Name, T_SIM_PROCESS_NAME'length); - Proc.Status := SIM_PROCESS_STATUS_ACTIVE; - Proc.IsLowPriority := IsLowPriority; - - -- add process to list - globalSim_Processes(Proc.ID) := Proc; - globalSim_ProcessCount := globalSim_ProcessCount + 1; - globalSim_ActiveProcessCount := inc_if(not IsLowPriority, globalSim_ActiveProcessCount); - -- add process to test - TestProcID := globalSim_Tests(TestID).ProcessCount; - globalSim_Tests(TestID).ProcessIDs(TestProcID) := Proc.ID; - globalSim_Tests(TestID).ProcessCount := TestProcID + 1; - globalSim_Tests(TestID).ActiveProcessCount := inc_if(not IsLowPriority, globalSim_Tests(TestID).ActiveProcessCount); - -- return the process ID - return Proc.ID; - else - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - return T_SIM_PROCESS_ID'high; - end if; - end function; - - procedure deactivateProcess(ProcID : T_SIM_PROCESS_ID) is - variable TestID : T_SIM_TEST_ID; - begin - if ProcID < globalSim_ProcessCount then - TestID := globalSim_Processes(ProcID).TestID; - -- deactivate process - if (globalSim_Processes(ProcID).Status = SIM_PROCESS_STATUS_ACTIVE) then - if C_SIM_VERBOSE then report "deactivateProcess(ProcID=" & T_SIM_PROCESS_ID'image(ProcID) & "): TestID=" & T_SIM_TEST_ID'image(TestID) & " Name=" & str_trim(globalSim_Processes(ProcID).Name) severity NOTE; end if; - globalSim_Processes(ProcID).Status := SIM_PROCESS_STATUS_ENDED; - globalSim_ActiveProcessCount := dec_if(not globalSim_Processes(ProcID).IsLowPriority, globalSim_ActiveProcessCount); - globalSim_Tests(TestID).ActiveProcessCount := dec_if(not globalSim_Processes(ProcID).IsLowPriority, globalSim_Tests(TestID).ActiveProcessCount); - if (globalSim_Tests(TestID).ActiveProcessCount = 0) then - finalizeTest(TestID); - end if; - end if; - else - report "ProcID (" & T_SIM_PROCESS_ID'image(ProcID) & ") is unknown." severity FAILURE; - end if; - end procedure; - - procedure stopAllProcesses is - begin - if C_SIM_VERBOSE then report "stopAllProcesses:" severity NOTE; end if; - for i in C_SIM_DEFAULT_TEST_ID to globalSim_TestCount - 1 loop - stopProcesses(i); - end loop; - end procedure; - - procedure stopProcesses(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is - begin - if TestID < globalSim_TestCount then - if C_SIM_VERBOSE then report "stopProcesses(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(globalSim_Tests(TestID).Name) severity NOTE; end if; - globalSim_MainProcessEnables(TestID) := FALSE; - stopClocks(TestID); - else - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - end if; - end procedure; - - procedure stopAllClocks is - begin - if C_SIM_VERBOSE then report "stopAllClocks:" severity NOTE; end if; - for i in C_SIM_DEFAULT_TEST_ID to globalSim_TestCount - 1 loop - stopClocks(i); - end loop; - end procedure; - - procedure stopClocks(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) is - begin - if TestID < globalSim_TestCount then - if C_SIM_VERBOSE then report "stopClocks(TestID=" & T_SIM_TEST_ID'image(TestID) & "): Name=" & str_trim(globalSim_Tests(TestID).Name) severity NOTE; end if; - globalSim_MainClockEnables(TestID) := FALSE; - else - report "TestID (" & T_SIM_TEST_ID'image(TestID) & ") is unknown." severity FAILURE; - end if; - end procedure; - - impure function isStopped(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is - begin - return not globalSim_MainClockEnables(TestID); - end function; - - impure function isFinalized(TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is - begin - return (globalSim_Tests(TestID).Status = SIM_TEST_STATUS_ENDED); - end function; - - impure function isAllFinalized return boolean is - begin - return (globalSim_ActiveTestCount = 0); - end function; -end package body; diff --git a/src/sim/sim_waveform.vhdl b/src/sim/sim_waveform.vhdl deleted file mode 100644 index 4bc3dcbee..000000000 --- a/src/sim/sim_waveform.vhdl +++ /dev/null @@ -1,980 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- Martin Zabel --- --- Package: Simulation constants, functions and utilities. --- --- Description: --- ------------------------------------- --- .. TODO:: No documentation available. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IEEE.math_real.all; - -use work.utils.all; --- use work.strings.all; -use work.vectors.all; -use work.physical.all; - -use work.sim_types.all; --- use work.sim_random.all; -use work.simulation.all; - - -package waveform is - -- clock generation - -- =========================================================================== - procedure simGenerateClock( - signal Clock : out std_logic; - constant Frequency : in FREQ; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ); - procedure simGenerateClock( - constant TestID : in T_SIM_TEST_ID; - signal Clock : out std_logic; - constant Frequency : in FREQ; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ); - procedure simGenerateClock( - signal Clock : out std_logic; - constant Period : in time; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ); - procedure simGenerateClock( - constant TestID : in T_SIM_TEST_ID; - signal Clock : out std_logic; - constant Period : in time; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ); - - procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive); - procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive); - procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive); - procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive); - - procedure simGenerateClock2(constant TestID : in T_SIM_TEST_ID; signal Clock : out std_logic; signal Debug : out REAL; constant Period : in time); - - -- waveform description - -- =========================================================================== - type T_SIM_WAVEFORM_TUPLE_SL is record - Delay : time; - Value : std_logic; - end record; - - type T_SIM_WAVEFORM_TUPLE_SLV_8 is record - Delay : time; - Value : T_SLV_8; - end record; - - type T_SIM_WAVEFORM_TUPLE_SLV_16 is record - Delay : time; - Value : T_SLV_16; - end record; - - type T_SIM_WAVEFORM_TUPLE_SLV_24 is record - Delay : time; - Value : T_SLV_24; - end record; - - type T_SIM_WAVEFORM_TUPLE_SLV_32 is record - Delay : time; - Value : T_SLV_32; - end record; - - type T_SIM_WAVEFORM_TUPLE_SLV_48 is record - Delay : time; - Value : T_SLV_48; - end record; - - type T_SIM_WAVEFORM_TUPLE_SLV_64 is record - Delay : time; - Value : T_SLV_64; - end record; - - subtype T_SIM_WAVEFORM is TIME_VECTOR; -- use predefined physical type TIME here - type T_SIM_WAVEFORM_SL is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SL; - type T_SIM_WAVEFORM_SLV_8 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8; - type T_SIM_WAVEFORM_SLV_16 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16; - type T_SIM_WAVEFORM_SLV_24 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24; - type T_SIM_WAVEFORM_SLV_32 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32; - type T_SIM_WAVEFORM_SLV_48 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48; - type T_SIM_WAVEFORM_SLV_64 is array(natural range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64; - - -- waveform generation procedures - -- =========================================================================== - -- TODO: get initial value from Waveform(0) if .Delay = o fs, otherwise use (others => 'U') ? - procedure simGenerateWaveform( - signal Wave : out boolean; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in boolean := FALSE - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out boolean; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in boolean := FALSE - ); - procedure simGenerateWaveform( - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in std_logic := '0' - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in std_logic := '0' - ); - procedure simGenerateWaveform( - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in std_logic := '0' - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in std_logic := '0' - ); - procedure simGenerateWaveform( - signal Wave : out T_SLV_8; - constant Waveform : in T_SIM_WAVEFORM_SLV_8; - constant InitialValue : in T_SLV_8 := (others => '0') - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_8; - constant Waveform : in T_SIM_WAVEFORM_SLV_8; - constant InitialValue : in T_SLV_8 := (others => '0') - ); - procedure simGenerateWaveform( - signal Wave : out T_SLV_16; - constant Waveform : in T_SIM_WAVEFORM_SLV_16; - constant InitialValue : in T_SLV_16 := (others => '0') - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_16; - constant Waveform : in T_SIM_WAVEFORM_SLV_16; - constant InitialValue : in T_SLV_16 := (others => '0') - ); - procedure simGenerateWaveform( - signal Wave : out T_SLV_24; - constant Waveform : in T_SIM_WAVEFORM_SLV_24; - constant InitialValue : in T_SLV_24 := (others => '0') - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_24; - constant Waveform : in T_SIM_WAVEFORM_SLV_24; - constant InitialValue : in T_SLV_24 := (others => '0') - ); - procedure simGenerateWaveform( - signal Wave : out T_SLV_32; - constant Waveform : in T_SIM_WAVEFORM_SLV_32; - constant InitialValue : in T_SLV_32 := (others => '0') - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_32; - constant Waveform : in T_SIM_WAVEFORM_SLV_32; - constant InitialValue : in T_SLV_32 := (others => '0') - ); - procedure simGenerateWaveform( - signal Wave : out T_SLV_48; - constant Waveform : in T_SIM_WAVEFORM_SLV_48; - constant InitialValue : in T_SLV_48 := (others => '0') - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_48; - constant Waveform : in T_SIM_WAVEFORM_SLV_48; - constant InitialValue : in T_SLV_48 := (others => '0') - ); - procedure simGenerateWaveform( - signal Wave : out T_SLV_64; - constant Waveform : in T_SIM_WAVEFORM_SLV_64; - constant InitialValue : in T_SLV_64 := (others => '0') - ); - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_64; - constant Waveform : in T_SIM_WAVEFORM_SLV_64; - constant InitialValue : in T_SLV_64 := (others => '0') - ); - - function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM; - function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM; - function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8; - function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8; - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16; - function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16; - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24; - function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24; - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32; - function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32; - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48; - function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48; - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64; - function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64; - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64; - - -- convert arrays to waveforms - -- TODO: optimize waveform if input data doesn't change - -- TODO: write single bit variant - function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM; - function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL; - function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8; - function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16; - function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24; - function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32; - function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48; - function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64; - - -- predefined common waveforms - function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM; - - -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here - end package; - - -package body waveform is - -- clock generation - -- =========================================================================== - procedure simGenerateClock( - signal Clock : out std_logic; - constant Frequency : in FREQ; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ) is - constant Period : time := to_time(Frequency); - begin - simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander); - end procedure; - - procedure simGenerateClock( - constant TestID : in T_SIM_TEST_ID; - signal Clock : out std_logic; - constant Frequency : in FREQ; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ) is - constant Period : time := to_time(Frequency); - begin - simGenerateClock(TestID, Clock, Period, Phase, DutyCycle, Wander); - end procedure; - - procedure simGenerateClock( - signal Clock : out std_logic; - constant Period : in time; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ) is - begin - simGenerateClock(C_SIM_DEFAULT_TEST_ID, Clock, Period, Phase, DutyCycle, Wander); - end procedure; - - procedure simGenerateClock( - constant TestID : in T_SIM_TEST_ID; - signal Clock : out std_logic; - constant Period : in time; - constant Phase : in T_PHASE := 0 deg; - constant DutyCycle : in T_DUTYCYCLE := 50 percent; - constant Wander : in T_WANDER := 0 permil - ) is - constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360° - constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle - constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9; - constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0; - constant Delay : time := Period * PhaseAsFactor; - constant TimeHigh : time := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level - constant TimeLow : time := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level - constant ClockAfterRun_cy : positive := 5; - - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateClock(period=" & to_string(Period, 2) & ")", IsLowPriority => TRUE); - begin - -- report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & LF & - -- "Period: " & TIME'image(Period) & LF & - -- "Phase: " & T_PHASE'image(Phase) & LF & - -- "DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & LF & - -- "PhaseAsFactor: " & REAL'image(PhaseAsFactor) & LF & - -- "WanderAsFactor: " & REAL'image(WanderAsFactor) & LF & - -- "DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & LF & - -- "Delay: " & TIME'image(Delay) & LF & - -- "TimeHigh: " & TIME'image(TimeHigh) & LF & - -- "TimeLow: " & TIME'image(TimeLow) - -- severity NOTE; - - if (Delay = 0 ns) then - null; - elsif (Delay <= TimeLow) then - Clock <= '0'; - wait for Delay; - else - Clock <= '1'; - wait for Delay - TimeLow; - Clock <= '0'; - wait for TimeLow; - end if; - Clock <= '1'; - while not simIsStopped(TestID) loop - wait for TimeHigh; - Clock <= '0'; - wait for TimeLow; - Clock <= '1'; - end loop; - simDeactivateProcess(PROCESS_ID); - -- create N more cycles to allow other processes to recognize the stop condition (clock after run) - for i in 1 to ClockAfterRun_cy loop - wait for TimeHigh; - Clock <= '0'; - wait for TimeLow; - Clock <= '1'; - end loop; - Clock <= '0'; - end procedure; - - type T_SIM_NORMAL_DIST_PARAMETER is record - StandardDeviation : REAL; - Mean : REAL; - end record; - type T_JITTER_DISTRIBUTION is array (natural range <>) of T_SIM_NORMAL_DIST_PARAMETER; - - procedure simGenerateClock2( - constant TestID : in T_SIM_TEST_ID; - signal Clock : out std_logic; - signal Debug : out REAL; - constant Period : in time - ) is - constant TimeHigh : time := Period * 0.5; - constant TimeLow : time := Period - TimeHigh; - constant JitterPeakPeak : REAL := 0.1; -- UI - constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge - constant JitterDistribution : T_JITTER_DISTRIBUTION := ( - -- 0 => (StandardDeviation => 0.2, Mean => -0.4), - -- 1 => (StandardDeviation => 0.2, Mean => 0.4) - - -- 0 => (StandardDeviation => 0.2, Mean => -0.4), - -- 1 => (StandardDeviation => 0.3, Mean => -0.1), - -- 2 => (StandardDeviation => 0.5, Mean => 0.0), - -- 3 => (StandardDeviation => 0.3, Mean => 0.1), - -- 4 => (StandardDeviation => 0.2, Mean => 0.4) - - 0 => (StandardDeviation => 0.15, Mean => -0.6), - 1 => (StandardDeviation => 0.2, Mean => -0.3), - 2 => (StandardDeviation => 0.25, Mean => -0.2), - 3 => (StandardDeviation => 0.3, Mean => 0.0), - 4 => (StandardDeviation => 0.25, Mean => 0.2), - 5 => (StandardDeviation => 0.2, Mean => 0.3), - 6 => (StandardDeviation => 0.15, Mean => 0.6) - ); - variable Seed : T_SIM_RAND_SEED; - variable rand : REAL; - variable Jitter : REAL; - variable Index : natural; - - constant ClockAfterRun_cy : positive := 5; - begin - Clock <= '1'; - randInitializeSeed(Seed); - - while not simIsStopped(TestID) loop - ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand); - Index := scale(rand, 0, JitterDistribution'length * 10) mod JitterDistribution'length; - randNormalDistributedValue(Seed, rand, JitterDistribution(Index).StandardDeviation, JitterDistribution(Index).Mean, -1.0, 1.0); - - Jitter := JitterAsFactor * rand; - Debug <= rand; - - -- Debug <= integer(rand * 256.0 + 256.0); - wait for TimeHigh + (Period * Jitter); - Clock <= '0'; - wait for TimeLow + (Period * Jitter); - Clock <= '1'; - end loop; - -- create N more cycles to allow other processes to recognize the stop condition (clock after run) - for i in 1 to ClockAfterRun_cy loop - wait for TimeHigh; - Clock <= '0'; - wait for TimeLow; - Clock <= '1'; - end loop; - Clock <= '0'; - end procedure; - - - procedure simWaitUntilRisingEdge(signal Clock : in std_logic; constant Times : in positive) is - begin - simWaitUntilRisingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times); - end procedure; - - procedure simWaitUntilRisingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is - begin - for i in 1 to Times loop - wait until rising_edge(Clock); - exit when simIsStopped(TestID); - end loop; - end procedure; - - procedure simWaitUntilFallingEdge(signal Clock : in std_logic; constant Times : in positive) is - begin - simWaitUntilFallingEdge(C_SIM_DEFAULT_TEST_ID, Clock, Times); - end procedure; - - procedure simWaitUntilFallingEdge(constant TestID : in T_SIM_TEST_ID; signal Clock : in std_logic; constant Times : in positive) is - begin - for i in 1 to Times loop - wait until falling_edge(Clock); - exit when simIsStopped(TestID); - end loop; - end procedure; - - -- waveform generation - -- =========================================================================== - procedure simGenerateWaveform( - signal Wave : out boolean; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in boolean := FALSE - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out boolean; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in boolean := FALSE - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - variable State : boolean; - begin - State := InitialValue; - Wave <= State; - for i in Waveform'range loop - wait for Waveform(i); - State := not State; - Wave <= State; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in std_logic := '0' - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM; - constant InitialValue : in std_logic := '0' - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - variable State : std_logic; - begin - State := InitialValue; - Wave <= State; - for i in Waveform'range loop - wait for Waveform(i); - State := not State; - Wave <= State; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in std_logic := '0' - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out std_logic; - constant Waveform : in T_SIM_WAVEFORM_SL; - constant InitialValue : in std_logic := '0' - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out T_SLV_8; - constant Waveform : in T_SIM_WAVEFORM_SLV_8; - constant InitialValue : in T_SLV_8 := (others => '0') - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_8; - constant Waveform : in T_SIM_WAVEFORM_SLV_8; - constant InitialValue : in T_SLV_8 := (others => '0') - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out T_SLV_16; - constant Waveform : in T_SIM_WAVEFORM_SLV_16; - constant InitialValue : in T_SLV_16 := (others => '0') - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_16; - constant Waveform : in T_SIM_WAVEFORM_SLV_16; - constant InitialValue : in T_SLV_16 := (others => '0') - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out T_SLV_24; - constant Waveform : in T_SIM_WAVEFORM_SLV_24; - constant InitialValue : in T_SLV_24 := (others => '0') - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_24; - constant Waveform : in T_SIM_WAVEFORM_SLV_24; - constant InitialValue : in T_SLV_24 := (others => '0') - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out T_SLV_32; - constant Waveform : in T_SIM_WAVEFORM_SLV_32; - constant InitialValue : in T_SLV_32 := (others => '0') - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_32; - constant Waveform : in T_SIM_WAVEFORM_SLV_32; - constant InitialValue : in T_SLV_32 := (others => '0') - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out T_SLV_48; - constant Waveform : in T_SIM_WAVEFORM_SLV_48; - constant InitialValue : in T_SLV_48 := (others => '0') - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_48; - constant Waveform : in T_SIM_WAVEFORM_SLV_48; - constant InitialValue : in T_SLV_48 := (others => '0') - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - procedure simGenerateWaveform( - signal Wave : out T_SLV_64; - constant Waveform : in T_SIM_WAVEFORM_SLV_64; - constant InitialValue : in T_SLV_64 := (others => '0') - ) is - begin - simGenerateWaveform(C_SIM_DEFAULT_TEST_ID, Wave, Waveform, InitialValue); - end procedure; - - procedure simGenerateWaveform( - constant TestID : in T_SIM_TEST_ID; - signal Wave : out T_SLV_64; - constant Waveform : in T_SIM_WAVEFORM_SLV_64; - constant InitialValue : in T_SLV_64 := (others => '0') - ) is - constant PROCESS_ID : T_SIM_PROCESS_ID := simRegisterProcess(TestID, "simGenerateWaveform"); - begin - Wave <= InitialValue; - for i in Waveform'range loop - wait for Waveform(i).Delay; - Wave <= Waveform(i).Value; - exit when simIsStopped(TestID); - end loop; - simDeactivateProcess(PROCESS_ID); - end procedure; - - -- Waveform arithmetic - function "*" (Wave : T_SIM_WAVEFORM; Times : natural) return T_SIM_WAVEFORM is - variable Result : T_SIM_WAVEFORM(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is - begin - return (Wave(Wave'low) + Offset) & Wave(Wave'low + 1 to Wave'high); - end function; - - function "<" (Wave : T_SIM_WAVEFORM; Offset : time) return T_SIM_WAVEFORM is - variable Result : T_SIM_WAVEFORM(Wave'range); - variable TimePos : time; - begin - report "Has bugs" severity ERROR; - TimePos := 0 fs; - for i in Wave'range loop - TimePos := TimePos + Wave(i); - if TimePos > Offset then - return (TimePos - Offset) & Wave(i + 1 to Wave'high); - end if; - end loop; - return (0 => 0 fs); - end function; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_8; Times : natural) return T_SIM_WAVEFORM_SLV_8 is - variable Result : T_SIM_WAVEFORM_SLV_8(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : time) return T_SIM_WAVEFORM_SLV_8 is - begin - return T_SIM_WAVEFORM_TUPLE_SLV_8'( - Delay => Wave(Wave'low).Delay + Offset, - Value => Wave(Wave'low).Value - ) & Wave(Wave'low + 1 to Wave'high); - end function; - - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_8; Offset : TIME) return T_SIM_WAVEFORM_SLV_8 is - -- begin - -- report "Not implemented" severity FAILURE; - -- end function; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_16; Times : natural) return T_SIM_WAVEFORM_SLV_16 is - variable Result : T_SIM_WAVEFORM_SLV_16(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : time) return T_SIM_WAVEFORM_SLV_16 is - begin - return T_SIM_WAVEFORM_TUPLE_SLV_16'( - Delay => Wave(Wave'low).Delay + Offset, - Value => Wave(Wave'low).Value - ) & Wave(Wave'low + 1 to Wave'high); - end function; - - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_16; Offset : TIME) return T_SIM_WAVEFORM_SLV_16 is - -- begin - -- report "Not implemented" severity FAILURE; - -- end function; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_24; Times : natural) return T_SIM_WAVEFORM_SLV_24 is - variable Result : T_SIM_WAVEFORM_SLV_24(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : time) return T_SIM_WAVEFORM_SLV_24 is - begin - return T_SIM_WAVEFORM_TUPLE_SLV_24'( - Delay => Wave(Wave'low).Delay + Offset, - Value => Wave(Wave'low).Value - ) & Wave(Wave'low + 1 to Wave'high); - end function; - - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_24; Offset : TIME) return T_SIM_WAVEFORM_SLV_24 is - -- begin - -- report "Not implemented" severity FAILURE; - -- end function; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_32; Times : natural) return T_SIM_WAVEFORM_SLV_32 is - variable Result : T_SIM_WAVEFORM_SLV_32(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : time) return T_SIM_WAVEFORM_SLV_32 is - begin - return T_SIM_WAVEFORM_TUPLE_SLV_32'( - Delay => Wave(Wave'low).Delay + Offset, - Value => Wave(Wave'low).Value - ) & Wave(Wave'low + 1 to Wave'high); - end function; - - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_32; Offset : TIME) return T_SIM_WAVEFORM_SLV_32 is - -- begin - -- report "Not implemented" severity FAILURE; - -- end function; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_48; Times : natural) return T_SIM_WAVEFORM_SLV_48 is - variable Result : T_SIM_WAVEFORM_SLV_48(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : time) return T_SIM_WAVEFORM_SLV_48 is - begin - return T_SIM_WAVEFORM_TUPLE_SLV_48'( - Delay => Wave(Wave'low).Delay + Offset, - Value => Wave(Wave'low).Value - ) & Wave(Wave'low + 1 to Wave'high); - end function; - - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_48; Offset : TIME) return T_SIM_WAVEFORM_SLV_48 is - -- begin - -- report "Not implemented" severity FAILURE; - -- end function; - - function "*" (Wave : T_SIM_WAVEFORM_SLV_64; Times : natural) return T_SIM_WAVEFORM_SLV_64 is - variable Result : T_SIM_WAVEFORM_SLV_64(0 to Wave'length * Times - 1); - begin - for i in 0 to Times - 1 loop - Result(i * Wave'length to (i + 1) * Wave'length - 1) := Wave; - end loop; - return Result; - end function; - - function ">" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : time) return T_SIM_WAVEFORM_SLV_64 is - begin - return T_SIM_WAVEFORM_TUPLE_SLV_64'( - Delay => Wave(Wave'low).Delay + Offset, - Value => Wave(Wave'low).Value - ) & Wave(Wave'low + 1 to Wave'high); - end function; - - -- function "<" (Wave : T_SIM_WAVEFORM_SLV_64; Offset : TIME) return T_SIM_WAVEFORM_SLV_64 is - -- begin - -- report "Not implemented" severity FAILURE; - -- end function; - - - function to_waveform(bv : bit_vector; Delay : time) return T_SIM_WAVEFORM is - variable Result : T_SIM_WAVEFORM(0 to bv'length - 1); - begin - report "Has bugs" severity ERROR; - for i in 0 to bv'length - 1 loop - Result(i) := Delay; - end loop; - return Result; - end function; - - function to_waveform(slv : std_logic_vector; Delay : time) return T_SIM_WAVEFORM_SL is - variable Result : T_SIM_WAVEFORM_SL(0 to slv'length - 1); - begin - for i in 0 to slv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slv(i); - end loop; - return Result; - end function; - - function to_waveform(slvv : T_SLVV_8; Delay : time) return T_SIM_WAVEFORM_SLV_8 is - variable Result : T_SIM_WAVEFORM_SLV_8(0 to slvv'length - 1); - begin - for i in 0 to slvv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slvv(i); - end loop; - return Result; - end function; - - function to_waveform(slvv : T_SLVV_16; Delay : time) return T_SIM_WAVEFORM_SLV_16 is - variable Result : T_SIM_WAVEFORM_SLV_16(0 to slvv'length - 1); - begin - for i in 0 to slvv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slvv(i); - end loop; - return Result; - end function; - - function to_waveform(slvv : T_SLVV_24; Delay : time) return T_SIM_WAVEFORM_SLV_24 is - variable Result : T_SIM_WAVEFORM_SLV_24(0 to slvv'length - 1); - begin - for i in 0 to slvv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slvv(i); - end loop; - return Result; - end function; - - function to_waveform(slvv : T_SLVV_32; Delay : time) return T_SIM_WAVEFORM_SLV_32 is - variable Result : T_SIM_WAVEFORM_SLV_32(0 to slvv'length - 1); - begin - for i in 0 to slvv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slvv(i); - end loop; - return Result; - end function; - - function to_waveform(slvv : T_SLVV_48; Delay : time) return T_SIM_WAVEFORM_SLV_48 is - variable Result : T_SIM_WAVEFORM_SLV_48(0 to slvv'length - 1); - begin - for i in 0 to slvv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slvv(i); - end loop; - return Result; - end function; - - function to_waveform(slvv : T_SLVV_64; Delay : time) return T_SIM_WAVEFORM_SLV_64 is - variable Result : T_SIM_WAVEFORM_SLV_64(0 to slvv'length - 1); - begin - for i in 0 to slvv'length - 1 loop - Result(i).Delay := Delay; - Result(i).Value := slvv(i); - end loop; - return Result; - end function; - - -- predefined common waveforms - function simGenerateWaveform_Reset(constant Pause : time := 0 ns; ResetPulse : time := 10 ns) return T_SIM_WAVEFORM is - variable p : time; - variable rp : time; - begin - -- WORKAROUND: for Mentor QuestaSim/ModelSim - -- Version: 10.4c - -- Issue: - -- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns), - -- regardless of the passed function parameters - -- Bugfix: - -- The bugfix will be included in 10.5a, but this workaround must be - -- present until Altera updates the embedded ModelSim Altera Edition. - p := Pause; - rp := ResetPulse; - return (0 => p, 1 => rp); - end function; -end package body; diff --git a/src/sort/sort.pro b/src/sort/sort.pro index 83262d4b6..9470a842b 100644 --- a/src/sort/sort.pro +++ b/src/sort/sort.pro @@ -1,6 +1,6 @@ # ============================================================================= -# Authors: -# Adrian Weiland +# Authors: Adrian Weiland +# Stefan Unrein # # License: # ============================================================================= @@ -22,3 +22,4 @@ analyze sort_lru_cache.vhdl analyze sort_lru_list.vhdl +include ./sortnet/sortnet.pro diff --git a/src/sort/sort_lru_cache.files b/src/sort/sort_lru_cache.files deleted file mode 100644 index e2e968a81..000000000 --- a/src/sort/sort_lru_cache.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -include "src/arith/arith_prefix_and.files" - -# PoC.sort -vhdl poc "src/sort/sort_lru_cache.vhdl" # Top-Level diff --git a/src/sort/sort_lru_list.files b/src/sort/sort_lru_list.files deleted file mode 100644 index 8c39b15f0..000000000 --- a/src/sort/sort_lru_list.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.arith -include "src/arith/arith_prefix_and.files" - -# PoC.sort -vhdl poc "src/sort/sort_lru_list.vhdl" # Top-Level diff --git a/src/sort/sortnet/sortnet.pro b/src/sort/sortnet/sortnet.pro new file mode 100644 index 000000000..28d96f881 --- /dev/null +++ b/src/sort/sortnet/sortnet.pro @@ -0,0 +1,28 @@ +# ============================================================================= +# Authors: Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./sortnet.pkg.vhdl +analyze ./sortnet_BitonicSort.vhdl +analyze ./sortnet_MergeSort_Streamed.vhdl +analyze ./sortnet_OddEvenMergeSort.vhdl +analyze ./sortnet_OddEvenSort.vhdl +analyze ./sortnet_Transform.vhdl +analyze ./sortnet_Stream_Adapter.vhdl +analyze ./sortnet_Stream_Adapter2.vhdl diff --git a/src/sort/sortnet/sortnet_BitonicSort.files b/src/sort/sortnet/sortnet_BitonicSort.files deleted file mode 100644 index 0a7ddc601..000000000 --- a/src/sort/sortnet/sortnet_BitonicSort.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.sort.sortnet -vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # -vhdl poc "src/sort/sortnet/sortnet_BitonicSort.vhdl" # Top-Level diff --git a/src/sort/sortnet/sortnet_MergeSort_Streamed.files b/src/sort/sortnet/sortnet_MergeSort_Streamed.files deleted file mode 100644 index a857f8daf..000000000 --- a/src/sort/sortnet/sortnet_MergeSort_Streamed.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.sort.sortnet -vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # -vhdl poc "src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl" # Top-Level diff --git a/src/sort/sortnet/sortnet_OddEvenMergeSort.files b/src/sort/sortnet/sortnet_OddEvenMergeSort.files deleted file mode 100644 index 500aebd7d..000000000 --- a/src/sort/sortnet/sortnet_OddEvenMergeSort.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.sort.sortnet -vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # -vhdl poc "src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl" # Top-Level diff --git a/src/sort/sortnet/sortnet_OddEvenSort.files b/src/sort/sortnet/sortnet_OddEvenSort.files deleted file mode 100644 index 17d5c6db9..000000000 --- a/src/sort/sortnet/sortnet_OddEvenSort.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.sort.sortnet -vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # -vhdl poc "src/sort/sortnet/sortnet_OddEvenSort.vhdl" # Top-Level diff --git a/src/sort/sortnet/sortnet_Stream_Adapter.files b/src/sort/sortnet/sortnet_Stream_Adapter.files deleted file mode 100644 index 36cd1bb31..000000000 --- a/src/sort/sortnet/sortnet_Stream_Adapter.files +++ /dev/null @@ -1,19 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.gearbox -include "src/misc/gearbox/gearbox_down_cc.files" # -include "src/misc/gearbox/gearbox_up_cc.files" # - -# PoC.sort.sortnet -vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # -include "src/sort/sortnet/sortnet_BitonicSort.files" # -include "src/sort/sortnet/sortnet_OddEvenSort.files" # -include "src/sort/sortnet/sortnet_OddEvenMergeSort.files" # -vhdl poc "src/sort/sortnet/sortnet_Stream_Adapter.vhdl" # Top-Level diff --git a/src/sort/sortnet/sortnet_Stream_Adapter2.files b/src/sort/sortnet/sortnet_Stream_Adapter2.files deleted file mode 100644 index cb9e9544f..000000000 --- a/src/sort/sortnet/sortnet_Stream_Adapter2.files +++ /dev/null @@ -1,24 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.fifo -include "src/fifo/fifo_cc_got.files" # - -# PoC.misc.gearbox -include "src/misc/gearbox/gearbox_down_cc.files" # -include "src/misc/gearbox/gearbox_up_cc.files" # - -# PoC.sort.sortnet -vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # -include "src/sort/sortnet/sortnet_BitonicSort.files" # -include "src/sort/sortnet/sortnet_MergeSort_Streamed.files" # -include "src/sort/sortnet/sortnet_OddEvenSort.files" # -include "src/sort/sortnet/sortnet_OddEvenMergeSort.files" # -vhdl poc "src/sort/sortnet/sortnet_Transform.vhdl" # -vhdl poc "src/sort/sortnet/sortnet_Stream_Adapter2.vhdl" # Top-Level diff --git a/src/sync/sync.pro b/src/sync/sync.pro index 596a34d87..e567827a1 100644 --- a/src/sync/sync.pro +++ b/src/sync/sync.pro @@ -1,3 +1,23 @@ +# ============================================================================= +# Authors: Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + analyze ./sync.pkg.vhdl if { $::poc::vendor eq "Xilinx" } { diff --git a/src/sync/sync_Bits.files b/src/sync/sync_Bits.files deleted file mode 100644 index f45c47610..000000000 --- a/src/sync/sync_Bits.files +++ /dev/null @@ -1,24 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -vhdl poc "src/misc/sync/sync.pkg.vhdl" -if (DeviceVendor = "Altera") then - include "lib/Altera.files" # Altera primitives - vhdl poc "src/misc/sync/sync_Bits_Altera.vhdl" -elseif (DeviceVendor = "Xilinx") then - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/misc/sync/sync_Bits_Xilinx.vhdl" - if (ToolChain = "Xilinx_ISE") then -# ucf "ucf/misc/sync/sync_Bits_Xilinx.ucf" - elseif (ToolChain = "Xilinx_Vivado") then -# xdc "ucf/misc/sync/sync_Bits_Xilinx.xdc" - end if -end if -vhdl poc "src/misc/sync/sync_Bits.vhdl" # Top-Level diff --git a/src/sync/sync_Command.files b/src/sync/sync_Command.files deleted file mode 100644 index 07ae7c3dd..000000000 --- a/src/sync/sync_Command.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer -vhdl poc "src/misc/sync/sync_Command.vhdl" # diff --git a/src/sync/sync_Pulse.files b/src/sync/sync_Pulse.files deleted file mode 100644 index f38769520..000000000 --- a/src/sync/sync_Pulse.files +++ /dev/null @@ -1,26 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -vhdl poc "src/misc/sync/sync.pkg.vhdl" -if (DeviceVendor = "Altera") then - include "lib/Altera.files" # Altera primitives - vhdl poc "src/misc/sync/sync_Bits_Altera.vhdl" - vhdl poc "src/misc/sync/sync_Pulse_Altera.vhdl" -elseif (DeviceVendor = "Xilinx") then - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/misc/sync/sync_Bits_Xilinx.vhdl" - vhdl poc "src/misc/sync/sync_Pulse_Xilinx.vhdl" - if (ToolChain = "Xilinx_ISE") then -# ucf "ucf/misc/sync/sync_Bits_Xilinx.ucf" - elseif (ToolChain = "Xilinx_Vivado") then -# xdc "ucf/misc/sync/sync_Bits_Xilinx.xdc" - end if -end if -vhdl poc "src/misc/sync/sync_Pulse.vhdl" # Top-Level diff --git a/src/sync/sync_Reset.files b/src/sync/sync_Reset.files deleted file mode 100644 index 097f140a9..000000000 --- a/src/sync/sync_Reset.files +++ /dev/null @@ -1,24 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -vhdl poc "src/misc/sync/sync.pkg.vhdl" # -if (DeviceVendor = "Altera") then - include "lib/Altera.files" # Altera primitives - vhdl poc "src/misc/sync/sync_Reset_Altera.vhdl" # -elseif (DeviceVendor = "Xilinx") then - include "lib/Xilinx.files" # Xilinx primitives - vhdl poc "src/misc/sync/sync_Reset_Xilinx.vhdl" # - if (ToolChain = "Xilinx_ISE") then - ucf "ucf/misc/sync/sync_Reset_Xilinx.ucf" # - elseif (ToolChain = "Xilinx_Vivado") then - xdc "ucf/misc/sync/sync_Reset_Xilinx.xdc" # - end if -end if -vhdl poc "src/misc/sync/sync_Reset.vhdl" # diff --git a/src/sync/sync_Strobe.files b/src/sync/sync_Strobe.files deleted file mode 100644 index b203fa6f5..000000000 --- a/src/sync/sync_Strobe.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer -vhdl poc "src/misc/sync/sync_Strobe.vhdl" # diff --git a/src/sync/sync_Vector.files b/src/sync/sync_Vector.files deleted file mode 100644 index 4e503724e..000000000 --- a/src/sync/sync_Vector.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer -vhdl poc "src/misc/sync/sync_Vector.vhdl" # diff --git a/src/xil/mig/README.md b/src/xil/mig/README.md deleted file mode 100644 index b521850f7..000000000 --- a/src/xil/mig/README.md +++ /dev/null @@ -1,31 +0,0 @@ -# Namespace `PoC.xil.mig` - -The namespace `PoC.xil.mig` offers pre-configured memory controllers generated -with Xilinx's Memory Interface Generator (MIG). - - -## Entities - - - **for Spartan-6 boards:** - - [`mig_Atlys_1x128`][mig_Atlys_1x128] A DDR2 memory controller for the Digilent Atlys board. - Run PoC's [synthesis flow][netlist] twice: - 1. Generate the source files from the IP core using Xilinx MIG and afterwards patch them - `PS> .\poc.ps1 coregen PoC.xil.mig.Atlys_1x128 -l --board Atlys` - 2. Compile the patched sources into a ready to use netlist (\*.ngc) and constraint file (\*.ucf) - `PS> .\poc.ps1 xst PoC.xil.mig.Atlys_1x128 -l --board Atlys` - - **for Kintex-7 boards:** - - [`mig_KC705_MT8JTF12864HZ_1G6`][mig_KC705_MT8JTF12864HZ_1G6] A DDR3 memory controller for the Xilinx KC705 board. - Run PoC's [synthesis flow][netlist] twice: - 1. Generate the source files from the IP core using Xilinx MIG and afterwards patch them - `PS> .\poc.ps1 coregen PoC.xil.mig.KC705_MT8JTF12864HZ_1G6 -l --board KC705` - 2. Compile the patched sources into a ready to use netlist (\*.ngc) and constraint file (\*.ucf) - `PS> .\poc.ps1 xst PoC.xil.mig.KC705_MT8JTF12864HZ_1G6 -l --board KC705` - - for Virtex-7 boards: - - ... - - [mig.pkg]: mig.pkg.vhdl - - [mig_Atlys_1x128]: mig_Atlys_1x128.xco - [mig_KC705_MT8JTF12864HZ_1G6]: mig_KC705_MT8JTF12864HZ_1G6.xco - - [netlist]: ../../../netlist diff --git a/src/xil/mig/mig_Atlys_1x128.prj b/src/xil/mig/mig_Atlys_1x128.prj deleted file mode 100644 index 11ce85a94..000000000 --- a/src/xil/mig/mig_Atlys_1x128.prj +++ /dev/null @@ -1,62 +0,0 @@ - - - mig_Atlys_1x128 - xc6slx45-csg324/-3 - 3.92 - - DDR2_SDRAM/Components/MT47H64M16XX-25E - 3333 - 0 - 1 - FALSE - - 13 - 10 - 3 - - - - 8(011) - 5 - Enable-Normal - Fullstrength - 50ohms - 0 - OCD Exit - Enable - Disable - Enable - Disable - NATIVE - Class II - Class II - EXTERN_TERM - 25 Ohms - - - - Single-Ended - 1 - Disable - Single-Ended - One 128-bit bi-directional port - L6 - P4 - Port0 - Bi-directional - ROW_BANK_COLUMN - Round Robin - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - diff --git a/src/xil/mig/mig_Atlys_1x128.rules b/src/xil/mig/mig_Atlys_1x128.rules deleted file mode 100644 index 3aa7a2bed..000000000 --- a/src/xil/mig/mig_Atlys_1x128.rules +++ /dev/null @@ -1,41 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Notes: -# - all files are relative to PoCRoot directory -# - ${section:option} expressions refer to the section, wherein this rule file was referenced -# -PreProcessRules - Copy "${SrcDir}/${TopLevel}.prj" To "${SPECIAL:OutputDir}/${TopLevel}/user_design/mig.prj" -End PreProcessRules - -PostProcessRules - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/iodrp_controller.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/iodrp_controller.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/iodrp_mcb_controller.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/iodrp_mcb_controller.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/mcb_raw_wrapper.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/mcb_raw_wrapper.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/mcb_soft_calibration_top.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/mcb_soft_calibration_top.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/mcb_soft_calibration.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/mcb_soft_calibration.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/memc3_infrastructure.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/memc3_infrastructure.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/memc3_wrapper.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/memc3_wrapper.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/rtl/${TopLevel}.vhd" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_top.vhd" - Copy "${SPECIAL:OutputDir}/${TopLevel}/user_design/par/${TopLevel}.ucf" To "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf" - - File "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_top.vhd" - Replace "(entity ${TopLevel} is\\n\\s*generic\\s+?\\()" With "\\1\\n C3_CLKOUT2_DIVIDE : integer := 6; -- fraction of 600 MHz clock => 6 means 100 MHz\\n" Options Multiline - End File - File "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}_top.vhd" - Replace "(constant C3_CLKOUT2_DIVIDE\\s+: integer :=)\\s\\d+;" With "-- C3_CLKOUT2_DIVIDE is now a generic" - Replace "(constant C3_CLKFBOUT_MULT\\s+: integer :=)\\s\\d+;" With "\\1 6; -- for 100 MHz board clock" - End File - File "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/memc3_infrastructure.vhd" - Replace "(rst0_sync_r\\s+: std_logic.*?);" With "\\1 := (others => '1');" - Replace "(powerup_pll_locked\\s+: std_logic);" With "\\1 := '0';" - Replace " se_input_clk" With " -- Add option for no clock buffer\\n no_ibufg: if C_INPUT_CLK_TYPE = \"NONE\" generate sys_clk_ibufg <= sys_clk; end generate no_ibufg;\\n\\n se_input_clk" - End File - File "${PoC:NLDir}/${SPECIAL:Device}/${RelDir}/${TopLevel}.ncf" - Replace "(NET.*?SYS_CLK3.*?;)" With "#\\1" - Replace "(TIMESPEC.*?SYS_CLK3.*?;)" With "#\\1" - Replace "NET\\s+\\\"c3_sys_.*?;" With "" - End File -End PostProcessRules diff --git a/src/xil/mig/mig_Atlys_1x128.xco b/src/xil/mig/mig_Atlys_1x128.xco deleted file mode 100644 index 0c7601e3c..000000000 --- a/src/xil/mig/mig_Atlys_1x128.xco +++ /dev/null @@ -1,49 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Wed Jan 27 15:28:04 2016 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:mig:3.92 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92 -# END Select -# BEGIN Parameters -CSET component_name=mig_Atlys_1x128 -CSET xml_input_file=./mig_Atlys_1x128/user_design/mig.prj -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-10-13T18:46:09Z -# END Extra information -GENERATE -# CRC: df977e14 diff --git a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.prj b/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.prj deleted file mode 100644 index 15cd119d3..000000000 --- a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.prj +++ /dev/null @@ -1,191 +0,0 @@ - - - - mig_KC705_MT8JTF12864HZ_1G6 - 1 - 1 - OFF - 1024 - ON - Disabled - xc7k325t-ffg900/-2 - 1.9 - No Buffer - No Buffer - ACTIVE HIGH - FALSE - 0 - 50 Ohms - 1 - - DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 - 1428 - 2.0V - 4:1 - 200.08 - 0 - 1.000 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - FALSE - - 14 - 10 - 3 - 1.5V - ROW_BANK_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/7 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - NATIVE - - - diff --git a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules b/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules deleted file mode 100644 index b5b29b4b8..000000000 --- a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.rules +++ /dev/null @@ -1,77 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Notes: -# - all files are relative to PoCRoot directory -# - ${section:option} expressions refer to the section, wherin this rule file was referenced -# -# Section [CG.xil.mig.KC705_MT8JTF12864HZ_1G6.cg] defines `tempDir` and `dstDir` -# -PreProcessRules - Copy "${SrcDir}/${TopLevel}.prj" To "${tempDir}/mig.prj" -End PreProcessRules - -PostProcessRules - Copy "${tempDir}/user_design/rtl/ecc/mig_7series_v1_9_ecc_buf.v" To "${dstDir}/mig_7series_v1_9_ecc_buf.v" - Copy "${tempDir}/user_design/rtl/ecc/mig_7series_v1_9_ecc_gen.v" To "${dstDir}/mig_7series_v1_9_ecc_gen.v" - Copy "${tempDir}/user_design/rtl/ecc/mig_7series_v1_9_ecc_merge_enc.v" To "${dstDir}/mig_7series_v1_9_ecc_merge_enc.v" - Copy "${tempDir}/user_design/rtl/ecc/mig_7series_v1_9_ecc_dec_fix.v" To "${dstDir}/mig_7series_v1_9_ecc_dec_fix.v" - Copy "${tempDir}/user_design/rtl/clocking/mig_7series_v1_9_tempmon.v" To "${dstDir}/mig_7series_v1_9_tempmon.v" - Copy "${tempDir}/user_design/rtl/clocking/mig_7series_v1_9_clk_ibuf.v" To "${dstDir}/mig_7series_v1_9_clk_ibuf.v" - Copy "${tempDir}/user_design/rtl/clocking/mig_7series_v1_9_iodelay_ctrl.v" To "${dstDir}/mig_7series_v1_9_iodelay_ctrl.v" - Copy "${tempDir}/user_design/rtl/clocking/mig_7series_v1_9_infrastructure.v" To "${dstDir}/mig_7series_v1_9_infrastructure.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_bank_queue.v" To "${dstDir}/mig_7series_v1_9_bank_queue.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_bank_compare.v" To "${dstDir}/mig_7series_v1_9_bank_compare.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_arb_select.v" To "${dstDir}/mig_7series_v1_9_arb_select.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_arb_mux.v" To "${dstDir}/mig_7series_v1_9_arb_mux.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_col_mach.v" To "${dstDir}/mig_7series_v1_9_col_mach.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_bank_common.v" To "${dstDir}/mig_7series_v1_9_bank_common.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_bank_state.v" To "${dstDir}/mig_7series_v1_9_bank_state.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_mc.v" To "${dstDir}/mig_7series_v1_9_mc.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_bank_cntrl.v" To "${dstDir}/mig_7series_v1_9_bank_cntrl.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_rank_cntrl.v" To "${dstDir}/mig_7series_v1_9_rank_cntrl.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_bank_mach.v" To "${dstDir}/mig_7series_v1_9_bank_mach.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_rank_mach.v" To "${dstDir}/mig_7series_v1_9_rank_mach.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_arb_row_col.v" To "${dstDir}/mig_7series_v1_9_arb_row_col.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_rank_common.v" To "${dstDir}/mig_7series_v1_9_rank_common.v" - Copy "${tempDir}/user_design/rtl/controller/mig_7series_v1_9_round_robin_arb.v" To "${dstDir}/mig_7series_v1_9_round_robin_arb.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrlvl.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_wrlvl.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_init.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_init.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_mc_phy_wrapper.v" To "${dstDir}/mig_7series_v1_9_ddr_mc_phy_wrapper.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_mc_phy.v" To "${dstDir}/mig_7series_v1_9_ddr_mc_phy.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_tempmon.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_tempmon.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_4lanes.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_4lanes.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrcal.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_wrcal.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_calib_top.v" To "${dstDir}/mig_7series_v1_9_ddr_calib_top.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_if_post_fifo.v" To "${dstDir}/mig_7series_v1_9_ddr_if_post_fifo.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_rdlvl.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_rdlvl.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_dqs_found_cal.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_prbs_gen.v" To "${dstDir}/mig_7series_v1_9_ddr_prbs_gen.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_oclkdelay_cal.v" To "${dstDir}/mig_7series_v1_9_ddr_phy_oclkdelay_cal.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_of_pre_fifo.v" To "${dstDir}/mig_7series_v1_9_ddr_of_pre_fifo.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_byte_lane.v" To "${dstDir}/mig_7series_v1_9_ddr_byte_lane.v" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_top.vhd" To "${dstDir}/mig_7series_v1_9_ddr_phy_top.vhd" - Copy "${tempDir}/user_design/rtl/phy/mig_7series_v1_9_ddr_byte_group_io.v" To "${dstDir}/mig_7series_v1_9_ddr_byte_group_io.v" - Copy "${tempDir}/user_design/rtl/ip_top/mig_7series_v1_9_mem_intfc.v" To "${dstDir}/mig_7series_v1_9_mem_intfc.v" - Copy "${tempDir}/user_design/rtl/ip_top/mig_7series_v1_9_memc_ui_top_std.v" To "${dstDir}/mig_7series_v1_9_memc_ui_top_std.v" - Copy "${tempDir}/user_design/rtl/ui/mig_7series_v1_9_ui_top.v" To "${dstDir}/mig_7series_v1_9_ui_top.v" - Copy "${tempDir}/user_design/rtl/ui/mig_7series_v1_9_ui_rd_data.v" To "${dstDir}/mig_7series_v1_9_ui_rd_data.v" - Copy "${tempDir}/user_design/rtl/ui/mig_7series_v1_9_ui_wr_data.v" To "${dstDir}/mig_7series_v1_9_ui_wr_data.v" - Copy "${tempDir}/user_design/rtl/ui/mig_7series_v1_9_ui_cmd.v" To "${dstDir}/mig_7series_v1_9_ui_cmd.v" - Copy "${tempDir}/user_design/rtl/${TopLevel}.vhd" To "${dstDir}/${TopLevel}_top.vhd" - Copy "${tempDir}/user_design/constraints/${TopLevel}.ucf" To "${dstDir}/${TopLevel}.ncf" - Copy "${tempDir}/user_design/constraints/${TopLevel}.ucf" To "${dstDir}/${TopLevel}.xcf" - File "${dstDir}/${TopLevel}.ncf" - Replace "DATAPATHONLY;" With "DATAPATHONLY;\\nINST \"*/xadc_supplied_temperature.rst_r1*\" TNM=\"TNM_XADC_ASYNC_RST\";\\nTIMESPEC \"TS_XADC_ASYNC_RST\" = TO \"TNM_XADC_ASYNC_RST\" TIG;" - End File - File "${dstDir}/${TopLevel}.xcf" - Replace "############## NET - IOSTANDARD.*" With "" Options MultiLine, DotAll - Replace "#NET" With "NET" - Replace "#TIMESPEC" With "TIMESPEC" - End File -End PostProcessRules diff --git a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xco b/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xco deleted file mode 100644 index 1d9a5064f..000000000 --- a/src/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.xco +++ /dev/null @@ -1,49 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Fri Feb 19 14:25:48 2016 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:mig_7series:1.9 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc7k325t -SET devicefamily = kintex7 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ffg900 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT MIG_7_Series family Xilinx,_Inc. 1.9 -# END Select -# BEGIN Parameters -CSET component_name=mig_KC705_MT8JTF12864HZ_1G6 -CSET xml_input_file=./mig_KC705_MT8JTF12864HZ_1G6/mig.prj -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-10-13T18:46:09Z -# END Extra information -GENERATE -# CRC: ce56b5e9 diff --git a/src/xil/xil.pkg.vhdl b/src/xil/xil.pkg.vhdl index 0728bac88..9b7933f25 100644 --- a/src/xil/xil.pkg.vhdl +++ b/src/xil/xil.pkg.vhdl @@ -2,30 +2,30 @@ -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= --- Authors: Patrick Lehmann +-- Authors: Patrick Lehmann -- --- Entity: VHDL package for component declarations, types and functions --- associated to the PoC.xil namespace +-- Entity: VHDL package for component declarations, types and functions +-- associated to the PoC.xil namespace -- -- Description: -- ------------------------------------- --- This package declares types and components for --- - Xilinx ChipScope Pro IPCores (ICON, ILA, VIO) --- - Xilinx Dynamic Reconfiguration Port (DRP) related types --- - SystemMonitor for FPGA core temperature measurement and fan control --- (see PoC.io.FanControl) --- - Component declarations for Xilinx related modules +-- This package declares types and components for +-- - Xilinx Dynamic Reconfiguration Port (DRP) related types +-- - SystemMonitor for FPGA core temperature measurement and fan control +-- (see PoC.io.FanControl) +-- - Component declarations for Xilinx related modules -- -- License: -- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors -- Copyright 2007-2015 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- --- http://www.apache.org/licenses/LICENSE-2.0 +-- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, @@ -38,6 +38,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; +use work.config.all; use work.utils.all; use work.vectors.all; @@ -45,89 +46,112 @@ use work.vectors.all; package xil is -- ChipScope -- ========================================================================== - subtype T_XIL_CHIPSCOPE_CONTROL is std_logic_vector(35 downto 0); - type T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (natural range <>) of T_XIL_CHIPSCOPE_CONTROL; + subtype T_XIL_CHIPSCOPE_CONTROL is std_logic_vector(35 downto 0); + type T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (natural range <>) of T_XIL_CHIPSCOPE_CONTROL; -- Dynamic Reconfiguration Port (DRP) -- ========================================================================== - subtype T_XIL_DRP_ADDRESS is T_SLV_16; - subtype T_XIL_DRP_DATA is T_SLV_16; + subtype T_XIL_DRP_ADDRESS is T_SLV_16; + subtype T_XIL_DRP_DATA is T_SLV_16; - type T_XIL_DRP_ADDRESS_VECTOR is array (natural range <>) of T_XIL_DRP_ADDRESS; - type T_XIL_DRP_DATA_VECTOR is array (natural range <>) of T_XIL_DRP_DATA; + type T_XIL_DRP_ADDRESS_VECTOR is array (natural range <>) of T_XIL_DRP_ADDRESS; + type T_XIL_DRP_DATA_VECTOR is array (natural range <>) of T_XIL_DRP_DATA; type T_XIL_DRP_BUS_IN is record - Clock : std_logic; - Enable : std_logic; - ReadWrite : std_logic; - Address : T_XIL_DRP_ADDRESS; - Data : T_XIL_DRP_DATA; + Clock : std_logic; + Enable : std_logic; + ReadWrite : std_logic; + Address : T_XIL_DRP_ADDRESS; + Data : T_XIL_DRP_DATA; end record; constant C_XIL_DRP_BUS_IN_EMPTY : T_XIL_DRP_BUS_IN := ( - Clock => '0', - Enable => '0', + Clock => '0', + Enable => '0', ReadWrite => '0', - Address => (others => '0'), - Data => (others => '0')); + Address => (others => '0'), + Data => (others => '0') + ); type T_XIL_DRP_BUS_OUT is record - Data : T_XIL_DRP_DATA; - Ack : std_logic; + Data : T_XIL_DRP_DATA; + Ack : std_logic; end record; constant C_XIL_DRP_BUS_OUT_EMPTY : T_XIL_DRP_BUS_OUT := ( - Ack => '0', - Data => (others => '0')); + Ack => '0', + Data => (others => '0') + ); type T_XIL_DRP_CONFIG is record - Address : T_XIL_DRP_ADDRESS; - Mask : T_XIL_DRP_DATA; - Data : T_XIL_DRP_DATA; + Address : T_XIL_DRP_ADDRESS; + Mask : T_XIL_DRP_DATA; + Data : T_XIL_DRP_DATA; end record; - -- define array indices - constant C_XIL_DRP_MAX_CONFIG_COUNT : positive := 8; +-- define array indices + constant C_XIL_DRP_MAX_CONFIG_COUNT : positive := 8; - subtype T_XIL_DRP_CONFIG_INDEX is integer range 0 to C_XIL_DRP_MAX_CONFIG_COUNT - 1; - type T_XIL_DRP_CONFIG_VECTOR is array (natural range <>) of T_XIL_DRP_CONFIG; + subtype T_XIL_DRP_CONFIG_INDEX is integer range 0 to C_XIL_DRP_MAX_CONFIG_COUNT - 1; + type T_XIL_DRP_CONFIG_VECTOR is array (natural range <>) of T_XIL_DRP_CONFIG; type T_XIL_DRP_CONFIG_SET is record - Configs : T_XIL_DRP_CONFIG_VECTOR(T_XIL_DRP_CONFIG_INDEX); - LastIndex : T_XIL_DRP_CONFIG_INDEX; + Configs : T_XIL_DRP_CONFIG_VECTOR(T_XIL_DRP_CONFIG_INDEX); + LastIndex : T_XIL_DRP_CONFIG_INDEX; end record; - type T_XIL_DRP_CONFIG_ROM is array (natural range <>) of T_XIL_DRP_CONFIG_SET; + type T_XIL_DRP_CONFIG_ROM is array (natural range <>) of T_XIL_DRP_CONFIG_SET; - constant C_XIL_DRP_CONFIG_EMPTY : T_XIL_DRP_CONFIG := ( - Address => (others => '0'), - Data => (others => '0'), - Mask => (others => '0') + constant C_XIL_DRP_CONFIG_EMPTY : T_XIL_DRP_CONFIG := ( + Address => (others => '0'), + Data => (others => '0'), + Mask => (others => '0') ); - constant C_XIL_DRP_CONFIG_SET_EMPTY : T_XIL_DRP_CONFIG_SET := ( - Configs => (others => C_XIL_DRP_CONFIG_EMPTY), - LastIndex => 0 + constant C_XIL_DRP_CONFIG_SET_EMPTY : T_XIL_DRP_CONFIG_SET := ( + Configs => (others => C_XIL_DRP_CONFIG_EMPTY), + LastIndex => 0 ); - component xil_ChipScopeICON is - generic ( - PORTS : positive - ); + function get_DNABITS return natural; + +------------COMPONENTS--------------------------- + component xil_SystemMonitor is port ( - ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0) + Reset : in std_logic; -- Reset signal for the System Monitor control logic + + Alarm_UserTemp : out std_logic; -- Temperature-sensor alarm output + Alarm_OverTemp : out std_logic; -- Over-Temperature alarm output + Alarm : out std_logic; -- OR'ed output of all the alarms + VP : in std_logic; -- Dedicated analog input pair + VN : in std_logic ); end component; - component xil_SystemMonitor is + component xil_DNAPort is + generic ( + SIM_DNA_VALUE : bit_vector := resize("0", get_DNABITS) -- DNA value for simulation + ); port ( - Reset : in std_logic; -- Reset signal for the System Monitor control logic - - Alarm_UserTemp : out std_logic; -- Temperature-sensor alarm output - Alarm_OverTemp : out std_logic; -- Over-Temperature alarm output - Alarm : out std_logic; -- OR'ed output of all the alarms - VP : in std_logic; -- Dedicated analog input pair - VN : in std_logic + Clock : in std_logic; + Reset : in std_logic; + Valid : out std_logic; + DataOut : out std_logic_vector(get_DNABITS -1 downto 0) ); end component; end package; + + +package body xil is + + function get_DNABITS return natural is + begin + case THIS_DEVICE.DevSeries is + when DEVICE_SERIES_7_SERIES => return 64; + when DEVICE_SERIES_ULTRASCALE_PLUS | + DEVICE_SERIES_ULTRASCALE => return 96; + when others => return 0; + end case; + end function; + +end package body; diff --git a/src/xil/xil.pro b/src/xil/xil.pro new file mode 100644 index 000000000..a6685007b --- /dev/null +++ b/src/xil/xil.pro @@ -0,0 +1,40 @@ +# ============================================================================= +# Authors: Adrian Weiland +# Jonas Schreiner +# Stefan Unrein +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +analyze ./xil.pkg.vhdl +if { $::poc::vendor eq "Xilinx" } { + analyze ./xil_DNAPort.vhdl + analyze ./xil_ICAP.vhdl + analyze ./xil_BSCAN.vhdl + analyze ./xil_Reconfigurator.vhdl + analyze ./xil_SystemMonitor.vhdl + analyze ./reconfig/reconfig_icap_fsm.vhdl + analyze ./reconfig/reconfig_icap_wrapper.vhdl + +} elseif { $::poc::vendor eq "Altera" } { + puts "No Altera files in this namespace." + +} elseif { $::poc::vendor ne "GENERIC" } { + puts "Unknow vendor '$::poc::vendor' in arith!" + exit 1 +} + diff --git a/src/xil/xil_BSCAN.files b/src/xil/xil_BSCAN.files deleted file mode 100644 index 7cf5cb919..000000000 --- a/src/xil/xil_BSCAN.files +++ /dev/null @@ -1,16 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.xil -if (Vendor = "Xilinx") then - vhdl PoC "src/xil/xil.pkg.vhdl" # PoC.xil package - vhdl PoC "src/xil/xil_BSCAN.vhdl" # Top-Level -else - report "These modules are for Xilinx only." -end if diff --git a/src/xil/xil_ChipScopeICON.files b/src/xil/xil_ChipScopeICON.files deleted file mode 100644 index adb2ea371..000000000 --- a/src/xil/xil_ChipScopeICON.files +++ /dev/null @@ -1,31 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.xil -if (Vendor = "Xilinx") then - vhdl PoC "src/xil/xil.pkg.vhdl" # PoC.xil package - xco PoC "PoC.xil.ChipScopeICON_1" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_2" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_3" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_4" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_5" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_6" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_7" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_8" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_9" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_10" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_11" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_12" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_13" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_14" # IP core generated by Xilinx ISE Core Generator - xco PoC "PoC.xil.ChipScopeICON_15" # IP core generated by Xilinx ISE Core Generator - vhdl PoC "src/xil/ChipScopeICON.vhdl" # Top-Level -else - report "These modules are for Xilinx only." -end if diff --git a/src/xil/xil_ChipScopeICON.vhdl b/src/xil/xil_ChipScopeICON.vhdl deleted file mode 100644 index 38a985389..000000000 --- a/src/xil/xil_ChipScopeICON.vhdl +++ /dev/null @@ -1,278 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- ============================================================================= --- Authors: Patrick Lehmann --- --- Entity: Generic Xilinx ChipScope ICON wrapper --- --- Description: --- ------------------------------------- --- This module wraps 15 ChipScope ICON IP core netlists generated from ChipScope --- ICON xco files. The generic parameter ``PORTS`` selects the apropriate ICON --- instance with 1 to 15 ICON ``ControlBus`` ports. Each ``ControlBus`` port is --- of type ``T_XIL_CHIPSCOPE_CONTROL`` and of mode ``inout``. --- --- .. rubric:: Compile required CoreGenerator IP Cores to Netlists with PoC --- --- Please use the provided Xilinx ISE compile command ``ise`` in PoC to recreate --- the needed source and netlist files on your local machine. --- --- .. code-block:: PowerShell --- --- cd PoCRoot --- .\poc.ps1 ise PoC.xil.ChipScopeICON --board=KC705 --- --- SeeAlso: --- :doc:`Using PoC -> Synthesis ` --- For how to run synthesis with PoC and CoreGenerator. --- --- License: --- ============================================================================= --- Copyright 2007-2016 Technische Universitaet Dresden - Germany --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -use work.xil.all; - - -entity xil_ChipScopeICON is - generic ( - PORTS : positive - ); - port ( - ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0) - ); -end entity; - - -architecture rtl of xil_ChipScopeICON is -begin - assert (PORTS < 16) report "To many ICON CONTROL ports." severity failure; - - genICON1 : if PORTS = 1 generate - ICON: entity work.xil_ChipScopeICON_1 - port map ( - CONTROL0 => ControlBus(0) - ); - end generate; - - genICON2 : if PORTS = 2 generate - ICON: entity work.xil_ChipScopeICON_2 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1) - ); - end generate; - - genICON3 : if PORTS = 3 generate - ICON: entity work.xil_ChipScopeICON_3 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2) - ); - end generate; - - genICON4 : if PORTS = 4 generate - ICON: entity work.xil_ChipScopeICON_4 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3) - ); - end generate; - - genICON5 : if PORTS = 5 generate - ICON: entity work.xil_ChipScopeICON_5 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4) - ); - end generate; - - genICON6 : if PORTS = 6 generate - ICON: entity work.xil_ChipScopeICON_6 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5) - ); - end generate; - - genICON7 : if PORTS = 7 generate - ICON: entity work.xil_ChipScopeICON_7 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6) - ); - end generate; - - genICON8 : if PORTS = 8 generate - ICON: entity work.xil_ChipScopeICON_8 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7) - ); - end generate; - - genICON9 : if PORTS = 9 generate - ICON: entity work.xil_ChipScopeICON_9 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8) - ); - end generate; - - genICON10 : if PORTS = 10 generate - ICON: entity work.xil_ChipScopeICON_10 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8), - CONTROL9 => ControlBus(9) - ); - end generate; - - genICON11 : if PORTS = 11 generate - ICON: entity work.xil_ChipScopeICON_11 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8), - CONTROL9 => ControlBus(9), - CONTROL10 => ControlBus(10) - ); - end generate; - - genICON12 : if PORTS = 12 generate - ICON: entity work.xil_ChipScopeICON_12 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8), - CONTROL9 => ControlBus(9), - CONTROL10 => ControlBus(10), - CONTROL11 => ControlBus(11) - ); - end generate; - - genICON13 : if PORTS = 13 generate - ICON: entity work.xil_ChipScopeICON_13 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8), - CONTROL9 => ControlBus(9), - CONTROL10 => ControlBus(10), - CONTROL11 => ControlBus(11), - CONTROL12 => ControlBus(12) - ); - end generate; - - genICON14 : if PORTS = 14 generate - ICON: entity work.xil_ChipScopeICON_14 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8), - CONTROL9 => ControlBus(9), - CONTROL10 => ControlBus(10), - CONTROL11 => ControlBus(11), - CONTROL12 => ControlBus(12), - CONTROL13 => ControlBus(13) - ); - end generate; - - genICON15 : if PORTS = 15 generate - ICON: entity work.xil_ChipScopeICON_15 - port map ( - CONTROL0 => ControlBus(0), - CONTROL1 => ControlBus(1), - CONTROL2 => ControlBus(2), - CONTROL3 => ControlBus(3), - CONTROL4 => ControlBus(4), - CONTROL5 => ControlBus(5), - CONTROL6 => ControlBus(6), - CONTROL7 => ControlBus(7), - CONTROL8 => ControlBus(8), - CONTROL9 => ControlBus(9), - CONTROL10 => ControlBus(10), - CONTROL11 => ControlBus(11), - CONTROL12 => ControlBus(12), - CONTROL13 => ControlBus(13), - CONTROL14 => ControlBus(14) - ); - end generate; -end architecture; diff --git a/src/xil/xil_ChipScopeICON_1.xco b/src/xil/xil_ChipScopeICON_1.xco deleted file mode 100644 index f887d9216..000000000 --- a/src/xil/xil_ChipScopeICON_1.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_1 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=1 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_10.xco b/src/xil/xil_ChipScopeICON_10.xco deleted file mode 100644 index c5b941966..000000000 --- a/src/xil/xil_ChipScopeICON_10.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_10 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=10 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_11.xco b/src/xil/xil_ChipScopeICON_11.xco deleted file mode 100644 index fc2d617bc..000000000 --- a/src/xil/xil_ChipScopeICON_11.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_11 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=11 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_12.xco b/src/xil/xil_ChipScopeICON_12.xco deleted file mode 100644 index be63df5d4..000000000 --- a/src/xil/xil_ChipScopeICON_12.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_12 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=12 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_13.xco b/src/xil/xil_ChipScopeICON_13.xco deleted file mode 100644 index 82df678c2..000000000 --- a/src/xil/xil_ChipScopeICON_13.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_13 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=13 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_14.xco b/src/xil/xil_ChipScopeICON_14.xco deleted file mode 100644 index 5634b86d6..000000000 --- a/src/xil/xil_ChipScopeICON_14.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_14 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=14 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_15.xco b/src/xil/xil_ChipScopeICON_15.xco deleted file mode 100644 index 6cbd5e854..000000000 --- a/src/xil/xil_ChipScopeICON_15.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_15 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=15 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_2.xco b/src/xil/xil_ChipScopeICON_2.xco deleted file mode 100644 index 3a91273cf..000000000 --- a/src/xil/xil_ChipScopeICON_2.xco +++ /dev/null @@ -1,56 +0,0 @@ -2############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_2 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=2 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_3.xco b/src/xil/xil_ChipScopeICON_3.xco deleted file mode 100644 index ab4da2cf6..000000000 --- a/src/xil/xil_ChipScopeICON_3.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_3 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=3 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_4.xco b/src/xil/xil_ChipScopeICON_4.xco deleted file mode 100644 index 44d8ce919..000000000 --- a/src/xil/xil_ChipScopeICON_4.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_4 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=4 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_5.xco b/src/xil/xil_ChipScopeICON_5.xco deleted file mode 100644 index ca7d99a1b..000000000 --- a/src/xil/xil_ChipScopeICON_5.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_5 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=5 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_6.xco b/src/xil/xil_ChipScopeICON_6.xco deleted file mode 100644 index a6edb165f..000000000 --- a/src/xil/xil_ChipScopeICON_6.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_6 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=6 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_7.xco b/src/xil/xil_ChipScopeICON_7.xco deleted file mode 100644 index d0b76a67d..000000000 --- a/src/xil/xil_ChipScopeICON_7.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_7 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=7 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_8.xco b/src/xil/xil_ChipScopeICON_8.xco deleted file mode 100644 index 41697cf9a..000000000 --- a/src/xil/xil_ChipScopeICON_8.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_8 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=8 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_ChipScopeICON_9.xco b/src/xil/xil_ChipScopeICON_9.xco deleted file mode 100644 index e3c65afbb..000000000 --- a/src/xil/xil_ChipScopeICON_9.xco +++ /dev/null @@ -1,56 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.6 -# Date: Sun Jun 15 09:54:20 2014 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = false -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc5vlx50t -SET devicefamily = virtex5 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = ff1136 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -1 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a -# END Select -# BEGIN Parameters -CSET component_name=xil_ChipScopeICON_9 -CSET constraint_type=external -CSET enable_jtag_bufg=true -CSET example_design=true -CSET number_control_ports=9 -CSET use_ext_bscan=false -CSET use_softbscan=false -CSET use_unused_bscan=false -CSET user_scan_chain=USER1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2013-06-08T17:28:33Z -# END Extra information -GENERATE -# CRC: 640eeda diff --git a/src/xil/xil_DNAPort.vhdl b/src/xil/xil_DNAPort.vhdl new file mode 100644 index 000000000..2a76630ac --- /dev/null +++ b/src/xil/xil_DNAPort.vhdl @@ -0,0 +1,112 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Stefan Unrein +-- +-- Entity: xil_DNA +-- +-- Description: This component provides the Internal "DNA" (Unique Serial Number +-- or ID) Data of Xilinx devices as parallel dataport. +-- ------------------------------------- +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +use work.config.all; +use work.utils.all; +use work.config.all; +use work.xil.all; +use work.components.all; + + +entity xil_DNAPort is + generic ( + SIM_DNA_VALUE : bit_vector := resize("0", get_DNABITS) -- DNA value for simulation + ); + port ( + Clock : in std_logic; + Reset : in std_logic; + Valid : out std_logic; + DataOut : out std_logic_vector(get_DNABITS -1 downto 0) + ); +end entity; + + +architecture rtl of xil_DNAPort is + alias DNA_VALUE : bit_vector(SIM_DNA_VALUE'length - 1 downto 0) is SIM_DNA_VALUE; + constant COUNTER_MAX : natural := DataOut'length +2; + + signal DataOut_i : DataOut'subtype := (others => '0'); + signal Shift : std_logic; + signal Read : std_logic; + signal DataOut_Shift : std_logic; + + signal counter_us : unsigned(log2ceilnz(COUNTER_MAX +1) -1 downto 0) := (others => '0'); + signal is_counter_high : std_logic; + signal is_counter_high_1 : std_logic; +begin + counter_us <= upcounter_next(cnt => counter_us, rst => Reset, en => not is_counter_high) when rising_edge(Clock); + is_counter_high <= upcounter_equal(counter_us, COUNTER_MAX); + is_counter_high_1 <= upcounter_equal(counter_us, COUNTER_MAX -1); + + Read <= '1' when counter_us = 1 else '0'; + Shift <= '1' when counter_us > 1 and is_counter_high_1 = '0' else '0'; + Valid <= is_counter_high; + DataOut <= DataOut_i; + + genSeries: if THIS_DEVICE.DevSeries = DEVICE_SERIES_7_SERIES generate + DataOut_i <= DataOut_i(DataOut_i'high -1 downto 0) & DataOut_Shift when rising_edge(Clock) and (counter_us > 1 and is_counter_high = '0'); + + DNA : component DNA_PORT + generic map ( + SIM_DNA_VALUE => DNA_VALUE + ) + port map ( + CLK => Clock, + READ => Read, + SHIFT => Shift, + DIN => '0', + DOUT => DataOut_Shift + ); + elsif (THIS_DEVICE.DevSeries = DEVICE_SERIES_ULTRASCALE_PLUS) or (DEVICE_SERIES = DEVICE_SERIES_ULTRASCALE) generate + DataOut_i <= DataOut_Shift & DataOut_i(DataOut_i'high downto 1) when rising_edge(Clock) and (counter_us > 1 and is_counter_high = '0'); + + DNA : component DNA_PORTE2 + generic map ( + SIM_DNA_VALUE => to_slv(DNA_VALUE) + ) + port map ( + CLK => Clock, + READ => Read, + SHIFT => Shift, + DIN => '0', + DOUT => DataOut_Shift + ); + else generate + assert false report "xil_DNAPort:: DEVICE_SERIES not supported!" severity failure; + end generate; +end architecture; diff --git a/src/xil/xil_ICAP.files b/src/xil/xil_ICAP.files deleted file mode 100644 index c2e229544..000000000 --- a/src/xil/xil_ICAP.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# PoC.xil -if (Vendor = "Xilinx") then - vhdl PoC "src/xil/xil_ICAP.vhdl" # Top-Level -else - report "These modules are for Xilinx only." -end if diff --git a/tb/arith/RunAllTests.pro b/tb/arith/RunAllTests.pro index d92adff2a..c29e726d7 100644 --- a/tb/arith/RunAllTests.pro +++ b/tb/arith/RunAllTests.pro @@ -1,9 +1,24 @@ # ============================================================================= -# Authors: -# Jonas Schreiner +# Authors: Jonas Schreiner +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. # ============================================================================= -TestSuite arith +TestSuite PoC.arith library tb_arith diff --git a/tb/arith/arith_addw_tb.files b/tb/arith/arith_addw_tb.files deleted file mode 100644 index b78c81b39..000000000 --- a/tb/arith/arith_addw_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_addw.files" # Unit Under Test - -# Testbench file(s) -if (Tool in ["Xilinx_iSim", "Xilinx_xSim"]) then - vhdl test "tb/arith/arith_addw_tb.iSim.vhdl" # Testbench -else - vhdl test "tb/arith/arith_addw_tb.vhdl" # Testbench -end if diff --git a/tb/arith/arith_convert_bin2bcd_tb.files b/tb/arith/arith_convert_bin2bcd_tb.files deleted file mode 100644 index 1c390b5cd..000000000 --- a/tb/arith/arith_convert_bin2bcd_tb.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_convert_bin2bcd.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/arith/arith_convert_bin2bcd_tb.vhdl" # Testbench - diff --git a/tb/arith/arith_counter_bcd_tb.files b/tb/arith/arith_counter_bcd_tb.files deleted file mode 100644 index d6c3373cf..000000000 --- a/tb/arith/arith_counter_bcd_tb.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_counter_bcd.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/arith/arith_counter_bcd_tb.vhdl" # Testbench - diff --git a/tb/arith/arith_div_tb.files b/tb/arith/arith_div_tb.files deleted file mode 100644 index 8af761f06..000000000 --- a/tb/arith/arith_div_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_div.files" # Unit Under Test - -if (VHDLVersion < 2002) then - report "VHDL version not supported." -end if - -# Testbench file(s) -vhdl test "tb/arith/arith_div_tb.vhdl" # Testbench diff --git a/tb/arith/arith_firstone_tb.files b/tb/arith/arith_firstone_tb.files deleted file mode 100644 index bb240eff7..000000000 --- a/tb/arith/arith_firstone_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_firstone.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/arith/arith_firstone_tb.vhdl" # Testbench diff --git a/tb/arith/arith_prefix_and_tb.files b/tb/arith/arith_prefix_and_tb.files deleted file mode 100644 index 612fe9948..000000000 --- a/tb/arith/arith_prefix_and_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_prefix_and.files" # Unit Under Test - -# Testbench file(s) -if (Tool = "Xilinx_iSim") then - vhdl test "tb/arith/arith_prefix_and_tb.iSim.vhdl" # Testbench -else - vhdl test "tb/arith/arith_prefix_and_tb.vhdl" # Testbench -end if diff --git a/tb/arith/arith_prefix_or_tb.files b/tb/arith/arith_prefix_or_tb.files deleted file mode 100644 index 7aed8b0e6..000000000 --- a/tb/arith/arith_prefix_or_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_prefix_or.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/arith/arith_prefix_or_tb.vhdl" # Testbench diff --git a/tb/arith/arith_prng_tb.files b/tb/arith/arith_prng_tb.files deleted file mode 100644 index cecceaa8d..000000000 --- a/tb/arith/arith_prng_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_prng.files" # Unit Under Test - -# Testbench file(s) -if ((Tool in ["Xilinx_iSim", "Xilinx_xSim"]) and (VHDLVersion < 2008)) then - vhdl test "tb/arith/arith_prng_tb.isim.vhdl" # Testbench -else - vhdl test "tb/arith/arith_prng_tb.vhdl" # Testbench -end if diff --git a/tb/arith/arith_scaler_tb.files b/tb/arith/arith_scaler_tb.files deleted file mode 100644 index bb1b57bf3..000000000 --- a/tb/arith/arith_scaler_tb.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.arith -include "src/arith/arith_scaler.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/arith/arith_scaler_tb.vhdl" # Testbench - diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl index 79d614232..5ad23a1eb 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_ReadWrite.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl index 8c6fdadc2..5e9229399 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestController.vhdl @@ -25,7 +25,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl index 9aa0f1dd0..b6076d915 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl @@ -25,7 +25,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl index 021e8d3f1..f49c5c994 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_initial.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl index 8cd94d484..aa0abe012 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_pkg.vhdl @@ -23,7 +23,7 @@ -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= diff --git a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro index 79b35b134..ad32fdb3d 100644 --- a/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro +++ b/tb/bus/axi4/AXI4Lite/AXI4Lite_Register/RunAllTests.pro @@ -19,8 +19,6 @@ # limitations under the License. # ============================================================================= -TestSuite PoC.bus.axi4.axi4lite.Register - library tb_axi4liteRegister analyze AXI4Lite_Register_pkg.vhdl diff --git a/tb/bus/axi4/AXI4Lite/RunAllTests.pro b/tb/bus/axi4/AXI4Lite/RunAllTests.pro index 2b652080a..3c84686d7 100644 --- a/tb/bus/axi4/AXI4Lite/RunAllTests.pro +++ b/tb/bus/axi4/AXI4Lite/RunAllTests.pro @@ -1,7 +1,6 @@ # ============================================================================= -# Authors: -# Iqbal Asif (PLC2 Design GmbH) -# Patrick Lehmann (PLC2 Design GmbH) +# Authors: Iqbal Asif (PLC2 Design GmbH) +# Patrick Lehmann (PLC2 Design GmbH) # # License: # ============================================================================= @@ -20,8 +19,7 @@ # limitations under the License. # ============================================================================= -# TestSuite PoC.bus.axi4.axi4Lite -# Deactivated to avoid failure on non-existing testcases +TestSuite PoC.bus.axi4.axi4Lite library tb_axi4Lite diff --git a/tb/cache/cache_cpu_tb.files b/tb/cache/cache_cpu_tb.files deleted file mode 100644 index e5c721d76..000000000 --- a/tb/cache/cache_cpu_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.cache -include "src/cache/cache_cpu.files" # UUT (Unit Under Test) - -# PoC.arith -include "src/arith/arith_prng.files" - -# Testbench files -vhdl test "tb/mem/mem_model.vhdl" # Memory Model -vhdl test "tb/cache/cache_cpu_tb.vhdl" # Testbench diff --git a/tb/cache/cache_mem_tb.files b/tb/cache/cache_mem_tb.files deleted file mode 100644 index 4f847a35f..000000000 --- a/tb/cache/cache_mem_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.cache -include "src/cache/cache_mem.files" # UUT (Unit Under Test) - -# PoC.arith -include "src/arith/arith_prng.files" - -# Testbench files -vhdl test "tb/mem/mem_model.vhdl" # Memory Model -vhdl test "tb/cache/cache_mem_tb.vhdl" # Testbench diff --git a/tb/cache/cache_par2_tb.files b/tb/cache/cache_par2_tb.files deleted file mode 100644 index 34415a0e9..000000000 --- a/tb/cache/cache_par2_tb.files +++ /dev/null @@ -1,17 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.cache -include "src/cache/cache_par2.files" # UUT (Unit Under Test) - -# Testbench file(s) -if (ToolChain = "Cocotb") then - cocotb "tb/common/utils.py" - cocotb "tb/common/lru_dict.py" - cocotb "tb/cache/cache_par2_cocotb.py" # Cocotb Testbench -else - report "Only Cocotb testbench available." -end if diff --git a/tb/cache/cache_par_tb.files b/tb/cache/cache_par_tb.files deleted file mode 100644 index 32f30b086..000000000 --- a/tb/cache/cache_par_tb.files +++ /dev/null @@ -1,17 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.cache -include "src/cache/cache_par.files" # UUT (Unit Under Test) - -# Testbench file(s) -if (ToolChain = "Cocotb") then - cocotb "tb/common/utils.py" - cocotb "tb/common/lru_dict.py" - cocotb "tb/cache/cache_par_cocotb.py" # Cocotb Testbench -else - report "Only Cocotb testbench available." -end if diff --git a/tb/common/config_tb.files b/tb/common/config_tb.files deleted file mode 100644 index 8e021ea8c..000000000 --- a/tb/common/config_tb.files +++ /dev/null @@ -1,10 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Testbench file(s) -include "src/common/common.files" - -vhdl test "tb/common/config_tb.vhdl" # Testbench diff --git a/tb/common/my_config.files b/tb/common/my_config.files deleted file mode 100644 index aa21c0694..000000000 --- a/tb/common/my_config.files +++ /dev/null @@ -1,120 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# project configuration file -vhdl poc "tb/common/my_project.vhdl" - -# board and device configuration files -# -# Generic boards -# ====================================== -if (BoardName = "GENERIC") then - vhdl poc "tb/common/my_config_GENERIC.vhdl" -elseif (BoardName = "Custom") then - path TempDirectory = ${CONFIG.DirectoryNames:TemporaryFiles} - if (Tool = "GHDL") then - path ToolDirectory = (TempDirectory / ${CONFIG.DirectoryNames:GHDLFiles}) - elseif (Tool in ["Mentor_vSim", "Cocotb_QuestaSim"]) then - path ToolDirectory = (TempDirectory / ${CONFIG.DirectoryNames:ModelSimFiles}) - else - report "Tool not supported." - end if - - path CustomConfigFile = (ToolDirectory / "my_config_Custom.vhdl") - vhdl poc CustomConfigFile - -# Altera boards -# ====================================== -# Cyclone III boards -elseif (BoardName = "DE0") then - vhdl poc "tb/common/my_config_DE0.vhdl" -#elseif (BoardName = "DE0nano") then -# vhdl poc "tb/common/my_config_DE0nano.vhdl" - -# Stratix II boards -elseif (BoardName = "S2GXAV") then - vhdl poc "tb/common/my_config_S2GXAV.vhdl" - -# Stratix IV boards -elseif (BoardName = "DE4") then - vhdl poc "tb/common/my_config_DE4.vhdl" - -# Stratix V boards -elseif (BoardName = "DE5") then - vhdl poc "tb/common/my_config_DE5.vhdl" - -# Lattice boards -# ====================================== -elseif (BoardName = "ECP5Versa") then - vhdl poc "tb/common/my_config_ECP5Versa.vhdl" - -# Xilinx boards -# ====================================== -# Spartan-3 boards -elseif (BoardName = "S3SK1000") then - vhdl poc "tb/common/my_config_S3SK1000.vhdl" - -# Spartan-3E boards -elseif (BoardName = "S3ESK500") then - vhdl poc "tb/common/my_config_S3ESK500.vhdl" - -# Spartan-6 boards -elseif (BoardName = "Atlys") then - vhdl poc "tb/common/my_config_Atlys.vhdl" - -# Spartan-7 boards -elseif (BoardName = "ArtyS7") then - vhdl poc "tb/common/my_config_ArtyS7.vhdl" - -# Zynq-7000 boards -elseif (BoardName = "ZC706") then - vhdl poc "tb/common/my_config_ZC706.vhdl" - -elseif (BoardName = "ZedBoard") then - vhdl poc "tb/common/my_config_ZedBoard.vhdl" - -elseif (BoardName = "ArtyZ7") then - vhdl poc "tb/common/my_config_ArtyZ7.vhdl" - -# Artix-7 BoardNames -elseif (BoardName = "AC701") then - vhdl poc "tb/common/my_config_AC701.vhdl" - -elseif (BoardName = "Arty") then - vhdl poc "tb/common/my_config_Arty.vhdl" - -elseif (BoardName = "Nexys4") then - vhdl poc "tb/common/my_config_Nexys4.vhdl" - -elseif (BoardName = "Nexys4DDR") then - vhdl poc "tb/common/my_config_Nexys4DDR.vhdl" - -# Kintex-7 BoardNames -elseif (BoardName = "KC705") then - vhdl poc "tb/common/my_config_KC705.vhdl" - -# Virtex-5 boards -elseif (BoardName = "ML505") then - vhdl poc "tb/common/my_config_ML505.vhdl" -elseif (BoardName = "ML506") then - vhdl poc "tb/common/my_config_ML506.vhdl" -elseif (BoardName = "XUPV5") then - vhdl poc "tb/common/my_config_XUPV5.vhdl" - -# Virtex-6 boards -elseif (BoardName = "ML605") then - vhdl poc "tb/common/my_config_ML605.vhdl" - -# Virtex-7 boards -elseif (BoardName = "VC707") then - vhdl poc "tb/common/my_config_VC707.vhdl" -elseif (BoardName = "VC709") then - vhdl poc "tb/common/my_config_VC709.vhdl" - -# other boards -else - report "Board not supported. No generic my_config.vhdl found." -end if diff --git a/tb/common/physical_tb.files b/tb/common/physical_tb.files deleted file mode 100644 index a1365e6d6..000000000 --- a/tb/common/physical_tb.files +++ /dev/null @@ -1,10 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Testbench file(s) -include "src/common/common.files" - -vhdl test "tb/common/physical_tb.vhdl" diff --git a/tb/common/strings_tb.files b/tb/common/strings_tb.files deleted file mode 100644 index 8bf79059d..000000000 --- a/tb/common/strings_tb.files +++ /dev/null @@ -1,10 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Testbench file(s) -include "src/common/common.files" - -vhdl test "tb/common/strings_tb.vhdl" # Testbench diff --git a/tb/dstruct/dstruct_deque_tb.files b/tb/dstruct/dstruct_deque_tb.files deleted file mode 100644 index d2ff1f004..000000000 --- a/tb/dstruct/dstruct_deque_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.dstruct -include "src/dstruct/dstruct_deque.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/dstruct/dstruct_deque_tb.vhdl" # Testbench diff --git a/tb/dstruct/dstruct_stack_tb.files b/tb/dstruct/dstruct_stack_tb.files deleted file mode 100644 index b2687aa6a..000000000 --- a/tb/dstruct/dstruct_stack_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.dstruct -include "src/dstruct/dstruct_stack.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/dstruct/dstruct_stack_tb.vhdl" # Testbench diff --git a/tb/fifo/fifo_cc_got_tb.files b/tb/fifo/fifo_cc_got_tb.files deleted file mode 100644 index df193d7e9..000000000 --- a/tb/fifo/fifo_cc_got_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.fifo -include "src/fifo/fifo_cc_got.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/fifo/fifo_cc_got_tb.vhdl" # Testbench diff --git a/tb/fifo/fifo_cc_got_tempput_tb.files b/tb/fifo/fifo_cc_got_tempput_tb.files deleted file mode 100644 index 4fb5626b9..000000000 --- a/tb/fifo/fifo_cc_got_tempput_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.comm -include "src/comm/comm_scramble.files" # Scrambler - -# PoC.fifo -include "src/fifo/fifo_cc_got_tempput.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/fifo/fifo_cc_got_tempput_tb.vhdl" # Testbench diff --git a/tb/fifo/fifo_ic_assembly_tb.files b/tb/fifo/fifo_ic_assembly_tb.files deleted file mode 100644 index e6124fa65..000000000 --- a/tb/fifo/fifo_ic_assembly_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.fifo -include "src/fifo/fifo_ic_assembly.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/fifo/fifo_ic_assembly_tb.vhdl" # Testbench diff --git a/tb/fifo/fifo_ic_got_tb.files b/tb/fifo/fifo_ic_got_tb.files deleted file mode 100644 index f7666efc0..000000000 --- a/tb/fifo/fifo_ic_got_tb.files +++ /dev/null @@ -1,17 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.comm -include "src/comm/comm_scramble.files" # Scrambler - -# PoC.fifo -include "src/fifo/fifo_ic_got.files" # Unit Under Test - -# PoC.comm -include "src/comm/comm_scramble.files" - -# Testbench file(s) -vhdl test "tb/fifo/fifo_ic_got_tb.vhdl" # Testbench diff --git a/tb/io/ddrio/ddrio_in_tb.files b/tb/io/ddrio/ddrio_in_tb.files deleted file mode 100644 index f242861b3..000000000 --- a/tb/io/ddrio/ddrio_in_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.io -include "src/io/ddrio/ddrio_in.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/io/ddrio/ddrio_in_tb.vhdl" # Testbench diff --git a/tb/io/ddrio/ddrio_inout_tb.files b/tb/io/ddrio/ddrio_inout_tb.files deleted file mode 100644 index 2842755fd..000000000 --- a/tb/io/ddrio/ddrio_inout_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.io -include "src/io/ddrio/ddrio_inout.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/io/ddrio/ddrio_inout_tb.vhdl" # Testbench diff --git a/tb/io/ddrio/ddrio_out_tb.files b/tb/io/ddrio/ddrio_out_tb.files deleted file mode 100644 index 1f733a3dd..000000000 --- a/tb/io/ddrio/ddrio_out_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.io -include "src/io/ddrio/ddrio_out.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/io/ddrio/ddrio_out_tb.vhdl" # Testbench diff --git a/tb/io/io_Debounce_tb.files b/tb/io/io_Debounce_tb.files deleted file mode 100644 index 581047ad1..000000000 --- a/tb/io/io_Debounce_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.io -include "src/io/io_Debounce.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/io/io_Debounce_tb.vhdl" # Testbench diff --git a/tb/io/uart/uart_rx_tb.files b/tb/io/uart/uart_rx_tb.files deleted file mode 100644 index 0beea05c0..000000000 --- a/tb/io/uart/uart_rx_tb.files +++ /dev/null @@ -1,16 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # Synchronizer - -# PoC.io.uart -vhdl poc "src/io/uart/uart.pkg.vhdl" # UART Package -vhdl poc "src/io/uart/uart_bclk.vhdl" # Bit clock generator -vhdl poc "src/io/uart/uart_rx.vhdl" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/io/uart/uart_rx_tb.vhdl" # Testbench diff --git a/tb/mem/lut/lut_Sine_tb.files b/tb/mem/lut/lut_Sine_tb.files deleted file mode 100644 index b840f0570..000000000 --- a/tb/mem/lut/lut_Sine_tb.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.lut -include "src/mem/lut/lut_Sine.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/mem/lut/lut_Sine_tb.vhdl" # Testbench - diff --git a/tb/mem/ocram/ocram_esdp_tb.files b/tb/mem/ocram/ocram_esdp_tb.files deleted file mode 100644 index 848d8864d..000000000 --- a/tb/mem/ocram/ocram_esdp_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.ocram -include "src/mem/ocram/ocram_esdp.files" # Unit Under Test - -# Testbench files -vhdl test "tb/mem/ocram/ocram_esdp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_sdp_tb.files b/tb/mem/ocram/ocram_sdp_tb.files deleted file mode 100644 index e91f4e213..000000000 --- a/tb/mem/ocram/ocram_sdp_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.ocram -include "src/mem/ocram/ocram_sdp.files" # Unit Under Test - -# Testbench files -vhdl test "tb/mem/ocram/ocram_sdp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_sdp_wf_tb.files b/tb/mem/ocram/ocram_sdp_wf_tb.files deleted file mode 100644 index 9e04ce11c..000000000 --- a/tb/mem/ocram/ocram_sdp_wf_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.ocram -include "src/mem/ocram/ocram_sdp_wf.files" # Unit Under Test - -# Testbench files -vhdl test "tb/mem/ocram/ocram_sdp_wf_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_sp_tb.files b/tb/mem/ocram/ocram_sp_tb.files deleted file mode 100644 index 49142dcd3..000000000 --- a/tb/mem/ocram/ocram_sp_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.ocram -include "src/mem/ocram/ocram_sp.files" # Unit Under Test - -# Testbench files -vhdl test "tb/mem/ocram/ocram_sp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_tdp_tb.files b/tb/mem/ocram/ocram_tdp_tb.files deleted file mode 100644 index 0371b8e8b..000000000 --- a/tb/mem/ocram/ocram_tdp_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.ocram -include "src/mem/ocram/ocram_tdp.files" # Unit Under Test - -# Testbench files -vhdl test "tb/mem/ocram/ocram_tdp_tb.vhdl" # Testbench diff --git a/tb/mem/ocram/ocram_tdp_wf_tb.files b/tb/mem/ocram/ocram_tdp_wf_tb.files deleted file mode 100644 index e52d8e2c3..000000000 --- a/tb/mem/ocram/ocram_tdp_wf_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.mem.ocram -include "src/mem/ocram/ocram_tdp_wf.files" # Unit Under Test - -# Testbench files -vhdl test "tb/mem/ocram/ocram_tdp_wf_tb.vhdl" # Testbench diff --git a/tb/misc/gearbox/gearbox_down_cc_tb.files b/tb/misc/gearbox/gearbox_down_cc_tb.files deleted file mode 100644 index 9e69ae449..000000000 --- a/tb/misc/gearbox/gearbox_down_cc_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.misc.gearbox -include "src/misc/gearbox/gearbox_down_cc.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/misc/gearbox/gearbox_down_cc_tb.vhdl" # Testbench diff --git a/tb/misc/gearbox/gearbox_down_dc_tb.files b/tb/misc/gearbox/gearbox_down_dc_tb.files deleted file mode 100644 index 94e6428f5..000000000 --- a/tb/misc/gearbox/gearbox_down_dc_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.misc.gearbox -include "src/misc/gearbox/gearbox_down_dc.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/misc/gearbox/gearbox_down_dc_tb.vhdl" # Testbench diff --git a/tb/misc/gearbox/gearbox_up_cc_tb.files b/tb/misc/gearbox/gearbox_up_cc_tb.files deleted file mode 100644 index b8871e018..000000000 --- a/tb/misc/gearbox/gearbox_up_cc_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.misc.gearbox -include "src/misc/gearbox/gearbox_up_cc.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/misc/gearbox/gearbox_up_cc_tb.vhdl" # Testbench diff --git a/tb/misc/gearbox/gearbox_up_dc_tb.files b/tb/misc/gearbox/gearbox_up_dc_tb.files deleted file mode 100644 index bcf36a3c0..000000000 --- a/tb/misc/gearbox/gearbox_up_dc_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.misc.gearbox -include "src/misc/gearbox/gearbox_up_dc.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/misc/gearbox/gearbox_up_dc_tb.vhdl" # Testbench diff --git a/tb/misc/stat/stat_Average_tb.files b/tb/misc/stat/stat_Average_tb.files deleted file mode 100644 index ab33a13f7..000000000 --- a/tb/misc/stat/stat_Average_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.stat -include "src/misc/stat/stat_Average.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/stat/stat_Average_tb.vhdl" # Testbench diff --git a/tb/misc/stat/stat_Histogram_tb.files b/tb/misc/stat/stat_Histogram_tb.files deleted file mode 100644 index 9874c022c..000000000 --- a/tb/misc/stat/stat_Histogram_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.stat -include "src/misc/stat/stat_Histogram.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/stat/stat_Histogram_tb.vhdl" # Testbench diff --git a/tb/misc/stat/stat_Maximum_tb.files b/tb/misc/stat/stat_Maximum_tb.files deleted file mode 100644 index 17f71af5f..000000000 --- a/tb/misc/stat/stat_Maximum_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.stat -include "src/misc/stat/stat_Maximum.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/stat/stat_Maximum_tb.vhdl" # Testbench diff --git a/tb/misc/stat/stat_Minimum_tb.files b/tb/misc/stat/stat_Minimum_tb.files deleted file mode 100644 index 23f4e9750..000000000 --- a/tb/misc/stat/stat_Minimum_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.stat -include "src/misc/stat/stat_Minimum.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/stat/stat_Minimum_tb.vhdl" # Testbench diff --git a/tb/sim/sim_ClockGenerator_tb.files b/tb/sim/sim_ClockGenerator_tb.files deleted file mode 100644 index 09436642d..000000000 --- a/tb/sim/sim_ClockGenerator_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# Testbench file(s) -vhdl test "tb/sim/sim_ClockGenerator_tb.vhdl" # Testbench diff --git a/tb/sim/sim_VCDParser_tb.files b/tb/sim/sim_VCDParser_tb.files deleted file mode 100644 index 566a42d05..000000000 --- a/tb/sim/sim_VCDParser_tb.files +++ /dev/null @@ -1,12 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # Load common packages -vhdl PoC "src/sim/sim_VCDParser.vhdl" # VCD parser - -# Testbench file(s) -vhdl test "tb/sim/sim_VCDParser_tb.vhdl" # Testbench diff --git a/tb/sim/sim_Waveform_tb.files b/tb/sim/sim_Waveform_tb.files deleted file mode 100644 index 76781e660..000000000 --- a/tb/sim/sim_Waveform_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Common PoC packages for configuration, synthesis and simulation -include "src/common/common.files" # load common packages - -# Testbench file(s) -vhdl test "tb/sim/sim_Waveform_tb.vhdl" # Testbench diff --git a/tb/sort/sort_lru_cache_tb.files b/tb/sort/sort_lru_cache_tb.files deleted file mode 100644 index b7a7c6cd1..000000000 --- a/tb/sort/sort_lru_cache_tb.files +++ /dev/null @@ -1,21 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -if (ToolChain != "Cocotb") then - include "lib/OSVVM.files" # -end if - -# PoC.sort -include "src/sort/sort_lru_cache.files" # UUT (Unit Under Test) - -# Testbench file(s) -if (ToolChain = "Cocotb") then - cocotb "tb/common/lru_dict.py" - cocotb "tb/sort/sort_lru_cache_cocotb.py" # Cocotb Testbench -else - vhdl test "tb/sort/sort_lru_cache_tb.vhdl" # Testbench -end if diff --git a/tb/sort/sort_lru_list_tb.files b/tb/sort/sort_lru_list_tb.files deleted file mode 100644 index 113c75810..000000000 --- a/tb/sort/sort_lru_list_tb.files +++ /dev/null @@ -1,16 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.sort -include "src/sort/sort_lru_list.files" # UUT (Unit Under Test) - -# Testbench file(s) -if (ToolChain = "Cocotb") then - cocotb "tb/common/lru_dict.py" - cocotb "tb/sort/sort_lru_list_cocotb.py" # Cocotb Testbench -else - report "Only Cocotb testbench available." -end if diff --git a/tb/sort/sortnet/sortnet_BitonicSort_tb.files b/tb/sort/sortnet/sortnet_BitonicSort_tb.files deleted file mode 100644 index a4ad125c7..000000000 --- a/tb/sort/sortnet/sortnet_BitonicSort_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.sort.sortnet -include "src/sort/sortnet/sortnet_BitonicSort.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/sort/sortnet/sortnet_tb.pkg.vhdl" # Testbench package -vhdl test "tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files b/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files deleted file mode 100644 index ad73d43f9..000000000 --- a/tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.sort.sortnet -include "src/sort/sortnet/sortnet_OddEvenMergeSort.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/sort/sortnet/sortnet_tb.pkg.vhdl" # Testbench package -vhdl test "tb/sort/sortnet/sortnet_OddEvenMergeSort_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_OddEvenSort_tb.files b/tb/sort/sortnet/sortnet_OddEvenSort_tb.files deleted file mode 100644 index 2aab8cf09..000000000 --- a/tb/sort/sortnet/sortnet_OddEvenSort_tb.files +++ /dev/null @@ -1,15 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.sort.sortnet -include "src/sort/sortnet/sortnet_OddEvenSort.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/sort/sortnet/sortnet_tb.pkg.vhdl" # Testbench package -vhdl test "tb/sort/sortnet/sortnet_OddEvenSort_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.files b/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.files deleted file mode 100644 index 286a587c8..000000000 --- a/tb/sort/sortnet/sortnet_Stream_Adapter2_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.sort.sortnet -include "src/sort/sortnet/sortnet_Stream_Adapter2.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/sort/sortnet/sortnet_Stream_Adapter2_tb.vhdl" # Testbench diff --git a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.files b/tb/sort/sortnet/sortnet_Stream_Adapter_tb.files deleted file mode 100644 index 762a01db7..000000000 --- a/tb/sort/sortnet/sortnet_Stream_Adapter_tb.files +++ /dev/null @@ -1,14 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# Load external vendor libraries -include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) - -# PoC.sort.sortnet -include "src/sort/sortnet/sortnet_Stream_Adapter.files" # UUT (Unit Under Test) - -# Testbench file(s) -vhdl test "tb/sort/sortnet/sortnet_Stream_Adapter_tb.vhdl" # Testbench diff --git a/tb/sync/sync_Bits_tb.files b/tb/sync/sync_Bits_tb.files deleted file mode 100644 index 3b47a5d2f..000000000 --- a/tb/sync/sync_Bits_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.sync -include "src/misc/sync/sync_Bits.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/sync/sync_Bits_tb.vhdl" # Testbench diff --git a/tb/sync/sync_Command_tb.files b/tb/sync/sync_Command_tb.files deleted file mode 100644 index a7555f54a..000000000 --- a/tb/sync/sync_Command_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.sync -include "src/misc/sync/sync_Command.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/sync/sync_Command_tb.vhdl" # Testbench diff --git a/tb/sync/sync_Reset_tb.files b/tb/sync/sync_Reset_tb.files deleted file mode 100644 index 982037da3..000000000 --- a/tb/sync/sync_Reset_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.sync -include "src/misc/sync/sync_Reset.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/sync/sync_Reset_tb.vhdl" # Testbench diff --git a/tb/sync/sync_Strobe_tb.files b/tb/sync/sync_Strobe_tb.files deleted file mode 100644 index 44db1b8fa..000000000 --- a/tb/sync/sync_Strobe_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.sync -include "src/misc/sync/sync_Strobe.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/sync/sync_Strobe_tb.vhdl" # Testbench diff --git a/tb/sync/sync_Vector_tb.files b/tb/sync/sync_Vector_tb.files deleted file mode 100644 index e6eba4153..000000000 --- a/tb/sync/sync_Vector_tb.files +++ /dev/null @@ -1,11 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -# PoC.misc.sync -include "src/misc/sync/sync_Vector.files" # Unit Under Test - -# Testbench file(s) -vhdl test "tb/misc/sync/sync_Vector_tb.vhdl" # Testbench diff --git a/tools/git/preSynth_GitVersionRegister_Vivado.tcl b/tools/git/preSynth_GitVersionRegister_Vivado.tcl new file mode 100644 index 000000000..aded16ea3 --- /dev/null +++ b/tools/git/preSynth_GitVersionRegister_Vivado.tcl @@ -0,0 +1,132 @@ +## EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +## vim: tabstop=2:shiftwidth=2:noexpandtab +## kate: tab-width 2; replace-tabs off; indent-width 2; +## ============================================================================= +## Authors: Stefan Unrein +## Max Kraft-Kugler +## Patrick Lehmann +## Iqbal Asif +## +## Script: preSynth_GitVersionRegister_Vivado.tcl +## +## Description: +## ------------------------------------- +## Use as pre-synthesis tcl file to create the memory file for the +## AXI4Lite_GitVersionRegister. +## +## The relative paths are used as for the default project-folder-structure of PoC +## +## License: +## ============================================================================= +## Copyright 2025-2025 The PoC-Library Authors +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +## ============================================================================= + +puts "BuildVersion: Running script..." + +# Script configuration +# Go up by three folders from ./project/my_project.runs/synth_1 +set version_file ../../../temp/GitVersion.mem; + +# Project Versioning +if {[catch {open "../../../Project_Version" r} results]} { + set Project_Major 0 + set Project_Minor 0 + set Project_Release [exec git rev-list --count HEAD] +} else { + set project_version_file [open "../../../Project_Version" r] + set project_version [read $project_version_file] + close $project_version_file + set project_version [split $project_version "."] + set Project_Major [lindex $project_version 0] + set Project_Minor [lindex $project_version 1] + set Project_Release [lindex $project_version 2] + if {$Project_Release eq ""} {set Project_Release [exec git rev-list --count HEAD]} +} + +# Constants +set VersionOfVersionReg 1 + +# Build date +set systemTime [clock seconds] +set BuildDate_Day [clock format $systemTime -format {%d}] +set BuildDate_Month [clock format $systemTime -format {%m}] +set BuildDate_Year [clock format $systemTime -format {%Y}] + +# Vivado information +set VivadoVersion [version -short] +set VivadoVersion_Year [string range $VivadoVersion 0 3] +set VivadoVersion_Release [string range $VivadoVersion 5 5] +set VivadoVersion_SubRelease [string range $VivadoVersion 7 7] + +if {$VivadoVersion_SubRelease eq ""} {set VivadoVersion_SubRelease 0} + +set ProjectName [get_property NAME [current_project]] + +# Git information +set git_hash [exec git rev-parse HEAD] +set git_branch [exec git symbolic-ref --short HEAD] +set git_remote [lindex [exec git remote] 0] +set git_url [string range [exec git remote get-url $git_remote] 19 127] + +if {[catch {exec git status -s | findstr /b /i ".m"} results]} {set dirty_modified 0} else {set dirty_modified 1} +if {[catch {exec git status -s | findstr /b /i "??"} results]} {set dirty_untracked 0} else {set dirty_untracked 1} + +set GitDateTime [exec git show -s --format=%ci HEAD] +set GitDate_Year [string range $GitDateTime 0 3] +set GitDate_Month [string range $GitDateTime 5 6] +set GitDate_Day [string range $GitDateTime 8 9] +set GitTime_Hour [string range $GitDateTime 11 12] +set GitTime_Min [string range $GitDateTime 14 15] +set GitTime_Sec [string range $GitDateTime 17 18] +set GitTime_Zone [string range $GitDateTime 20 22] + +# Modules +set NumberModule 0 + + +puts "BuildVersion: Writing Version Data to $version_file" + +set fo [open $version_file w] + +# Automated Build Version Script +puts $fo "$BuildDate_Day +$BuildDate_Month +$BuildDate_Year +$NumberModule +$VersionOfVersionReg +$VivadoVersion_Year +$VivadoVersion_Release +$VivadoVersion_SubRelease +$ProjectName +$Project_Major +$Project_Minor +$Project_Release +0 +$dirty_untracked +$dirty_modified +$git_hash +$GitDate_Day +$GitDate_Month +$GitDate_Year +$GitTime_Hour +$GitTime_Min +$GitTime_Sec +$GitTime_Zone +$git_branch +$git_url +" +close $fo + +puts "==============" diff --git a/ucf/fifo/fifo_ic_got.xdc b/ucf/fifo/fifo_ic_got.xdc index 68230d8bd..395ff7769 100644 --- a/ucf/fifo/fifo_ic_got.xdc +++ b/ucf/fifo/fifo_ic_got.xdc @@ -2,14 +2,7 @@ # To achieve this, set property SCOPED_TO_REF to fifo_ic_got within the Vivado project. # Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. -# set max delay between register IPz and IPs to lower clock period -set_max_delay -from [get_cells -regexp {IPz_reg\[\d+\]}] -to [get_cells -regexp {IPs_reg\[\d+\]}] -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {IPz_reg[0]/C}]]], [get_property period [get_clocks -of_objects [get_pins {IPs_reg[0]/C}]]])"] - # set max delay between regfile write and read side lower clock period -# TODO a critical warning is issued if DATA_REG = false -set_max_delay -from [get_cells -regexp {gSmall\.regfile.*/RAM.*}] -to [get_cells -regexp {gSmall\.do_reg\[\d+\]}] -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {IPz_reg[0]/C}]]], [get_property period [get_clocks -of_objects [get_pins {IPs_reg[0]/C}]]])"] -# TODO a critical warning is issued if DATA_REG = false, or DATA_REG = true, but RAM is small and mapped to LUTs -set_max_delay -from [get_cells -regexp {gLarge\.ram/gInfer.ram_reg.*/RAM.*}] -to [get_cells -regexp {gLarge\.ram/gInfer\.q_reg\[\d+\]}] -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {IPz_reg[0]/C}]]], [get_property period [get_clocks -of_objects [get_pins {IPs_reg[0]/C}]]])"] - -# set max delay between register OP0 and OPs to lower clock period -set_max_delay -from [get_cells -regexp {OP0_reg\[\d+\]}] -to [get_cells -regexp {OPs_reg\[\d+\]}] -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {OP0_reg[0]/C}]]], [get_property period [get_clocks -of_objects [get_pins {OPs_reg[0]/C}]]])"] +set_max_delay -from [get_cells -regexp {gSmall\.regfile.*/.*|gLarge\.ram/gInfer.ram_reg.*/.*}] \ + -to [get_cells -regexp {gSmall\.do_reg\[\d+\]|gLarge\.ram/gInfer\.q_reg\[\d+\]}] \ + -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {Ful_reg/C}]]], [get_property period [get_clocks -of_objects [get_pins {Avl_reg/C}]]])"] diff --git a/xst/xil/mig/mig_Atlys_1x128.files b/xst/xil/mig/mig_Atlys_1x128.files deleted file mode 100644 index fa99ef0f4..000000000 --- a/xst/xil/mig/mig_Atlys_1x128.files +++ /dev/null @@ -1,18 +0,0 @@ -# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -# vim: tabstop=2:shiftwidth=2:noexpandtab -# kate: tab-width 2; replace-tabs off; indent-width 2; -# ============================================================================== -# Note: all files are relative to PoC root directory -# -if (BoardName = "Atlys") then - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/iodrp_controller.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/iodrp_mcb_controller.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/mcb_raw_wrapper.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/mcb_soft_calibration_top.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/mcb_soft_calibration.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/memc3_infrastructure.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/memc3_wrapper.vhd" - vhdl poc "netlist/XC6SLX45-3CSG324/xil/mig/mig_Atlys_1x128_top.vhd" -else - report "This memory controller is configured for the Digilent Atlys board." -end if diff --git a/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.files b/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.files deleted file mode 100644 index 23373d953..000000000 --- a/xst/xil/mig/mig_KC705_MT8JTF12864HZ_1G6.files +++ /dev/null @@ -1,52 +0,0 @@ -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_bank_queue.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ui_top.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_wrlvl.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ecc_buf.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_init.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_tempmon.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_mc_phy_wrapper.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_bank_compare.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_arb_select.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_arb_mux.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_mc_phy.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_clk_ibuf.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_tempmon.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ui_rd_data.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_col_mach.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_iodelay_ctrl.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_bank_common.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ui_wr_data.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_infrastructure.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_bank_state.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_mc.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ecc_gen.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ecc_merge_enc.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_4lanes.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_mem_intfc.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_bank_cntrl.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_wrcal.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_rank_cntrl.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_calib_top.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_bank_mach.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_memc_ui_top_std.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_if_post_fifo.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_rdlvl.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_dqs_found_cal.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_prbs_gen.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ecc_dec_fix.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_rank_mach.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_oclkdelay_cal.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_arb_row_col.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_of_pre_fifo.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_rank_common.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_byte_lane.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_round_robin_arb.v" -vhdl poc "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_phy_top.vhd" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ddr_byte_group_io.v" -verilog "netlist/XC7K325T-2FFG900/xil/mig/mig_7series_v1_9_ui_cmd.v" -vhdl poc "netlist/XC7K325T-2FFG900/xil/mig/mig_KC705_MT8JTF12864HZ_1G6_top.vhd" -